SO T2 23 BUK9840-55 N-channel TrenchMOS logic level FET 16 March 2016 Product data sheet 1. General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. 2. Features and benefits • • • AEC Q101 compliant Electrostatically robust due to integrated protection diodes Low conduction losses due to low on-state resistance 3. Applications • Automotive and general purpose power switching 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 55 V ID drain current Tsp = 25 °C - - 10.7 A Ptot total power dissipation Tsp = 25 °C; Fig. 4 - - 8.3 W VGS = 5 V; ID = 5 A; Tj = 25 °C - 30 40 mΩ ID = 3.6 A; Vsup ≤ 25 V; RGS = 50 Ω; - - 60 mJ Static characteristics RDSon drain-source on-state resistance Avalanche ruggedness EDS(AL)S non-repetitive drainsource avalanche energy VGS = 5 V; Tj(init) = 25 °C; unclamped Scan or click this QR code to view the latest information for this product BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain 3 S source 4 D drain Simplified outline Graphic symbol D 4 G 1 2 3 SC-73 (SOT223) S sym116 6. Ordering information Table 3. Ordering information Type number Package Name Description Version BUK9840-55 SC-73 plastic surface-mounted package with increased heatsink; 4 leads SOT223 BUK9840-55/CU SC-73 plastic surface-mounted package with increased heatsink; 4 leads SOT223 7. Marking Table 4. Marking codes Type number Marking code BUK9840-55 94055 BUK9840-55/CU xxYWW 94055 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 55 V VDGR drain-gate voltage RGS = 20 kΩ - 55 V VGS gate-source voltage -10 10 V Ptot total power dissipation Tsp = 25 °C; Fig. 4 - 8.3 W ID drain current Tsp = 25 °C - 10.7 A Tsp = 100 °C - 6.8 A BUK9840-55 Product data sheet All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 2 / 11 BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Max Unit IDM peak drain current Tsp = 25 °C; pulsed - 40 A Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Source-drain diode IS source current Tsp = 25 °C - 10.7 A ISM peak source current pulsed; Tsp = 25 °C - 40 A ID = 3.6 A; Vsup ≤ 25 V; RGS = 50 Ω; - 60 mJ - 2 kV Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 5 V; Tj(init) = 25 °C; unclamped Electrostatic discharge Vesd electrostatic discharge voltage HBM; C = 100 pF; R = 1.5 kΩ 003aaf254 100 ID (%) 80 003aaf255 102 RDS(on) = VDS / ID IDM (A) tp = 1 µs 10 µs 100 µs 10 60 1 ms D.C. 40 10 ms 1 100 ms 20 0 0 40 80 120 Tmb (°C) 160 10- 1 10- 1 VGS ≥ 10 V Fig. 1. Product data sheet 10 VDS (V) 102 Tsp = 25 °C; IDM is single pulse Normalized continuous drain current as a function of solder point temperature BUK9840-55 1 Fig. 2. Safe operating area; continuous and peak drain currents as a function of drain-source voltage All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 3 / 11 BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET 003aaf267 100 WDSS (%) 80 60 60 40 40 20 20 0 20 40 60 80 100 120 0 140 160 T(mb) (°C) ID = 3.6 A Fig. 3. 003aaf253 100 Pder (%) 80 Fig. 4. 0 40 80 120 Tmb (°C) 160 Normalized total power dissipation as a function of solder point temperature Normalised drain-source non-repetitive avalanche energy rating; avalanche energy as a function of mounting base temperature 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-sp) thermal resistance from junction to solder point Mounted on any printed-circuit board - 12 15 K/W Rth(j-a) thermal resistance from junction to ambient Mounted on a printed-circuit - 120 - K/W 003aaf256 102 Zth(j-mb) (K/W) 10 δ = 0.5 0.2 0.1 1 0.05 0.02 10- 1 δ= 0 10- 2 10- 6 Fig. 5. P 10- 5 tp 10- 4 10- 3 10- 2 tp T t T 10- 1 1 10 tp (s) Transient thermal impedance from junction to solder point as a function of pulse duration BUK9840-55 Product data sheet All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 4 / 11 BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 55 - - V ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 50 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 150 °C 0.6 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C - - 2.3 V ID = 1 mA; VDS = VGS; Tj = 25 °C 1 1.5 2 V VDS = 55 V; VGS = 0 V; Tj = 150 °C - - 100 µA VDS = 55 V; VGS = 0 V; Tj = 25 °C - 0.05 10 µA VGS = 5 V; VDS = 0 V; Tj = 25 °C - 0.02 1 µA VGS = -5 V; VDS = 0 V; Tj = 25 °C - 0.02 1 µA VGS = 5 V; VDS = 0 V; Tj = 150 °C - - 5 µA VGS = -5 V; VDS = 0 V; Tj = 150 °C - - 5 µA drain-source on-state resistance VGS = 5 V; ID = 5 A; Tj = 150 °C - - 74 mΩ VGS = 5 V; ID = 5 A; Tj = 25 °C - 30 40 mΩ gate-source breakdown voltage VDS = 0 V; Tj = 25 °C; IG = 1 mA 10 - - V VDS = 0 V; Tj = 25 °C; IG = -1 mA 10 - - V Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon V(BR)GSS drain leakage current gate leakage current Dynamic characteristics Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 1050 1400 pF Coss output capacitance Tj = 25 °C - 205 245 pF Crss reverse transfer capacitance - 110 150 pF td(on) turn-on delay time VDS = 30 V; RL = 3.3 Ω; VGS = 5 V; - 17 25 ns tr rise time RG(ext) = 10 Ω; Tj = 25 °C; ID = 9 A - 65 100 ns td(off) turn-off delay time - 70 105 ns tf fall time - 70 105 ns gfs transfer conductance VDS = 25 V; ID = 5 A; Tj = 25 °C 11 19 - S Source-drain diode VSD source-drain voltage IS = 5 A; VGS = 0 V; Tj = 25 °C - 0.85 1.1 V trr reverse recovery time IS = 5 A; dIS/dt = -100 A/µs; - 45 - ns Qr recovered charge VGS = -10 V; VDS = 30 V; Tj = 25 °C - 0.3 - µC BUK9840-55 Product data sheet All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 5 / 11 BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET 003aaf257 20 ID (A) 10 5 4 3.6 15 10 003aaf258 80 VGS (V) = 3.4 VGS (V) = 3.0 RDS(on) (mΩ) 3.2 60 3.2 3.0 3.4 5 2.2 3.6 4.0 5.0 40 2.8 2.6 2.4 0 Fig. 6. 0 2 4 6 8 VDS (V) 20 10 5 10 15 20 ID (A) 25 Tj = 25 °C Tj = 25 °C Output characteristics: drain current as a Fig. 7. function of drain-source voltage; typical values Drain-source on-state resistance as a function of drain current; typical values 003aaf259 20 003aaf260 25 ID (A) gfs (S) 15 20 10 15 5 0 Tj = 150 °C 0 1 10 Tj = 25 °C 2 3 VGS (V) 5 4 VDS > ID x RDSon Fig. 8. 0 Fig. 9. 003aaf261 4 8 12 16 20 003aaf262 2.5 VGS(th) (V) a ID (A) Forward transconductance as a function of drain current; typical values Transfer characteristics: drain current as a function of gate-source voltage; typical values 2.0 0 maximum 2.0 1.5 typical 1.5 1.0 minimum 1.0 0.5 - 100 0 100 Tmb (°C) 0.5 - 100 200 Fig. 10. Normalized drain-source on-state resistance factor as a function of junction temperature BUK9840-55 Product data sheet 0 100 Tj (°C) 200 ID = 1 mA; VDS = VGS Fig. 11. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 6 / 11 BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET 003aaf263 10- 1 ID (A) 10- 2 003aaf264 2.5 C (nF) 2.0 Ciss Coss 10- 3 1.5 2% 10- 4 typical Crss 98 % 1.0 10- 5 0.5 10- 6 0.5 1.0 1.5 2.0 VGS (V) 0 10- 2 2.5 Tj = 25 °C; VDS = VGS 10- 1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig. 12. Sub-threshold drain current as a function of gate-source voltage Fig. 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aaf265 6 003aaf266 20 IF (A) VGS (V) 15 4 VDS = 14 V VDS = 44 V 10 2 Tj = 150 °C 5 0 0 5 10 15 QG (nC) 0 20 Tj = 25 °C; ID = 9 A Product data sheet 0.4 0.8 VSDS (V) 1.2 VGS = 0 V Fig. 14. Gate-source voltage as a function of gate charge; typical values BUK9840-55 0 Tj = 25 °C Fig. 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 7 / 11 BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET 11. Package outline Plastic surface-mounted package with increased heatsink; 4 leads D SOT223 E B A X c y HE v M A b1 4 Q A A1 1 2 e1 3 Lp bp w M B detail X e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y mm 1.8 1.5 0.10 0.01 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 4.6 2.3 7.3 6.7 1.1 0.7 0.95 0.85 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT223 JEITA SC-73 EUROPEAN PROJECTION ISSUE DATE 04-11-10 06-03-16 Fig. 16. Package outline SC-73 (SOT223) BUK9840-55 Product data sheet All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 8 / 11 BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. Legal information 12.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 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In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 12.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. BUK9840-55 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 9 / 11 BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE, MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK9840-55 Product data sheet All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 10 / 11 BUK9840-55 NXP Semiconductors N-channel TrenchMOS logic level FET 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 5 11 Package outline ..................................................... 8 12 12.1 12.2 12.3 12.4 Legal information ...................................................9 Data sheet status ................................................. 9 Definitions .............................................................9 Disclaimers ...........................................................9 Trademarks ........................................................ 10 © NXP Semiconductors N.V. 2016. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 March 2016 BUK9840-55 Product data sheet All information provided in this document is subject to legal disclaimers. 16 March 2016 © NXP Semiconductors N.V. 2016. All rights reserved 11 / 11