Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W4x5.20
4x5 Array 20 Ball Wafer Level Chip Scale Package (WLCSP)
Rev 1 8/09
2.545 ± 0.02
X
2.00
20X 0.32 ± 0.03
Y
4
0.25
3
1.50
2.045 ± 0.02
2
1
0.50
0.10
PIN 1 (A1 CORNER)
TOP VIEW
E
D
C
B
A
(4X)
0.50
BOTTOM VIEW
PACKAGE OUTLINE
0.33
3
0.025 BSC
0.30 ± 0.015
0.23 ± 0.015
0.32 ± 0.03
SEATING PLANE
0.05 Z
0.10 M Z X Y
0.05 M Z
0.28
Z
SIDE VIEW
0.50
4 NSMD
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994,
and JESD 95-1 SPP-10.
1
3.
Back side coat 0.25mm thick applied to CSP package top.
4.
NSMD refers to non-solder mask defined pad design per
Intersil tech brief www.intersil.com/data/tb/TB451.pdf