Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W5x5.25B
5X5 ARRAY 25 BALL WITH 0.40 PITCH WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
Rev 2, 12/11
X
Y
1.60
2.11±0.03
25x 0.225±0.03
E
D
0.40
2.13±0.03
1.60
C
B
0.265
A
0.10
PIN 1 (A1 CORNER)
(4X)
TOP VIEW
1
2
3
4
0.254
5
0.40
BOTTOM VIEW
0.25
PACKAGE
OUTLINE
0.305±0.025
0.225
0.55 MAX
0.40
Z SEATING PLANE
0.19±0.03
3
0.25±0.03
NSMD
TYPICAL RECOMMENDED LAND PATTERN
0.10
0.05
ZXY
Z
0.05 Z
SIDE VIEW
NOTES:
1. All dimensions are in millimeters.
2. Dimension and tolerance per ASMEY 14.5M-1994,
and JESD 95-1 SPP-010.
3. NSMD refers to Non-Solder Mask Defined pad design per
Intersil Tech Brief TB451 located at:
http://www.intersil.com/data/tb/tb451.pdf.
1

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