HUF75823D3, HUF75823D3S
TM
Data Sheet
April 2000
File Number
4847
14A, 150V, 0.150 Ohm, N-Channel,
UltraFET Power MOSFET
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN
(FLANGE)
HUF75823D3S
HUF75823D3
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.150Ω, VGS = 10V
• Simulation Models
- Temperature Compensated PSPICE™ and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
Ordering Information
D
PART NUMBER
G
BRAND
TO-251AA
75823D
HUF75823D3S
TO-252AA
75823D
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF75823D3ST.
S
Absolute Maximum Ratings
PACKAGE
HUF75823D3
TC = 25oC, Unless
Otherwise Specified
HUF75823D3, HUF75823D3S
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
150
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
150
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS
±20
V
Drain Current
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
14
10
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
0.57
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HUF75823D3, HUF75823D3S
TC = 25oC, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
150
-
-
V
VDS = 140V, VGS = 0V
-
-
1
µA
VDS = 135V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BVDSS
IDSS
Gate to Source Leakage Current
IGSS
ID = 250µA, VGS = 0V (Figure 11)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
Drain to Source On Resistance
rDS(ON)
ID = 14A, VGS = 10V (Figure 9)
-
0.125
0.150
Ω
TO-251 and TO-252
-
-
1.76
oC/W
-
-
100
oC/W
-
-
48
ns
-
7.7
-
ns
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 75V, ID = 14A
VGS = 10V,
RGS = 12Ω
(Figures 18, 19)
-
24
-
ns
td(OFF)
-
45
-
ns
tf
-
26
-
ns
tOFF
-
-
105
ns
-
43
54
nC
-
23
29
nC
-
1.5
1.9
nC
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
VDD = 75V,
ID = 14A,
Ig(REF) = 1.0mA
(Figures 13, 16, 17)
Gate to Source Gate Charge
Qgs
-
3.4
-
nC
Gate to Drain "Miller" Charge
Qgd
-
8.8
-
nC
-
800
-
pF
-
180
-
pF
-
65
-
pF
MIN
TYP
MAX
UNITS
ISD = 14A
-
-
1.25
V
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Reverse Recovery Time
Reverse Recovered Charge
2
TEST CONDITIONS
ISD = 7A
-
-
1.00
V
trr
ISD = 14A, dISD/dt = 100A/µs
-
-
150
ns
QRR
ISD = 14A, dISD/dt = 100A/µs
-
-
750
nC
HUF75823D3, HUF75823D3S
Typical Performance Curves
15
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
12
VGS = 10V
9
6
3
0
25
175
50
75
TC , CASE TEMPERATURE (oC)
2
THERMAL IMPEDANCE
ZθJC, NORMALIZED
1
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
IDM, PEAK CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
175 - TC
I = I25
150
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
3
10-1
100
101
HUF75823D3, HUF75823D3S
Typical Performance Curves
(Continued)
ID, DRAIN CURRENT (A)
100
IAS, AVALANCHE CURRENT (A)
80
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
1
10ms
100
10
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
TJ = -55oC
20
VGS = 5V
16
12
8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
4
TJ = 25oC
0
3
4
5
VGS, GATE TO SOURCE VOLTAGE (V)
0
6
0
FIGURE 7. TRANSFER CHARACTERISTICS
1
2
3
VDS, DRAIN TO SOURCE VOLTAGE (V)
4
FIGURE 8. SATURATION CHARACTERISTICS
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250µA
2.4
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.8
10
VGS = 10V
VGS = 6V
24
8
2
1
28
16
4
0.1
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
20
TJ = 175oC
0.01
tAV, TIME IN AVALANCHE (ms)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
12
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
24
1
300
VDS, DRAIN TO SOURCE VOLTAGE (V)
28
STARTING TJ = 150oC
0.5
0.001
0.5
1
STARTING TJ = 25oC
10
2.0
1.6
1.2
1.0
0.8
0.8
VGS = 10V, ID = 14A
0.4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
200
0.6
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
HUF75823D3, HUF75823D3S
Typical Performance Curves
(Continued)
3000
ID = 250µA
VGS = 0V, f = 1MHz
1000
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
1.1
1.0
CISS = CGS + CGD
COSS ≅ CDS + CGD
100
CRSS = CGD
0.9
-80
-40
0
40
80
10
0.1
200
160
120
1.0
TJ , JUNCTION TEMPERATURE (oC)
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VGS , GATE TO SOURCE VOLTAGE (V)
10
VDD = 75V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 14A
ID = 7A
2
0
5
0
10
15
Qg, GATE CHARGE (nC)
20
25
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
5
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
HUF75823D3, HUF75823D3S
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
VGS = 10V
VGS
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
6
10%
50%
50%
PULSE WIDTH
FIGURE 19. SWITCHING TIME WAVEFORM
HUF75823D3, HUF75823D3S
PSPICE Electrical Model
.SUBCKT HUF75823 2 1 3 ;
rev 18 February 2000
CA 12 8 1.2e-9
CB 15 14 1.3e-9
CIN 6 8 7.4e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
17
EBREAK 18
50
-
IT 8 17 1
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.7e-2
RGATE 9 20 2.13
RLDRAIN 2 5 10
RLGATE 1 9 31.1
RLSOURCE 3 7 37.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.0e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1.0e-9
LGATE 1 9 3.11e-9
LSOURCE 3 7 3.72e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 157.1
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S2A
S1A
12
S1B
CA
RBREAK
15
14
13
13
8
17
18
RVTEMP
S2B
13
CB
6
8
VBAT
5
8
EDS
-
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
-
IT
14
+
+
EGS
19
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*25),3))}
.MODEL DBODYMOD D (IS = 6.5e-13 RS = 1.06e-2 XTI = 5 TRS1 = 2.4e-3 TRS2 = 1.5e-6 CJO = 8.0e-10 TT = 1.1e-7 M = 0.6)
.MODEL DBREAKMOD D (RS = 2.0 TRS1 = 2.0e-3 TRS2 = 1.0e-6)
.MODEL DPLCAPMOD D (CJO = 8.9e-10 IS = 1e-30 M = 0.8)
.MODEL MMEDMOD NMOS (VTO = 3.36 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.13)
.MODEL MSTROMOD NMOS (VTO = 3.84 KP = 63 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.89 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 21.3 )
.MODEL RBREAKMOD RES (TC1 = 1.08e-3 TC2 = -6.0e-7)
.MODEL RDRAINMOD RES (TC1 = 1.1e-2 TC2 = 2.7e-5)
.MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 2.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.8e-3 TC2 = -9.0e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.1e-3 TC2 = -9.0e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -5.8 VOFF= -2.4)
VON = -2.4 VOFF= -5.8)
VON = -1.8 VOFF= 0.5)
VON = 0.5 VOFF= -1.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
HUF75823D3, HUF75823D3S
SABER Electrical Model
REV 18 February 2000
template huf75823 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 6.5e-13, rs = 1.06e-2, xti = 5, trs1 = 2.4e-3, trs2 = 1.5e-6, cjo = 8.0e-10, tt = 1.1e-7, m = 0.6)
dp..model dbreakmod = (rs = 2.0, trs1 = 2.0e-3, trs2 = 1.0e-6)
dp..model dplcapmod = (cjo = 8.9e-10, is = 10e-30, m = 0.8)
m..model mmedmod = (type=_n, vto = 3.36, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.84, kp = 63, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.89, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.8, voff = -2.4)
DPLCAP 5
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.4, voff = -5.8)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8)
RSLC1
LDRAIN
DRAIN
2
RLDRAIN
51
c.ca n12 n8 = 1.2e-9
c.cb n15 n14 = 1.3e-9
c.cin n6 n8 = 7.4e-10
RSLC2
ISCL
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 3.11e-9
l.lsource n3 n7 = 3.72e-9
RDRAIN
6
8
ESG
EVTEMP
RGATE + 18 22
9
20
MWEAK
MSTRO
CIN
DBODY
EBREAK
+
17
18
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
-
8
LSOURCE
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/25))** 3))
}
}
-
IT
14
+
+
spe.ebreak n11 n7 n17 n18 = 157.1
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
8
21
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.08e-3, tc2 = -6.0e-7
res.rdrain n50 n16 = 7.7e-2, tc1 = 1.1e-2, tc2 = 2.7e-5
res.rgate n9 n20 = 2.13
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 31.1
res.rlsource n3 n7 = 37.2
res.rslc1 n5 n51 = 1e-6, tc1 = 3.5e-3, tc2 = 2.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.0e-2, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.1e-3, tc2 = -9.0e-7
res.rvthres n22 n8 = 1, tc1 = -2.8e-3, tc2 = -9.0e-6
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
VBAT
5
8
EDS
-
+
8
22
RVTHRES
SOURCE
3
HUF75823D3, HUF75823D3S
SPICE Thermal Model
REV 25 October 1999
th
JUNCTION
HUF75823D
CTHERM1 th 6 1.40e-3
CTHERM2 6 5 5.55e-3
CTHERM3 5 4 5.65e-3
CTHERM4 4 3 6.10e-3
CTHERM5 3 2 9.80e-3
CTHERM6 2 tl 7.70e-2
RTHERM1
CTHERM1
6
RTHERM1 th 6 1.10e-2
RTHERM2 6 5 5.80e-2
RTHERM3 5 4 1.35e-1
RTHERM4 4 3 3.60e-1
RTHERM5 3 2 4.13e-1
RTHERM6 2 tl 4.30e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model HUF75823D
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.40e-3
ctherm.ctherm2 6 5 = 5.55e-3
ctherm.ctherm3 5 4 = 5.65e-3
ctherm.ctherm4 4 3 = 6.10e-3
ctherm.ctherm5 3 2 = 9.80e-3
ctherm.ctherm6 2 tl = 7.70e-2
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
rtherm.rtherm1 th 6 = 1.10e-2
rtherm.rtherm2 6 5 = 5.80e-2
rtherm.rtherm3 5 4 = 1.35e-1
rtherm.rtherm4 4 3 = 3.60e-1
rtherm.rtherm5 3 2 = 4.13e-1
rtherm.rtherm6 2 tl = 4.30e-1
}
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
9
CASE
HUF75823D3, HUF75823D3S
TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
E
H1
A
b2
SYMBOL
A
A1
b
b1
b2
b3
c
D
E
e
e1
H1
J1
L
L1
A1
SEATING
PLANE
D
L2
1
L
3
b1
b
L1
e
c
e1
J1
0.265
(6.7)
TERM. 4
b3
L3
L2
L3
0.265 (6.7)
0.070 (1.8)
0.118 (3.0)
BACK VIEW
0.063 (1.6) TYP
0.090 (2.3) TYP
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
1.5mm
DIA. HOLE
INCHES
MIN
MAX
0.086
0.094
0.018
0.022
0.028
0.032
0.033
0.045
0.205
0.215
0.190
0.018
0.022
0.270
0.295
0.250
0.265
0.090 TYP
0.180 BSC
0.035
0.045
0.040
0.045
0.100
0.115
MILLIMETERS
MIN
MAX
2.19
2.38
0.46
0.55
0.72
0.81
0.84
1.14
5.21
5.46
4.83
0.46
0.55
6.86
7.49
6.35
6.73
2.28 TYP
4.57 BSC
0.89
1.14
1.02
1.14
2.54
2.92
0.020
0.025
0.170
0.51
0.64
4.32
0.040
-
NOTES
4, 5
4, 5
4
4, 5
2
4, 5
7
7
-
1.01
-
4, 6
3
2
NOTES:
1. These dimensions are within allowable dimensions of Rev. B of
JEDEC TO-252AA outline dated 9-88.
2. L3 and b3 dimensions establish a minimum mounting surface for
terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L1 is the terminal length for soldering.
7. Position of lead to be measured 0.090 inches (2.28mm) from bottom
of dimension D.
8. Controlling dimension: Inch.
9. Revision 11 dated 1-00.
4.0mm
USER DIRECTION OF FEED
2.0mm
TO-252AA
1.75mm
C
L
16mm TAPE AND REEL
16mm
8.0mm
22.4mm
COVER TAPE
13mm
330mm
50mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
10
16.4mm
HUF75823D3, HUF75823D3S
TO-251AA
3 LEAD JEDEC TO-251AA PLASTIC PACKAGE
E
b2
H1
INCHES
A
A1
TERM. 4
SEATING
PLANE
D
b1
L1
L
c
b
1
2
3
J1
e
e1
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.086
0.094
2.19
2.38
-
A1
0.018
0.022
0.46
0.55
3, 4
b
0.028
0.032
0.72
0.81
3, 4
b1
0.033
0.045
0.84
1.14
3
b2
0.205
0.215
5.21
5.46
3, 4
c
0.018
0.022
0.46
0.55
3, 4
D
0.270
0.295
6.86
7.49
-
E
0.250
0.265
6.35
6.73
-
e
0.090 TYP
2.28 TYP
5
e1
0.180 BSC
4.57 BSC
5
H1
0.035
0.045
0.89
1.14
-
J1
0.040
0.045
1.02
1.14
6
L
0.355
0.375
9.02
9.52
-
L1
0.075
0.090
1.91
2.28
2
NOTES:
1. These dimensions are within allowable dimensions of Rev. C of
JEDEC TO-251AA outline dated 9-88.
2. Solder finish uncontrolled in this area.
3. Dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder plating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D.
7. Controlling dimension: Inch.
8. Revision 3 dated 1-00.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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11
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