VISHAY SIHFBC30AL-E3

IRFBC30AS, IRFBC30AL, SiHFBC30AS, SiHFBC30AL
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg Results in Simple Drive
Requirement
600
RDS(on) (Ω)
VGS = 10 V
2.2
Qg (Max.) (nC)
23
Qgs (nC)
5.4
Qgd (nC)
11
Configuration
COMPLIANT
Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage
and Current
Single
• Effective Coss Specified
D
I2PAK (TO-262)
Available
• Improved Gate, Avalanche and Dynamic dV/dt RoHS*
• Lead (Pb)-free Available
D2PAK (TO-263)
APPLICATIONS
• Switch Mode Power Supply (SMPS)
G
G
D
• Uninterruptible Power Supply
S
• High Speed Power Switching
TYPICAL SMPS TOPOLOGIES
S
• Single Transistor Flyback
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
D2PAK (TO-263)
D2PAK (TO-263)
D2PAK (TO-263)
I2PAK (TO-262)
IRFBC30ASPbF
IRFBC30ASTRLPbFa
IRFBC30ASTRRPbFa
IRFBC30ALPbF
SiHFBC30AS-E3
SiHFBC30ASTL-E3a
SiHFBC30ASTR-E3a
SiHFBC30AL-E3
IRFBC30AS
IRFBC30ASTRLa
IRFBC30ASTRRa
IRFBC30AL
SiHFBC30AS
SiHFBC30ASTLa
SiHFBC30ASTRa
SiHFBC30AL
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
600
Gate-Source Voltage
VGS
± 30
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta, e
ID
IDM
Linear Derating Factor
Energyb
UNIT
V
3.6
2.3
A
14
0.69
W/°C
mJ
EAS
290
Avalanche Currenta
IAR
3.6
A
Repetiitive Avalanche Energya
EAR
7.4
mJ
Single Pulse Avalanche
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc, e
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
PD
74
W
dV/dt
7.0
V/ns
TJ, Tstg
- 55 to + 150
300d
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 46 mH, RG = 25 Ω, IAS = 3.6 A (see fig. 12).
c. ISD ≤ 3.6 A, dI/dt ≤ 170 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. Uses IRFBC30A/SiHFBC30A data and test conditions.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91109
S-81412-Rev. A, 07-Jul-08
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IRFBC30AS, IRFBC30AL, SiHFBC30AS, SiHFBC30AL
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient (PCB
Mounted, steady-state)a
PARAMETER
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
1.7
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
600
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mAd
-
0.67
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.5
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 600 V, VGS = 0 V
-
-
25
VDS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
250
-
-
2.2
Ω
VDS = 50 V, ID = 2.2 A
2.1
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
510
-
-
70
-
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 2.2 Ab
VGS = 10 V
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Coss
VGS = 0 V
Coss eff.
-
3.5
-
VDS = 1.0 V, f = 1.0 MHz
-
730
-
VDS = 480 V, f = 1.0 MHz
-
19
-
VDS = 0 V to 480 Vc
-
31
-
-
-
23
ID = 3.6 A, VDS = 480 V,
see fig. 6 and 13b
-
-
5.4
11
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
Turn-On Delay Time
td(on)
-
9.8
-
tr
-
13
-
-
19
-
-
12
-
-
-
3.6
-
-
14
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 10 V
VDD = 300 V, ID = 3.6 A,
RG = 12 Ω, RD = 82 Ω, see fig. 10b, d
tf
pF
nC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 3.6 A, VGS = 0 Vb
TJ = 25 °C, IF = 3.6 A, dI/dt = 100 A/µsb,
-
-
1.6
V
-
400
600
ns
-
1.1
1.7
µC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
d. Uses IRFBC30A/SiHFBC30A data and test conditions.
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Document Number: 91109
S-81412-Rev. A, 07-Jul-08
IRFBC30AS, IRFBC30AL, SiHFBC30AS, SiHFBC30AL
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
10
1
0.1
4.5V
20µs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
10
TJ = 150 ° C
1
TJ = 25 ° C
0.1
0.01
4.0
100
Fig. 1 - Typical Output Characteristics
I D , Drain-to-Source Current (A)
1
4.5V
20µs PULSE WIDTH
TJ = 150 ° C
1
10
Fig. 2 - Typical Output Characteristics
Document Number: 91109
S-81412-Rev. A, 07-Jul-08
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VDS , Drain-to-Source Voltage (V)
6.0
7.0
8.0
9.0
Fig. 3 - Typical Transfer Characteristics
TOP
0.1
0.1
5.0
VGS , Gate-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
10
V DS = 50V
20µs PULSE WIDTH
ID = 3.6A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFBC30AS, IRFBC30AL, SiHFBC30AS, SiHFBC30AL
Vishay Siliconix
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance(pF)
1000
Ciss
100
Coss
10
ISD , Reverse Drain Current (A)
100
10000
10
TJ = 150° C
TJ = 25 ° C
1
Crss
1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
ID = 3.6A
V GS = 0 V
0.6
0.8
1.0
1.2
VSD ,Source-to-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
VDS = 480V
VDS = 300V
VDS = 120V
16
ID , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
20
0.1
0.4
12
8
10us
10
100us
1
1ms
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
4
8
12
16
20
24
QG , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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0.1
10ms
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91109
S-81412-Rev. A, 07-Jul-08
IRFBC30AS, IRFBC30AL, SiHFBC30AS, SiHFBC30AL
Vishay Siliconix
RD
VDS
4.0
VGS
D.U.T.
ID , Drain Current (A)
RG
+
- VDD
3.0
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
2.0
Fig. 10a - Switching Time Test Circuit
VDS
1.0
90 %
0.0
25
50
75
100
125
10 %
VGS
150
TC , Case Temperature ( ° C)
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
10
1 D = 0.50
0.20
0.10
PDM
0.05
0.1
t1
0.02
0.01
t2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
L
VDS
D.U.T.
RG
IAS
20 V
tp
tp
Driver
+
A
- VDD
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91109
S-81412-Rev. A, 07-Jul-08
IAS
Fig. 12b - Unclamped Inductive Waveforms
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IRFBC30AS, IRFBC30AL, SiHFBC30AS, SiHFBC30AL
400
TOP
BOTTOM
ID
1.6A
2.3A
3.6A
300
200
100
740
V DSav , Avalanche Voltage ( V )
EAS , Single Pulse Avalanche Energy (mJ)
Vishay Siliconix
720
700
680
660
640
0
25
50
75
100
125
150
0.0
1.0
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
2.0
3.0
4.0
IAV , Avalanche Current ( A)
Fig. 12d - Typical Drain-to-Source Voltage vs.
Avalanache Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91109
S-81412-Rev. A, 07-Jul-08
IRFBC30AS, IRFBC30AL, SiHFBC30AS, SiHFBC30AL
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91109.
Document Number: 91109
S-81412-Rev. A, 07-Jul-08
www.vishay.com
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
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document or by any conduct of Vishay.
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Document Number: 91000
Revision: 18-Jul-08
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