D2 PA K PSMN9R5-100BS N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK Rev. 2 — 2 March 2012 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in a D2PAK package qualified to 175C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for standard level gate drive 1.3 Applications DC-to-DC converters Motor control Load switching Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 100 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 89 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 211 W Tj junction temperature -55 - 175 °C VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 13 - 8.16 9.6 mΩ VGS = 10 V; ID = 60 A; VDS = 50 V; see Figure 14;see Figure 15 - 23 - nC - 82 - nC - - 177 mJ Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 89 A; Vsup ≤ 100 V; unclamped; RGS = 50 Ω PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain[1] 3 S source mb D mounting base; connected to drain Simplified outline Graphic symbol mb D G S mbb076 2 1 3 SOT404 (D2PAK) [1] It is not possible to make connection to pin 2. 3. Ordering information Table 3. Ordering information Type number Package PSMN9R5-100BS Name Description Version D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT404 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V VDGR drain-gate voltage Tj ≤ 175 °C; Tj ≥ 25 °C; RGS = 20 kΩ - 100 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 - 63 A VGS = 10 V; Tmb = 25 °C; see Figure 1 - 89 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 - 355 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 211 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode IS source current Tmb = 25 °C - 89 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 355 A VGS = 10 V; Tj(init) = 25 °C; ID = 89 A; Vsup ≤ 100 V; unclamped; RGS = 50 Ω - 177 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy PSMN9R5-100BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 2 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 003aae016 100 03aa16 120 ID (A) Pder (%) 80 80 60 40 40 20 0 0 0 Fig 1. 50 100 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature 0 50 100 150 200 Tmb (°C) Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aae017 103 ID (A) Limit RDSon = VDS / ID 102 tp = 10 μs 100 μs 10 DC 1 1 ms 10 ms 100 ms 10−1 1 Fig 3. 102 10 103 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN9R5-100BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 3 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 0.38 0.71 K/W Rth(j-a) thermal resistance from junction to ambient Minimum footprint; mounted on a printed circuit board - 50 - K/W 003aad142 1 Zth(j-mb) δ = 0.5 (K/W) 10−1 0.2 0.1 0.05 0.02 10−2 single shot δ= P tp T 10−3 t tp 10−4 10−6 Fig 4. T 10−5 10−4 10−3 10−2 10−1 1 tp (s) 10 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN9R5-100BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 4 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 90 - - V ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 100 - - V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 10; see Figure 11 1 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 10; see Figure 11 2 3 4 V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10; see Figure 11 - - 4.8 V - 100 µA Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) gate-source threshold voltage IDSS drain leakage current VDS = 100 V; VGS = 0 V; Tj = 125 °C - VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.02 4 µA IGSS gate leakage current VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 10 V; ID = 15 A; Tj = 100 °C; see Figure 12 - - 17.3 mΩ VGS = 10 V; ID = 15 A; Tj = 175 °C; see Figure 12 - 23.5 27.4 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 13 - 8.16 9.6 mΩ - 0.7 - Ω ID = 0 A; VDS = 0 V; VGS = 10 V; see Figure 14 - 67 - nC - 82 - nC - 21 - nC RDSon RG drain-source on-state resistance internal gate resistance f = 1 MHz (AC) Dynamic characteristics QG(tot) total gate charge QGS gate-source charge ID = 60 A; VDS = 50 V; VGS = 10 V; see Figure 14; see Figure 15 QGS(th) pre-threshold gate-source charge ID = 60 A; VDS = 50 V; VGS = 3 V; see Figure 14 - 13.1 - nC QGS(th-pl) post-threshold gate-source charge ID = 60 A; VDS = 50 V; VGS = 10 V; see Figure 14 - 7.8 - nC QGD gate-drain charge ID = 60 A; VDS = 50 V; VGS = 10 V; see Figure 14; see Figure 15 - 23 - nC VGS(pl) gate-source plateau voltage VDS = 50 V; see Figure 14; see Figure 15 - 4.5 - V Ciss input capacitance Coss output capacitance VDS = 50 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) tf VDS = 50 V; RL = 0.8 Ω; VGS = 10 V; RG(ext) = 4.7 Ω; Tj = 25 °C - 4454 - pF - 302 - pF - 185 - pF - 22 - ns - 25.2 - ns turn-off delay time - 52.2 - ns fall time - 22.8 - ns PSMN9R5-100BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 5 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit - 0.85 1.2 V - 61.5 - ns - 157 - nC Source-drain diode VSD source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; see Figure 17 trr reverse recovery time Qr recovered charge IS = 20 A; dIS/dt = 100 A/µs; VGS = 0 V; VDS = 50 V 003aae025 30 003aae022 8000 RDSon (mΩ) C (pF) Ciss 24 6000 18 4000 Crss 12 2000 6 0 4 Fig 5. 8 12 16 VGS (V) 20 Drain-source on-state resistance as a function of gate-source voltage; typical values 003aae021 150 0 Fig 6. 3 6 9 12 Input and reverse transfer capacitances as a function of gate-source voltage; typical values 003aae019 100 5 10 5.5 ID (A) gfs (S) VGS (V) 75 4.8 100 4.7 50 4.5 50 25 4.3 VGS (V) = 4 0 0 0 Fig 7. 20 40 60 I D (A) 80 Forward transconductance as a function of drain current; typical values PSMN9R5-100BS Product data sheet 0 Fig 8. 0.5 1 1.5 VDS (V) 2 Output characteristics: drain current as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 6 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 003aae020 80 03aa35 10−1 ID (A) ID (A) min 10−2 typ max 60 10−3 40 10−4 20 Tj = 175 °C 10−5 Tj = 25 °C 10−6 0 0 Fig 9. 2 4 VGS (V) 6 0 4 6 VGS (V) Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 10. Sub-threshold drain current as a function of gate-source voltage 003aad280 5 2 003aad774 3.2 VGS(th) (V) a 4 max 3 2.4 typ 1.6 2 min 0.8 1 0 −60 0 60 120 180 Tj (°C) Fig 11. Gate-source threshold voltage as a function of junction temperature PSMN9R5-100BS Product data sheet 0 -60 0 60 120 Tj (°C) 180 Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 7 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 003aae024 40 VGS (V) = 4.5 RDSon (mΩ) 4.7 4.8 VDS 30 ID VGS(pl) 5 20 VGS(th) 10 VGS 5.5 10 QGS1 QGS2 QGS 0 0 25 50 75 I D (A) 100 Fig 13. Drain-source on-state resistance as a function of drain current; typical values 003aae026 10 QGD QG(tot) 003aaa508 Fig 14. Gate charge waveform definitions 003aae023 104 VGS (V) C (pF) 8 Ciss Coss VDS = 20 V 50 V Crss 6 103 4 2 0 0 25 50 75 QG (nC) 100 Product data sheet 10−1 1 102 10 VDS (V) Fig 15. Gate-source voltage as a function of gate charge; typical values PSMN9R5-100BS 102 10−2 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 8 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 003aae027 100 IS (A) 75 50 25 Tj = 175 °C Tj = 25 °C 0 0 0.3 0.6 0.9 VSD (V) 1.2 Fig 17. Source current as a function of source-drain voltage; typical values PSMN9R5-100BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 9 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 7. Package outline SOT404 Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-03-16 SOT404 Fig 18. Package outline SOT404 (D2PAK) PSMN9R5-100BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 10 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN9R5-100BS v.2 20120302 Product data sheet - PSMN9R5-100BS v.1 - - Modifications: PSMN9R5-100BS v.1 PSMN9R5-100BS Product data sheet • • Status changed from objective to product. Various changes to content. 20111025 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 11 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 9. 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Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values— Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 12 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK Terms and conditions of commercial sale— NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. 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NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations— A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G reenChip,HiPerSmart,HITAG,I²C-buslogo,ICODE,I-CODE,ITEC,Labelution ,MIFARE,MIFARE Plus,MIFARE Ultralight,MoReUse,QLPAK,Silicon Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMediaand UCODE— are trademarks of NXP B.V. HD RadioandHD Radiologo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:[email protected] PSMN9R5-100BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 13 of 14 PSMN9R5-100BS NXP Semiconductors N-channel 100 V 9.6 mΩ standard level MOSFET in D2PAK 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact information. . . . . . . . . . . . . . . . . . . . . .13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 March 2012 Document identifier: PSMN9R5-100BS