Data Sheet

D2
PA
K
PSMN2R7-30BL
N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
Rev. 1 — 21 March 2012
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel MOSFET in D2PAK package qualified to 175 °C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
 High efficiency due to low switching
and conduction losses
 Suitable for logic level gate drive
sources
1.3 Applications
 DC-to-DC converters
 Motor control
 Load switiching
 Server power supplies
1.4 Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
30
V
ID
drain current
Tmb = 25 °C; VGS = 10 V; see Figure 1
-
-
100
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
-
170
W
Tj
junction temperature
-55
-
175
°C
VGS = 10 V; ID = 25 A; Tj = 100 °C;
see Figure 13; see Figure 12
-
3.6
4.2
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 12
-
2.57
3
mΩ
[1]
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
QGD
gate-drain charge
VGS = 4.5 V; ID = 25 A; VDS = 15 V
-
8
-
nC
QG(tot)
total gate charge
VGS = 4.5 V; ID = 25 A; VDS = 15 V;
see Figure 14; see Figure 15
-
32
-
nC
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
Vsup ≤ 30 V; RGS = 50 Ω; unclamped
-
-
300
mJ
Avalanche ruggedness
EDS(AL)S
[1]
non-repetitive
drain-source
avalanche energy
Continuous current is limited by package.
PSMN2R7-30BL
NXP Semiconductors
N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
2. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
1
G
gate
2
D
drain[1]
3
S
source
mb
D
mounting base;
connected to drain
Simplified outline
Graphic symbol
mb
D
G
mbb076
S
2
1
3
SOT404 (D2PAK)
[1]
It is not possible to make connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Type number
PSMN2R7-30BL
Package
Name
Description
Version
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
4. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN2R7-30BL
PSMN2R7-30BL
PSMN2R7-30BL
Product data sheet
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
30
V
VDGR
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
30
V
VGS
gate-source voltage
ID
drain current
-20
20
V
VGS = 10 V; Tmb = 100 °C; see Figure 1
[1]
-
100
A
VGS = 10 V; Tmb = 25 °C; see Figure 1
[1]
-
100
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C;
see Figure 3
-
730
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
170
W
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
Tsld(M)
peak soldering temperature
-
260
°C
-
100
A
Source-drain diode
[1]
IS
source current
Tmb = 25 °C
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
-
730
A
VGS = 10 V; Tj(init) = 25 °C; ID = 100 A;
Vsup ≤ 30 V; RGS = 50 Ω; unclamped
-
300
mJ
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
EDS(AL)S
[1]
Continuous current is limited by package.
003aad358
200
ID
(A)
03aa16
120
Pder
(%)
150
80
(1)
100
40
50
0
0
0
Fig 1.
50
100
150
Tmb (°C)
200
Product data sheet
50
100
150
200
Tmb (°C)
Continuous drain current as a function of
mounting base temperature
PSMN2R7-30BL
0
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
003aad382
103
ID
(A)
Limit RDSon = VDS / ID
tp = 10 μs
102
100 μs
(1)
DC
10
1 ms
10 ms
100 ms
1
10-1
Fig 3.
1
10
VDS (V)
102
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN2R7-30BL
Product data sheet
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from
junction to mounting base
see Figure 4
-
0.54
0.88
K/W
Rth(j-a)
thermal resistance from
junction to ambient
minimum footprint; mounted on
a printed-circuit board
-
50
-
K/W
003aad355
1
Zth(j-mb) δ = 0.5
(K/W)
0.2
10-1
0.1
0.05
0.02
10-2
δ=
P
tp
T
10-3
single shot
t
tp
T
10-4
Fig 4.
10-6
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Transient thermal impedance from junction to mounting base as a function of pulse duration; typical
values
PSMN2R7-30BL
Product data sheet
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Rev. 1 — 21 March 2012
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
7. Characteristics
Table 7.
Characteristics
Tested to JEDEC standards where applicable.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
V
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
30
-
ID = 250 µA; VGS = 0 V; Tj = -55 °C
27
-
-
V
VGS(th)
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10; see Figure 11
1.3
1.7
2.15
V
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 11
0.5
-
-
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 11
-
-
2.45
V
IDSS
drain leakage current
VDS = 30 V; VGS = 0 V; Tj = 25 °C
-
0.3
5
µA
VDS = 30 V; VGS = 0 V; Tj = 125 °C
-
-
100
µA
IGSS
gate leakage current
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
10
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
10
100
nA
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
see Figure 12
-
3.16
3.7
mΩ
VGS = 10 V; ID = 25 A; Tj = 175 °C;
see Figure 13; see Figure 12
-
4.88
5.7
mΩ
VGS = 10 V; ID = 25 A; Tj = 100 °C;
see Figure 13; see Figure 12
-
3.6
4.2
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 12
-
2.57
3
mΩ
f = 1 MHz
-
1
-
Ω
ID = 25 A; VDS = 15 V; VGS = 10 V;
see Figure 14; see Figure 15
-
66
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
60
-
nC
ID = 25 A; VDS = 15 V; VGS = 4.5 V;
see Figure 14; see Figure 15
-
32
-
nC
-
12
-
nC
RDSon
RG
drain-source on-state
resistance
gate resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGS(th)
pre-threshold
gate-source charge
-
6.4
-
nC
QGS(th-pl)
post-threshold
gate-source charge
-
5.6
-
nC
QGD
gate-drain charge
ID = 25 A; VDS = 15 V; VGS = 4.5 V
-
8
-
nC
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 15 V;
see Figure 14; see Figure 15
-
2.6
-
V
Ciss
input capacitance
-
3954
-
pF
Coss
output capacitance
VDS = 15 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
-
822
-
pF
Crss
reverse transfer
capacitance
-
356
-
pF
td(on)
turn-on delay time
-
46
-
ns
PSMN2R7-30BL
Product data sheet
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
Table 7.
Characteristics …continued
Tested to JEDEC standards where applicable.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
-
82
-
ns
td(off)
turn-off delay time
VDS = 15 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
-
74
-
ns
tf
fall time
-
35
-
ns
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 17
-
0.7
1.2
V
trr
reverse recovery time
-
40
-
ns
Qr
recovered charge
IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 15 V
-
33
-
nC
003aad410
8000
C
(pF)
003aad411
180
gfs
(S)
150
Ciss
6000
120
4000
90
Crss
60
2000
30
0
0
0
Fig 5.
3
6
9
VGS (V)
Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
PSMN2R7-30BL
Product data sheet
0
12
Fig 6.
25
50
75
ID (A)
100
Forward transconductance as a function of
drain current; typical values
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
003aad412
10
RDSon
(mΩ)
003aad404
120
ID
(A)
10 4.5
3.5
8
VGS (V) = 3
90
6
60
2.8
30
2.6
4
2
2.4
0
0
0
Fig 7.
5
10
15
VGS (V)
20
Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aad406
100
0
Fig 8.
1
2
ID
(A)
10-2
60
10-3
40
10-4
3
Output characteristics: drain current as a
function of drain-source voltage; typical values
003aab271
10-1
ID
(A)
80
VDS (V)
min
typ
1
2
max
Tj = 175 °C
20
10-5
Tj = 25 °C
10-6
0
0
Fig 9.
1
2
3
VGS (V)
4
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
PSMN2R7-30BL
Product data sheet
0
VGS (V)
3
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
003a a c982
3
VGS (th)
(V)
003aad405
10
RDSon
(mΩ)
3
VGS (V) = 2.8
8
max
2
6
typ
min
4
3.5
1
2
10
4.5
0
-60
0
0
60
120
Tj (°C)
180
Fig 11. Gate-source threshold voltage as a function of
junction temperature
0
20
40
60
80
ID (A)
100
Fig 12. Drain-source on-state resistance as a function
of drain current; typical values
03aa27
2
a
VDS
1.5
ID
1
VGS(pl)
VGS(th)
0.5
VGS
QGS1
0
−60
QGS
0
60
120
Tj (°C)
180
Product data sheet
QGD
QG(tot)
003aaa508
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
PSMN2R7-30BL
QGS2
Fig 14. Gate charge waveform definitions
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
003aad408
10
VGS
(V)
003aad409
104
6V
C
(pF)
8
Ciss
24 V
6
VDS = 15 V
103
Coss
4
Crss
2
102
10-1
0
0
20
40
60
QG (nC)
80
Fig 15. Gate-source voltage as a function of gate
charge; typical values
1
10
VDS (V)
102
Fig 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aad407
100
IS
(A)
80
60
40
Tj = 175 °C
20
Tj = 25 °C
0
0
0.2
0.4
0.6
0.8
VSD (V)
1
Fig 17. Source current as a function of source-drain voltage; typical values
PSMN2R7-30BL
Product data sheet
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Rev. 1 — 21 March 2012
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
8. Package outline
SOT404
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-02-11
06-03-16
SOT404
Fig 18. Package outline SOT404 (D2PAK)
PSMN2R7-30BL
Product data sheet
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
9. Revision history
Table 8.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN2R7-30BL v.1
20120321
Product data sheet
-
-
PSMN2R7-30BL
Product data sheet
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10. Legal information
10.1 Data sheet status
Document status[1] [2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URLhttp://www.nxp.com.
10.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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data sheet shall define the specification of the product as agreed between
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customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
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Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with theTerms and conditions of commercial sale of NXP Semiconductors.
PSMN2R7-30BL
Product data sheet
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
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Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
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NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
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the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
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products are sold subject to the general terms and conditions of commercial
sale, as published athttp://www.nxp.com/profile/terms, unless otherwise
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Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G
reenChip,HiPerSmart,HITAG,I²C-bus
logo,ICODE,I-CODE,ITEC,Labelution,MIFARE,MIFARE Plus,MIFARE
Ultralight,MoReUse,QLPAK,Silicon
Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMedia
andUCODE — are trademarks of NXP B.V.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
HD Radio andHD Radio logo — are trademarks of iBiquity Digital
Corporation.
11. Contact information
For more information, please visit:http://www.nxp.com
For sales office addresses, please send an email to:[email protected]
PSMN2R7-30BL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2012
© NXP B.V. 2012. All rights reserved.
14 of 15
PSMN2R7-30BL
NXP Semiconductors
N-channel 30 V 3.0 mΩ logic level MOSFET in D2PAK
12. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
10
10.1
10.2
10.3
10.4
11
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12
Legal information. . . . . . . . . . . . . . . . . . . . . . . .13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Contact information. . . . . . . . . . . . . . . . . . . . . .14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 21 March 2012
Document identifier: PSMN2R7-30BL