D2 PA K PSMN4R3-30BL N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK Rev. 1 — 22 March 2012 Product data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in D2PAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for logic level gate drive sources 1.3 Applications DC-to-DC converters Motor control Load switching Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 30 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 100 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 103 W Tj junction temperature -55 - 175 °C VGS = 10 V; ID = 15 A; Tj = 100 °C; see Figure 12; see Figure 13 - 4.9 5.8 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 13 - 3.5 4.1 mΩ [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge VGS = 4.5 V; ID = 15 A; VDS = 15 V; see Figure 14; see Figure 15 - 5 - nC - 19 - nC - - 74 mJ Avalanche ruggedness EDS(AL)S [1] non-repetitive drain-source avalanche energy Continuous current is limited by package. VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 30 V; RGS = 50 Ω; unclamped PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain[1] Simplified outline Graphic symbol mb 3 S source mb D mounting base; connected to drain D G mbb076 S 2 1 3 SOT404 (D2PAK) [1] It is not possible to make connection to pin 2 3. Ordering information Table 3. Ordering information Type number PSMN4R3-30BL Package Name Description Version D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404 (one lead cropped) 4. Marking Table 4. Marking codes Type number Marking code PSMN4R3-30BL PSMN4R3-30BL PSMN4R3-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 2 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 30 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 [1] - 80 A VGS = 10 V; Tmb = 25 °C; see Figure 1 [1] - 100 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 - 465 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 103 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C - 100 A Source-drain diode [1] IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 465 A VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 30 V; RGS = 50 Ω; unclamped - 74 mJ Avalanche ruggedness non-repetitive drain-source avalanche energy EDS(AL)S [1] Continuous current is limited by package. 003aad235 150 ID (A) 03aa16 120 Pder (%) 80 100 (1) 50 40 0 0 0 50 100 150 200 0 Tmb (°C) Fig 1. Product data sheet 100 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature PSMN4R3-30BL 50 Fig 2. Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 3 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 003aad296 103 ID (A) Limit RDSon = VDS / ID tp = 10 μs 102 (1) 100 μs DC 10 1 ms 10 ms 100 ms 1 10-1 Fig 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN4R3-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 4 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 1 1.5 K/W Rth(j-a) thermal resistance from junction to ambient Minimum footprint; mounted on a printed circuit board - 50 - K/W 003aad234 10 Zth (j-mb) (K/W) 1 δ = 0.5 0.2 -1 10 0.1 0.05 10-2 single shot 10-3 δ= P 0.02 tp T t tp T 10-4 Fig 4. 10-6 10-5 10-4 10-3 10-2 10-1 1 tp (s) 10 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN4R3-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 5 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 7. Characteristics Table 7. Characteristics Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit 30 - - V Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C VGS(th) gate-source threshold voltage IDSS drain leakage current IGSS gate leakage current RDSon RG drain-source on-state resistance gate resistance ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 10; see Figure 11 1.3 1.7 2.15 V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 11 0.5 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 11 - - 2.45 V VDS = 30 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 30 V; VGS = 0 V; Tj = 125 °C - - 40 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 10 V; ID = 15 A; Tj = 175 °C; see Figure 12; see Figure 13 - 6.65 7.8 mΩ VGS = 4.5 V; ID = 15 A; Tj = 25 °C; see Figure 13 - 4.46 5.2 mΩ VGS = 10 V; ID = 15 A; Tj = 100 °C; see Figure 12; see Figure 13 - 4.9 5.8 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 13 - 3.5 4.1 mΩ f = 1 MHz - 1 - Ω ID = 15 A; VDS = 15 V; VGS = 4.5 V; see Figure 14; see Figure 15 - 19 - nC ID = 15 A; VDS = 15 V; VGS = 10 V; see Figure 14; see Figure 15 - 41.5 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 30 - nC ID = 15 A; VDS = 15 V; VGS = 4.5 V; see Figure 14; see Figure 15 - 8 - nC - 4 - nC Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gate-source charge QGS(th-pl) post-threshold gate-source charge - 4 - nC QGD gate-drain charge - 5 - nC VGS(pl) gate-source plateau voltage ID = 15 A; VDS = 15 V; see Figure 14; see Figure 15 - 2.7 - V Ciss input capacitance - 2400 - pF Coss output capacitance VDS = 15 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 500 - pF Crss reverse transfer capacitance - 240 - pF PSMN4R3-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 6 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK Table 7. Characteristics …continued Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit td(on) turn-on delay time - 28 - ns tr rise time VDS = 15 V; RL = 0.5 Ω; VGS = 10 V; RG(ext) = 5.6 Ω - 58 - ns td(off) turn-off delay time - 44 - ns tf fall time - 21 - ns - 0.81 1.2 V Source-drain diode VSD source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; see Figure 17 trr reverse recovery time Qr recovered charge IS = 15 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 15 V 003aad244 120 gfs (S) - 35 - ns - 30 - nC 003aad240 5000 C (pF) 4000 Ciss 80 3000 Crss 2000 40 1000 0 0 0 Fig 5. 20 40 60 80 ID (A) Forward transconductance as a function of drain current; typical values PSMN4R3-30BL Product data sheet 0 100 Fig 6. 3 6 9 V (V) 12 GS Input and reverse transfer capacitances as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 7 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 003aad238 12 003aad236 100 10 ID (A) RDSon (mΩ) 5 80 4 8 3 3.5 60 40 4 VGS (V) =2.5 20 0 0 0 Fig 7. 5 10 VGS (V) 003aad241 2 3 4 5 Fig 8. Output characteristics: drain current as a function of drain-source voltage; typical values 003aab271 10-1 ID (A) 10-2 ID (A) 80 Tj = 175 °C 60 min typ 1 2 max 10-3 40 10-4 25 °C 10-5 20 10-6 0 0 Fig 9. 1 VDS (V) Drain-source on-state resistance as a function of gate-source voltage; typical values 100 0 15 1 2 3 4 VGS (V) 5 Transfer characteristics: drain current as a function of gate-source voltage; typical values PSMN4R3-30BL Product data sheet 0 VGS (V) 3 Fig 10. Sub-threshold drain current as a function of gate-source voltage All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 8 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 003a a c982 3 03aa27 2 a VGS (th) (V) max 1.5 2 typ 1 min 1 0.5 0 -60 0 60 120 Tj (°C) 180 Fig 11. Gate-source threshold voltage as a function of junction temperature 0 −60 0 60 120 Tj (°C) 180 Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature 003aad237 16 VDS RDSon (mΩ) ID 3 12 VGS(pl) 3.5 8 VGS(th) 4 4.5 VGS QGS1 5 4 QGS2 QGS VGS (V) =10 QGD QG(tot) 003aaa508 0 0 20 40 60 80 ID (A) 100 Fig 13. Drain-source on-state resistance as a function of drain current; typical values PSMN4R3-30BL Product data sheet Fig 14. Gate charge waveform definitions All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 9 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 003aad242 10 003aad239 104 VGS (V) C (pF) 8 Ciss 6 VDS = 15V 103 4 Coss 2 Crss 102 10-1 0 0 20 40 QG (nC) 60 Fig 15. Gate-source voltage as a function of gate charge; typical values 1 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aad243 100 IS (A) 80 Tj = 175 °C 60 25 °C 40 20 0 0 0.5 1 1.5 VSD (V) 2 Fig 17. Source current as a function of source-drain voltage; typical values PSMN4R3-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 10 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 8. Package outline SOT404 Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-03-16 SOT404 Fig 18. Package outline SOT404 (D2PAK) PSMN4R3-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 11 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 9. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN4R3-30BL v.1 20120322 Product data sheet - - PSMN4R3-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 12 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 10. Legal information 10.1 Data sheet status Document status[1] [2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 13 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. 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Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G reenChip,HiPerSmart,HITAG,I²C-bus logo,ICODE,I-CODE,ITEC,Labelution,MIFARE,MIFARE Plus,MIFARE Ultralight,MoReUse,QLPAK,Silicon Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMedia andUCODE — are trademarks of NXP B.V. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the HD Radio andHD Radio logo — are trademarks of iBiquity Digital Corporation. 11. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:[email protected] PSMN4R3-30BL Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 14 of 15 PSMN4R3-30BL NXP Semiconductors N-channel 30 V 4.1 mΩ logic level MOSFET in D2PAK 12. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 10.1 10.2 10.3 10.4 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Contact information. . . . . . . . . . . . . . . . . . . . . .14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 March 2012 Document identifier: PSMN4R3-30BL