D2 PA K PSMN7R0-100BS N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. Rev. 2 — 2 March 2012 Objective data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in D2PAK package qualified to 175C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for standard level gate drive 1.3 Applications DC-to-DC converters Motor control Load switching Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 100 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 100 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 269 W Tj junction temperature -55 - 175 °C VGS = 10 V; ID = 15 A; Tj = 100 °C; see Figure 12 - - 12 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 13 - 5.4 6.8 mΩ [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge VGS = 10 V; ID = 25 A; VDS = 50 V; see Figure 15; see Figure 14 - 36 - nC QG(tot) total gate charge VGS = 10 V; ID = 25 A; VDS = 50 V; see Figure 14; see Figure 15 - 125 - nC VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup = 100 V; unclamped; RGS = 50 Ω - - 315 mJ Avalanche ruggedness EDS(AL)S [1] non-repetitive drain-source avalanche energy Continuous current is limited by package. PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain[1] Simplified outline Graphic symbol mb 3 S source mb D mounting base; connected to drain D G mbb076 S 2 1 3 SOT404 (D2PAK) [1] It is not possible to make connection to pin 2. 3. Ordering information Table 3. Ordering information Type number Package PSMN7R0-100BS Name Description Version D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT404 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 100 V VDGR drain-gate voltage Tj ≤ 175 °C; Tj ≥ 25 °C; RGS = 20 kΩ - 100 V VGS gate-source voltage -20 20 V ID drain current - 85 A - 100 A - 475 A VGS = 10 V; Tmb = 100 °C; see Figure 1 VGS = 10 V; Tmb = 25 °C; see Figure 1 [1] IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 269 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C - 100 A Source-drain diode [1] IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 475 A VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup = 100 V; unclamped; RGS = 50 Ω - 315 mJ Avalanche ruggedness EDS(AL)S [1] non-repetitive drain-source avalanche energy Continuous current is limited by package. PSMN7R0-100BS Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 2 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 003aad558 150 03aa16 120 ID (A) Pder (%) 80 100 (1) 40 50 0 0 0 Fig 1. 50 100 0 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature 50 100 150 200 Tmb (°C) Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aad559 103 ID (A) Limit RDSon = V DS / ID tp = 10 μ s 102 100 μ s 10 DC 1 ms 10 ms 1 100 ms 10-1 1 Fig 3. 102 10 103 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN7R0-100BS Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 3 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 0.3 0.56 K/W Rth(j-a) thermal resistance from junction to ambient Minimum footprint; mounted on a printed circuit board - 60 - K/W 003aad560 1 Zth (j-mb) (K/W) 10-1 δ = 0.5 0.2 0.1 10-2 0.05 0.02 δ= P tp T 10-3 single shot t tp T 10-4 10-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 1 tp (s) 10 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN7R0-100BS Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 4 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 90 - - V ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 100 - - V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 10 1 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 11; see Figure 10 2 3 4 V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10 - - 4.6 V - 150 µA Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) gate-source threshold voltage IDSS drain leakage current VDS = 100 V; VGS = 0 V; Tj = 125 °C - VDS = 100 V; VGS = 0 V; Tj = 25 °C - 0.08 5 µA IGSS gate leakage current VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 10 V; ID = 15 A; Tj = 100 °C; see Figure 12 - - 12 mΩ VGS = 10 V; ID = 15 A; Tj = 175 °C; see Figure 12 - 15 19 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 13 - 5.4 6.8 mΩ - 0.74 - Ω ID = 25 A; VDS = 50 V; VGS = 10 V; see Figure 14; see Figure 15 - 125 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 100 - nC RDSon RG drain-source on-state resistance internal gate resistance f = 1 MHz (AC) Dynamic characteristics QG(tot) total gate charge QGS gate-source charge ID = 25 A; VDS = 50 V; VGS = 10 V; see Figure 15; see Figure 14 - 28 - nC QGS(th) pre-threshold gate-source charge ID = 25 A; VDS = 50 V; VGS = 10 V; see Figure 15 - 19.4 - nC QGS(th-pl) post-threshold gate-source charge - 9 - nC QGD gate-drain charge ID = 25 A; VDS = 50 V; VGS = 10 V; see Figure 15; see Figure 14 - 36 - nC VGS(pl) gate-source plateau voltage VDS = 50 V; see Figure 15; see Figure 14 - 4.3 - V Ciss input capacitance - 6686 - pF Coss output capacitance VDS = 50 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 438 - pF Crss reverse transfer capacitance - 272 - pF PSMN7R0-100BS Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 5 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit td(on) turn-on delay time - 34.6 - ns tr rise time VDS = 50 V; RL = 2 Ω; VGS = 10 V; RG(ext) = 4.7 Ω; Tj = 25 °C - 45.6 - ns td(off) turn-off delay time - 103.9 - ns tf fall time - 49.5 - ns - 0.8 1.2 V - 64 - ns - 167 - nC Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 trr reverse recovery time Qr recovered charge IS = 25 A; dIS/dt = 100 A/µs; VGS = 0 V; VDS = 50 V 003a a d562 300 20 ID (A) 6 5.5 C (pF) 10000 10 240 5 180 003a a d566 12000 Cis s 8000 Crs s 120 6000 4.5 60 4000 VGS (V) = 4 0 2000 0 Fig 5. 1 2 3 VDS (V) 4 Output characteristics: drain current as a function of drain-source voltage; typical values PSMN7R0-100BS Objective data sheet 0 Fig 6. 5 10 15 20 VGS (V) Input and reverse transfer capacitances as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 6 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 003a a d572 240 003a a d568 60 ID (A) gfs (S ) 180 45 120 30 60 15 0 0 Fig 7. 50 100 150 200 003a a d571 40 Tj = 25 °C 0 250 I D (A) Forward transconductance as a function of drain current; typical values Tj = 175 °C 0 Fig 8. 2 4 VGS (V) 6 Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aad280 5 VGS(th) (V) RDS on (mΩ) 4 max 30 3 typ 20 2 min 10 1 0 0 Fig 9. 5 10 15 VGS (V) 20 Drain-source on-state resistance as a function of gate-source voltage; typical values PSMN7R0-100BS Objective data sheet 0 −60 0 60 120 180 Tj (°C) Fig 10. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 7 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 03aa35 10−1 ID (A) min 10−2 typ 003aad774 3.2 a max 2.4 10−3 1.6 10−4 0.8 10−5 10−6 0 2 4 6 0 -60 0 60 120 VGS (V) Fig 11. Sub-threshold drain current as a function of gate-source voltage 003a a d563 20 VGS (V) = 4.5 RDS on (mΩ) Tj (°C) 180 Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature 003aad569 10 VGS (V) 80 V 8 15 20 V 6 VDS = 50 V 10 4 5 6 5 10 2 20 0 0 0 20 40 60 80 Fig 13. Drain-source on-state resistance as a function of drain current; typical values PSMN7R0-100BS Objective data sheet 0 100 I D (A) 50 100 QG (nC) 150 Fig 14. Gate-source voltage as a function of gate charge; typical values All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 8 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 003aad567 104 Ciss C (pF) VDS ID 103 VGS(pl) Coss VGS(th) VGS QGS1 Crss QGS2 QGS QGD QG(tot) 102 10-1 1 003aaa508 Fig 15. Gate charge waveform definitions 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003a a d570 100 IS (A) 80 60 Tj = 175 °C 40 25 °C 20 0 0 0.3 0.6 0.9 VS D (V) 1.2 Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN7R0-100BS Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 9 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 7. Package outline SOT404 Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-03-16 SOT404 Fig 18. Package outline SOT404 (D2PAK) PSMN7R0-100BS Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 10 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN7R0-100BS v.2 20120302 Objective data sheet - PSMN7R0-100BS v.1 - - Modifications: PSMN7R0-100BS v.1 PSMN7R0-100BS Objective data sheet • Various changes to content. 20111025 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 11 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 9.2 Definitions Preview— The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Draft— The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet— A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification— The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Disclaimers Limited warranty and liability— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use— NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data— The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values— Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 12 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. Terms and conditions of commercial sale— NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license— Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control— This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products— Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations— A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G reenChip,HiPerSmart,HITAG,I²C-buslogo,ICODE,I-CODE,ITEC,Labelution ,MIFARE,MIFARE Plus,MIFARE Ultralight,MoReUse,QLPAK,Silicon Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMediaand UCODE— are trademarks of NXP B.V. HD RadioandHD Radiologo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:[email protected] PSMN7R0-100BS Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 2 March 2012 © NXP B.V. 2012. All rights reserved. 13 of 14 PSMN7R0-100BS NXP Semiconductors N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK. 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact information. . . . . . . . . . . . . . . . . . . . . .13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 March 2012 Document identifier: PSMN7R0-100BS