Data Sheet

PSMN5R2-60YL
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
3 June 2016
Product data sheet
1. General description
Logic level N-channel MOSFET in an LFPAK56 (Power SO8) package using TrenchMOS
technology. This product is designed and qualified for use in a wide range of power
supply & motor control equipment.
2. Features and benefits
•
•
•
•
Advanced TrenchMOS provides low RDSon and low gate charge
Logic level gate operation
Avalanche rated, 100% tested
LFPAK provides maximum power density in a Power SO8 package
3. Applications
•
•
•
•
•
Synchronous rectifier in LLC topology
Chargers & adaptors with Vout < 10 V
Fast charge & USB-PD applications
Battery powered motor control
LED lighting & TV backlight
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
-
60
V
ID
drain current
VGS = 5 V; Tmb = 25 °C; Fig. 2
-
-
100
A
Ptot
total power dissipation
Tmb = 25 °C; Fig. 1
-
-
195
W
VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11
-
4.6
6
mΩ
ID = 25 A; VDS = 48 V; VGS = 5 V;
-
11.1
-
nC
[1]
Static characteristics
RDSon
drain-source on-state
resistance
Dynamic characteristics
QGD
gate-drain charge
Fig. 13; Fig. 14
[1]
Continuous current is limited by package.
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PSMN5R2-60YL
NXP Semiconductors
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
5. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
Simplified outline
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
mbb076
S
1 2 3 4
LFPAK56; PowerSO8 (SOT669)
6. Ordering information
Table 3.
Ordering information
Type number
Package
PSMN5R2-60YL
Name
Description
Version
LFPAK56;
Power-SO8
Plastic single-ended surface-mounted package
(LFPAK56; Power-SO8); 4 leads
SOT669
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 175 °C
-
60
V
VDGR
drain-gate voltage
RGS = 20 kΩ
-
60
V
VGS
gate-source voltage
-20
20
V
Ptot
total power dissipation
Tmb = 25 °C; Fig. 1
-
195
W
ID
drain current
VGS = 5 V; Tmb = 25 °C; Fig. 2
-
100
A
VGS = 5 V; Tmb = 100 °C; Fig. 2
-
85
A
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
-
479
A
[1]
IDM
peak drain current
Tstg
storage temperature
-55
175
°C
Tj
junction temperature
-55
175
°C
-
100
A
-
479
A
Source-drain diode
IS
source current
Tmb = 25 °C
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
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Product data sheet
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PSMN5R2-60YL
NXP Semiconductors
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
Symbol
Parameter
Conditions
Min
Max
Unit
-
127
mJ
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
ID = 100 A; Vsup ≤ 60 V; RGS = 50 Ω;
[2][3]
VGS = 5 V; Tj(init) = 25 °C; unclamped;
Fig. 4
[1]
[2]
[3]
Continuous current is limited by package.
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
03aa16
120
003aaj185
150
ID
(A)
Pder
(%)
80
100
40
50
0
Fig. 1.
0
50
100
150
Tmb (°C)
0
200
Normalized total power dissipation as a
function of mounting base temperature
(1)
0
50
100
150
200
Tmb (°C)
(1) Capped at 100A due to package
Fig. 2.
Continuous drain current as a function of
mounting base temperature
003aaj187
103
ID
(A)
Limit RDSon = VDS / ID
tp =10 µ s
102
100 µ s
10
DC
10 ms
100 ms
1
10-1
10-1
Fig. 3.
1 ms
1
10
102
VDS (V)
103
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN5R2-60YL
Product data sheet
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PSMN5R2-60YL
NXP Semiconductors
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
003aaj186
103
IAL
(A)
102
(1)
10
(2)
1
(3)
10-1
10-3
Fig. 4.
10-2
10-1
1
tAL (ms)
10
Avalanche rating; avalanche current as a function of avalanche time
8. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
-
0.77
K/W
Zth(j-mb)
(K/W)
aaa-018259
1
δ = 0.5
0.2
10-1
0.1
0.05
0.02
single shot
P
10-2
δ=
tp
10-3
10-6
Fig. 5.
10-5
10-4
10-3
10-2
10-1
tp
T
t
T
tp (s)
1
Transient thermal impedance from junction to mounting base as a function of pulse duration.
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Product data sheet
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PSMN5R2-60YL
NXP Semiconductors
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
9. Characteristics
Table 6.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
60
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
54
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9;
1.4
1.7
2.1
V
ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 9
-
-
2.45
V
ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 9
0.5
-
-
V
VDS = 60 V; VGS = 0 V; Tj = 175 °C
-
-
500
µA
VDS = 60 V; VGS = 0 V; Tj = 25 °C
-
0.07
10
µA
VGS = 16 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = -16 V; VDS = 0 V; Tj = 25 °C
-
2
100
nA
VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11
-
4.6
6
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C;
-
4
5.2
mΩ
-
-
13.6
mΩ
-
39.4
-
nC
-
78.4
-
nC
Static characteristics
V(BR)DSS
VGS(th)
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
Fig. 10
Fig. 11
VGS = 5 V; ID = 25 A; Tj = 175 °C;
Fig. 11; Fig. 12
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 48 V; VGS = 5 V;
Fig. 13; Fig. 14
ID = 25 A; VDS = 48 V; VGS = 10 V;
Fig. 13; Fig. 14
QGS
gate-source charge
ID = 25 A; VDS = 48 V; VGS = 5 V;
-
12.3
-
nC
QGD
gate-drain charge
Fig. 13; Fig. 14
-
11.1
-
nC
Ciss
input capacitance
VDS = 25 V; VGS = 0 V; f = 1 MHz;
-
4739
6319
pF
Coss
output capacitance
Tj = 25 °C; Fig. 15
-
391
469
pF
Crss
reverse transfer
capacitance
-
202
277
pF
td(on)
turn-on delay time
VDS = 45 V; RL = 1.8 Ω; VGS = 5 V;
-
24
-
ns
tr
rise time
RG(ext) = 5 Ω
-
44
-
ns
td(off)
turn-off delay time
-
60
-
ns
tf
fall time
-
37
-
ns
-
0.8
1.2
V
Source-drain diode
VSD
source-drain voltage
PSMN5R2-60YL
Product data sheet
IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 16
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PSMN5R2-60YL
NXP Semiconductors
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
trr
reverse recovery time
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
26
-
ns
Qr
recovered charge
VDS = 25 V
-
23
-
nC
003aaj189
100
ID
(A)
10
4.5
003aaj190
20
R DSon
(mΩ )
3
75
15
2.8
50
10
2.6
25
5
2.4
0
VGS (V) = 2.2
0
0.5
1
VDS(V)
0
1.5
Tj = 25 °C; tp = 300 μs
Fig. 6.
Fig. 7.
Output characteristics; drain current as a
function of drain-source voltage; typical values
003aaj192
180
0
2.5
5
7.5
10
Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aah025
3
VGS(th)
(V)
2.5
ID
(A)
VGS (V)
max
2
120
typ
1.5
Tj = 175 °C
0
Fig. 8.
min
1
60
0
1
2
0.5
Tj = 25 °C
3
VGS (V)
0
-60
4
Transfer characteristics; drain current as a
function of gate-source voltage; typical values
PSMN5R2-60YL
Product data sheet
Fig. 9.
60
120
Tj (° C)
180
Gate-source threshold voltage as a function of
junction temperature
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PSMN5R2-60YL
NXP Semiconductors
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
003aah026
10-1
ID
(A)
10
003aaj195
20
RDSon
(m Ω )
-2
2.8
2.6
15
min
10-3
typ
max
10
10
-4
10
-5
10-6
3
4.5
5
VGS (V) = 10
0
1
2
V GS (V)
0
3
Fig. 10. Sub-threshold drain current as a function of
gate-source voltage
0
20
40
60
80
ID (A)
100
Tj = 25 °C; tp = 300 μs
Fig. 11. Drain-source on-state resistance as a function
of drain current; typical values
003aaj816
2.4
VDS
a
ID
1.6
VGS(pl)
VGS(th)
VGS
QGS2
0.8
QGS1
0
-60
0
60
120
Tj ( °C)
QGS
QGD
QG(tot)
003aaa508
Fig. 13. Gate charge waveform definitions
180
Fig. 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
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Product data sheet
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PSMN5R2-60YL
NXP Semiconductors
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
003aaj197
10
003aaj198
104
V GS
(V)
C
(pF)
8
Ciss
103
6
VDS = 14V
Coss
VDS = 48V
4
Crss
102
2
0
0
20
40
60
QG (nC)
10
10-1
80
1
10
V DS (V)
102
Fig. 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
Fig. 14. Gate-source voltage as a function of gate
charge; typical values
003aaj199
100
IS
(A)
80
60
40
20
Tj = 175 ° C
0
0
0.3
Tj = 25 °C
0.6
0.9 V (V) 1.2
SD
Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
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PSMN5R2-60YL
NXP Semiconductors
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
10. Package outline
Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads
E
A2
A
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w
b
A
X
c
1/2 e
A
(A3)
A1
C
q
L
detail X
0
y C
θ
5 mm
8°
scale
0°
Dimensions (mm are the original dimensions)
Unit(1)
A
A1
A2
A3
b
b2
max 1.20 0.15 1.10
0.50 4.41
nom
0.25
min 1.01 0.00 0.95
0.35 3.62
mm
c
c2
D(1) D1(1) E(1) E1(1)
b3
b4
2.2
0.9
0.25 0.30 4.10 4.20
5.0
3.3
2.0
0.7
0.19 0.24 3.80
4.8
3.1
e
1.27
H
L
L1
L2
6.2
0.85
1.3
1.3
5.8
0.40
0.8
0.8
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
Outline
version
SOT669
References
IEC
JEDEC
JEITA
w
y
0.25
0.1
sot669_po
European
projection
Issue date
11-03-25
13-02-27
MO-235
Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669)
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PSMN5R2-60YL
NXP Semiconductors
N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
11. Legal information
11.1 Data sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Please consult the most recently issued document before initiating or
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The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
11.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Draft — The document is a draft version only. The content is still under
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modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
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Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
11.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
PSMN5R2-60YL
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
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associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
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Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
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N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
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the product is not suitable for automotive use. It is neither qualified nor
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NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
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customer (a) shall use the product without NXP Semiconductors’ warranty
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between the translated and English versions.
11.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Bitsound, CoolFlux, CoReUse, DESFire, FabKey, GreenChip,
HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, MIFARE,
MIFARE Plus, MIFARE Ultralight, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP
Semiconductors N.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
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N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56
12. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
3
Applications ........................................................... 1
4
Quick reference data ............................................. 1
5
Pinning information ............................................... 2
6
Ordering information ............................................. 2
7
Limiting values .......................................................2
8
Thermal characteristics .........................................4
9
Characteristics ....................................................... 5
10
Package outline ..................................................... 9
11
11.1
11.2
11.3
11.4
Legal information .................................................10
Data sheet status ............................................... 10
Definitions ...........................................................10
Disclaimers .........................................................10
Trademarks ........................................................ 11
© NXP Semiconductors N.V. 2016. All rights reserved
For more information, please visit: http://www.nxp.com
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Date of release: 3 June 2016
PSMN5R2-60YL
Product data sheet
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3 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved
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