PSMN5R2-60YL N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56 3 June 2016 Product data sheet 1. General description Logic level N-channel MOSFET in an LFPAK56 (Power SO8) package using TrenchMOS technology. This product is designed and qualified for use in a wide range of power supply & motor control equipment. 2. Features and benefits • • • • Advanced TrenchMOS provides low RDSon and low gate charge Logic level gate operation Avalanche rated, 100% tested LFPAK provides maximum power density in a Power SO8 package 3. Applications • • • • • Synchronous rectifier in LLC topology Chargers & adaptors with Vout < 10 V Fast charge & USB-PD applications Battery powered motor control LED lighting & TV backlight 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 60 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - - 100 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 195 W VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11 - 4.6 6 mΩ ID = 25 A; VDS = 48 V; VGS = 5 V; - 11.1 - nC [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge Fig. 13; Fig. 14 [1] Continuous current is limited by package. Scan or click this QR code to view the latest information for this product PSMN5R2-60YL NXP Semiconductors N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package PSMN5R2-60YL Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 60 V VDGR drain-gate voltage RGS = 20 kΩ - 60 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 195 W ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - 100 A VGS = 5 V; Tmb = 100 °C; Fig. 2 - 85 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 479 A [1] IDM peak drain current Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C - 100 A - 479 A Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C PSMN5R2-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 3 June 2016 [1] © NXP Semiconductors N.V. 2016. All rights reserved 2 / 12 PSMN5R2-60YL NXP Semiconductors N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Min Max Unit - 127 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 100 A; Vsup ≤ 60 V; RGS = 50 Ω; [2][3] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 [1] [2] [3] Continuous current is limited by package. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 03aa16 120 003aaj185 150 ID (A) Pder (%) 80 100 40 50 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 Normalized total power dissipation as a function of mounting base temperature (1) 0 50 100 150 200 Tmb (°C) (1) Capped at 100A due to package Fig. 2. Continuous drain current as a function of mounting base temperature 003aaj187 103 ID (A) Limit RDSon = VDS / ID tp =10 µ s 102 100 µ s 10 DC 10 ms 100 ms 1 10-1 10-1 Fig. 3. 1 ms 1 10 102 VDS (V) 103 Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN5R2-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 3 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 3 / 12 PSMN5R2-60YL NXP Semiconductors N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56 003aaj186 103 IAL (A) 102 (1) 10 (2) 1 (3) 10-1 10-3 Fig. 4. 10-2 10-1 1 tAL (ms) 10 Avalanche rating; avalanche current as a function of avalanche time 8. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 0.77 K/W Zth(j-mb) (K/W) aaa-018259 1 δ = 0.5 0.2 10-1 0.1 0.05 0.02 single shot P 10-2 δ= tp 10-3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 tp T t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration. PSMN5R2-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 3 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 4 / 12 PSMN5R2-60YL NXP Semiconductors N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56 9. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 60 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 54 - - V gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 9; 1.4 1.7 2.1 V ID = 1 mA; VDS=VGS; Tj = -55 °C; Fig. 9 - - 2.45 V ID = 1 mA; VDS=VGS; Tj = 175 °C; Fig. 9 0.5 - - V VDS = 60 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 60 V; VGS = 0 V; Tj = 25 °C - 0.07 10 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11 - 4.6 6 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; - 4 5.2 mΩ - - 13.6 mΩ - 39.4 - nC - 78.4 - nC Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 10 Fig. 11 VGS = 5 V; ID = 25 A; Tj = 175 °C; Fig. 11; Fig. 12 Dynamic characteristics QG(tot) total gate charge ID = 25 A; VDS = 48 V; VGS = 5 V; Fig. 13; Fig. 14 ID = 25 A; VDS = 48 V; VGS = 10 V; Fig. 13; Fig. 14 QGS gate-source charge ID = 25 A; VDS = 48 V; VGS = 5 V; - 12.3 - nC QGD gate-drain charge Fig. 13; Fig. 14 - 11.1 - nC Ciss input capacitance VDS = 25 V; VGS = 0 V; f = 1 MHz; - 4739 6319 pF Coss output capacitance Tj = 25 °C; Fig. 15 - 391 469 pF Crss reverse transfer capacitance - 202 277 pF td(on) turn-on delay time VDS = 45 V; RL = 1.8 Ω; VGS = 5 V; - 24 - ns tr rise time RG(ext) = 5 Ω - 44 - ns td(off) turn-off delay time - 60 - ns tf fall time - 37 - ns - 0.8 1.2 V Source-drain diode VSD source-drain voltage PSMN5R2-60YL Product data sheet IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 16 All information provided in this document is subject to legal disclaimers. 3 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 5 / 12 PSMN5R2-60YL NXP Semiconductors N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Min Typ Max Unit trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 26 - ns Qr recovered charge VDS = 25 V - 23 - nC 003aaj189 100 ID (A) 10 4.5 003aaj190 20 R DSon (mΩ ) 3 75 15 2.8 50 10 2.6 25 5 2.4 0 VGS (V) = 2.2 0 0.5 1 VDS(V) 0 1.5 Tj = 25 °C; tp = 300 μs Fig. 6. Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values 003aaj192 180 0 2.5 5 7.5 10 Drain-source on-state resistance as a function of gate-source voltage; typical values 003aah025 3 VGS(th) (V) 2.5 ID (A) VGS (V) max 2 120 typ 1.5 Tj = 175 °C 0 Fig. 8. min 1 60 0 1 2 0.5 Tj = 25 °C 3 VGS (V) 0 -60 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values PSMN5R2-60YL Product data sheet Fig. 9. 60 120 Tj (° C) 180 Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. 3 June 2016 0 © NXP Semiconductors N.V. 2016. All rights reserved 6 / 12 PSMN5R2-60YL NXP Semiconductors N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56 003aah026 10-1 ID (A) 10 003aaj195 20 RDSon (m Ω ) -2 2.8 2.6 15 min 10-3 typ max 10 10 -4 10 -5 10-6 3 4.5 5 VGS (V) = 10 0 1 2 V GS (V) 0 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage 0 20 40 60 80 ID (A) 100 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values 003aaj816 2.4 VDS a ID 1.6 VGS(pl) VGS(th) VGS QGS2 0.8 QGS1 0 -60 0 60 120 Tj ( °C) QGS QGD QG(tot) 003aaa508 Fig. 13. Gate charge waveform definitions 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature PSMN5R2-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 3 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 7 / 12 PSMN5R2-60YL NXP Semiconductors N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56 003aaj197 10 003aaj198 104 V GS (V) C (pF) 8 Ciss 103 6 VDS = 14V Coss VDS = 48V 4 Crss 102 2 0 0 20 40 60 QG (nC) 10 10-1 80 1 10 V DS (V) 102 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Fig. 14. Gate-source voltage as a function of gate charge; typical values 003aaj199 100 IS (A) 80 60 40 20 Tj = 175 ° C 0 0 0.3 Tj = 25 °C 0.6 0.9 V (V) 1.2 SD Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN5R2-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 3 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 8 / 12 PSMN5R2-60YL NXP Semiconductors N-channel 60 V, 5.2 mΩ logic level MOSFET in LFPAK56 10. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 mm c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN5R2-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 3 June 2016 © NXP Semiconductors N.V. 2016. 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Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Limiting values .......................................................2 8 Thermal characteristics .........................................4 9 Characteristics ....................................................... 5 10 Package outline ..................................................... 9 11 11.1 11.2 11.3 11.4 Legal information .................................................10 Data sheet status ............................................... 10 Definitions ...........................................................10 Disclaimers .........................................................10 Trademarks ........................................................ 11 © NXP Semiconductors N.V. 2016. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 June 2016 PSMN5R2-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 3 June 2016 © NXP Semiconductors N.V. 2016. All rights reserved 12 / 12