D2 PA K PSMN4R4-80BS N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK Rev. 1 — 22 March 2012 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in SOT404 package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for standard level gate drive sources 1.3 Applications DC - DC converters Motor control Load switching Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 80 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 100 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 306 W Tj junction temperature -55 - 175 °C VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 13; see Figure 6 - 6.27 7.4 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 6 - 3.8 4.5 mΩ [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge VGS = 10 V; ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 - 25 - nC - 125 - nC - - 591 mJ Avalanche ruggedness EDS(AL)S [1] non-repetitive drain-source avalanche energy Continuous current is limited by package VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 80 V; RGS = 50 Ω; unclamped PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain[1] 3 S source mb D drain Simplified outline Graphic symbol mb D G mbb076 S 2 1 3 SOT404 (D2PAK) [1] It is not possible to make connection to pin 2 3. Ordering information Table 3. Ordering information Type number PSMN4R4-80BS Package Name Description Version D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404 (one lead cropped) 4. Marking Table 4. Marking codes Type number Marking code PSMN4R4-80BS PSMN4R4-80BS PSMN4R4-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 2 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 80 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 80 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 [1] - 100 A VGS = 10 V; Tmb = 25 °C; see Figure 1 [1] - 100 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 - 680 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 306 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C - 100 A - 680 A - 591 mJ Source-drain diode [1] IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C Avalanche ruggedness non-repetitive drain-source avalanche VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; energy Vsup ≤ 80 V; RGS = 50 Ω; unclamped EDS(AL)S [1] Continuous current is limited by package 003aad091 200 ID (A) 03aa16 120 Pder (%) 150 80 100 (1) 40 50 0 0 0 Fig 1. 50 100 150 Tmb ( C) 200 Product data sheet 50 100 150 200 Tmb (°C) Normalized continuous drain current as a function of mounting base temperature PSMN4R4-80BS 0 Fig 2. Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 3 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 003aad317 103 Limit RDSon = VDS / ID ID (A) tp = 10 μs 102 100 μs (1) 10 DC 1 ms 10 ms 100 ms 1 10-1 10-1 Fig 3. 1 10 102 103 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain source voltage PSMN4R4-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 4 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 0.23 0.49 K/W Rth(j-a) thermal resistance from junction to ambient Minimum footprint; mounted on a printed circuit board - 50 - K/W 003aad100 1 Zth (j-mb) (K/W) 10-1 δ = 0.5 0.2 0.1 10 -2 0.05 0.02 δ= P tp T 10-3 single shot t tp T 10-4 10-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 1 tp (s) 10 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN4R4-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 5 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 7. Characteristics Table 7. Characteristics Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit 73 - - V Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C VGS(th) gate-source threshold voltage IDSS drain leakage current IGSS gate leakage current RDSon RG ID = 250 µA; VGS = 0 V; Tj = 25 °C 80 - - V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 11 1 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 11 - - 4.6 V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 11; see Figure 12 2 3 4 V VDS = 80 V; VGS = 0 V; Tj = 25 °C - 0.02 10 µA VDS = 80 V; VGS = 0 V; Tj = 125 °C - - 200 µA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 175 °C; see Figure 13; see Figure 6 - 9.12 10.7 mΩ VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 13; see Figure 6 - 6.27 7.4 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 6 - 3.8 4.5 mΩ f = 1 MHz - 1 - Ω 112 - nC internal gate resistance (AC) Dynamic characteristics QG(tot) total gate charge ID = 0 A; VDS = 0 V; VGS = 10 V - 125 - nC gate-source charge ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14; see Figure 15 - QGS - 39 - nC QGS(th) pre-threshold gate-source charge - 24 - nC QGS(th-pl) post-threshold gate-source charge - 15 - nC QGD gate-drain charge - 25 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 - 4.65 - V Ciss input capacitance - 8400 - pF Coss output capacitance VDS = 40 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 700 - pF Crss reverse transfer capacitance - 336 - pF VDS = 40 V; RL = 0.5 Ω; VGS = 10 V; RG(ext) = 1.5 Ω - 34.7 - ns - 38.1 - ns turn-off delay time - 66 - ns fall time - 18.4 - ns td(on) turn-on delay time tr rise time td(off) tf PSMN4R4-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 6 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK Table 7. Characteristics …continued Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit - 0.8 1.2 V Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 trr reverse recovery time Qr recovered charge IS = 25 A; dIS/dt = 100 A/µs; VGS = 0 V; VDS = 20 V 300 ID VGS (V) = 20 (A) 250 003aad101 10 8 6 5.5 - 59 - ns - 130 - nC 003aad103 8 RDSon (mΩ) VGS (V) = 5 5.5 7 200 6 150 5 6 5 100 8 10 20 4 50 4.5 0 3 0 Fig 5. 0.75 1.5 2.25 VDS (V) Output characteristics: drain current as a function of drain-source voltage; typical values 003aad102 250 ID (A) 0 3 Fig 6. 75 150 225 ID (A) 300 Drain-source on-state resistance as a function of drain current; typical values 003aad106 12000 Ciss C (pf) 200 8000 150 Crss 175 °C 100 4000 25 °C 50 0 0 Fig 7. 2 4 VGS (V) Transfer characteristics: drain current as a function of gate-source voltage; typical values PSMN4R4-80BS Product data sheet 0 10-1 6 Fig 8. 1 10 VGS (V) 102 Input and reverse transfer capacitances as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 7 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 003aad109 250 gfs (S) RDSon (mΩ) 200 20 150 15 100 10 50 5 0 0 0 Fig 9. 003aad110 25 50 100 150 ID (A) 200 Forward transconductance as a function of drain current; typical values 003aad280 5 4 15 VGS (V) 20 Fig 10. Drain-source on-state resistance as a function of gate-source voltage; typical values 03aa35 10−1 min typ max 10−3 typ 2 10−4 min 10−5 1 10−6 0 60 120 180 0 Tj (°C) 2 4 6 VGS (V) Fig 11. Gate-source threshold voltage as a function of junction temperature Product data sheet 10 10−2 max 3 PSMN4R4-80BS 5 ID (A) VGS(th) (V) 0 −60 0 Fig 12. Sub-threshold drain current as a function of gate-source voltage All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 8 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 003aad327 2.5 VDS a ID 2 VGS(pl) 1.5 VGS(th) VGS 1 QGS1 QGS2 QGS 0.5 QGD QG(tot) 003aaa508 0 -60 0 60 120 Tj (°C) 180 Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature 003aad105 10 VGS (V) Fig 14. Gate charge waveform definitions 003aad104 10000 C (pF) Ciss VDS = 20 V 7.5 7500 VDS = 40 V 5 5000 2.5 2500 0 0 35 70 105 QG (nC) 140 Fig 15. Gate-source voltage as a function of gate charge; typical values PSMN4R4-80BS Product data sheet 0 10-1 Coss Crss 1 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 9 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 003aad107 100 IS (A) 75 50 175 °C 25 Tj = 25 °C 0 0 0.25 0.5 0.75 VSD (V) 1 Fig 17. Source current as a function of source-drain voltage; typical values PSMN4R4-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 10 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 8. Package outline SOT404 Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-03-16 SOT404 Fig 18. Package outline SOT404 (D2PAK) PSMN4R4-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 11 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 9. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN4R4-80BS v.1 20120322 Product data sheet - - PSMN4R4-80BS Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 12 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK 10. Legal information 10.1 Data sheet status Document status[1] [2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. 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NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 March 2012 © NXP B.V. 2012. All rights reserved. 13 of 15 PSMN4R4-80BS NXP Semiconductors N-channel 80 V, 4.5 mΩ standard level MOSFET in D2PAK Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 10.1 10.2 10.3 10.4 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Contact information. . . . . . . . . . . . . . . . . . . . . .14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 March 2012 Document identifier: PSMN4R4-80BS