Data Sheet

Freescale Semiconductor
Technical Data
Document Number: A2T18H160--24S
Rev. 0, 11/2015
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 28 W asymmetrical Doherty RF power LDMOS transistor is designed for
cellular base station applications covering the frequency range of 1805 to
1880 MHz.
1800 MHz
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 400 mA, VGSB = 0.65 Vdc, Pout = 28 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
1805 MHz
17.9
49.9
7.7
–32.0
1840 MHz
17.8
49.3
7.7
–33.8
1880 MHz
17.8
50.2
7.8
–34.7
A2T18H160--24SR3
1805–1880 MHz, 28 W AVG., 28 V
AIRFAST RF POWER LDMOS
TRANSISTOR
ACPR
(dBc)
NI--780S--4L2L
Features
 Advanced High Performance In--Package Doherty
 Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
 Designed for Digital Predistortion Error Correction Systems
6 VBWA(1)
Carrier
RFinA/VGSA 1
5 RFoutA/VDSA
RFinB/VGSB 2
4 RFoutB/VDSB
Peaking
3 VBWB(1)
(Top View)
Figure 1. Pin Connections
1. Device cannot operate with the VDD current
supplied through pin 3 and pin 6.
 Freescale Semiconductor, Inc., 2015. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
A2T18H160--24SR3
1
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain--Source Voltage
Rating
VDSS
–0.5, +65
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
Case Operating Temperature Range
TC
–40 to +150
C
(1,2)
TJ
–40 to +225
C
Characteristic
Symbol
Value (2,3)
Unit
RJC
0.45
C/W
Operating Junction Temperature Range
Table 2. Thermal Characteristics
Thermal Resistance, Junction to Case
Case Temperature 75C, 28 W Avg., W--CDMA, 28 Vdc, IDQA = 400 mA,
VGSB = 0.65 Vdc, 1840 MHz
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
2
Machine Model (per EIA/JESD22--A115)
B
Charge Device Model (per JESD22--C101)
IV
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 60 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Gate Quiescent Voltage
(VDD = 28 Vdc, ID = 400 mAdc, Measured in Functional Test)
VGSA(Q)
1.4
1.8
2.2
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 0.6 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 100 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 1.0 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Characteristic
Off Characteristics
(4)
On Characteristics -- Side A, Carrier
On Characteristics -- Side B, Peaking
1.
2.
3.
4.
Continuous use at maximum temperature will affect MTTF.
MTTF calculator available at http://www.freescale.com/rf/calculators.
Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf and search for AN1955.
Each side of device measured separately.
(continued)
A2T18H160--24SR3
2
RF Device Data
Freescale Semiconductor, Inc.
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests (1,2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 400 mA, VGSB = 0.65 Vdc, Pout = 28 W Avg.,
f = 1805 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in
3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
17.3
17.9
20.3
dB
Drain Efficiency
D
47.5
49.9
—
%
PAR
7.3
7.7
—
dB
ACPR
—
–32.0
–29.5
dBc
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Load Mismatch (2) (In Freescale Doherty Test Fixture, 50 ohm system) IDQA = 400 mA, VGSB = 0.65 Vdc, f = 1840 MHz
No Device Degradation
VSWR 10:1 at 32 Vdc, 158 W CW Output Power
(3 dB Input Overdrive from 100 W CW Rated Power)
Typical Performance (2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 400 mA, VGSB = 0.65 Vdc, 1805–1880 MHz
Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
126
—
W
Pout @ 3 dB Compression Point (3)
P3dB
—
182
—
W

—
–10.3
—

VBWres
—
135
—
MHz
Gain Flatness in 75 MHz Bandwidth @ Pout = 28 W Avg.
GF
—
0.04
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.008
—
dB/C
P1dB
—
0.003
—
dB/C
AM/PM
(Maximum value measured at the P3dB compression point across
the 1805–1880 MHz frequency range)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30C to +85C)
Table 5. Ordering Information
Device
A2T18H160--24SR3
Tape and Reel Information
R3 Suffix = 250 Units, 44 mm Tape Width, 13--inch Reel
Package
NI--780S--4L2L
1. Part internally matched both on input and output.
2. Measurements made with device in an asymmetrical Doherty configuration.
3. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
A2T18H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
3
VDDA
VGGA
-- C14
R2
C1
A2T18H160--24S
Rev. 2
C15
C17
C16
C2
C5 C6
Z1
R1
C3
C4
C7
C10 C11
C12
C8
C9
R4
C13
C
CUT OUT AREA
R3
C18
C19
P
C20
C21
D68661
C22
C24
C23
C25
VDDB
--
R5
VGGB
Figure 2. A2T18H160--24SR3 Test Circuit Component Layout
Table 6. A2T18H160--24SR3 Test Circuit Component Designations and Values
Part
Description
PCB
Part Number
Manufacturer
D58628
MTL
C1, C13, C16, C17, C22,
C24
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C2, C4, C8, C12, C15, C19,
C23
12 pF Chip Capacitors
ATC600F120JT250XT
ATC
C3
1.8 pF Chip Capacitor
ATC600F1R8BT250XT
ATC
C5, C6
0.3 pF Chip Capacitors
ATC600F0R3BT250XT
ATC
C7
1.0 pF Chip Capacitor
ATC600F1R0BT250XT
ATC
C9
2.0 pF Chip Capacitor
ATC600F2R0BT250XT
ATC
C10, C11, C20
0.5 pF Chip Capacitors
ATC600F0R5BT250XT
ATC
C14, C25
220 F, 50 V Electrolytic Capacitors
227CKS050M
Illinois Capacitor
C18
9.1 pF Chip Capacitor
ATC600F9R1BT250XT
ATC
C21
1.5 pF Chip Capacitor
ATC600F1R5BT250XT
ATC
R1
50 , 4 W Chip Resistor
C10A50Z4
Anaren
R2, R5
20 K, 1/4 W Chip Resistors
CRCW120620K0JNEA
Vishay
R3, R4
5.6 , 1/4 W Chip Resistors
CRCW12065R60FKEA
Vishay
Z1
1700–2000 MHz Band, 90, 5 dB Directional Coupler
X3C19P1-05S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D68661
MTL
A2T18H160--24SR3
4
RF Device Data
Freescale Semiconductor, Inc.
Gps, POWER GAIN (dB)
18.1
18
17.9
17.8
Gps
17.7
PARC
17.6
1800
–28
–2.1
–32
ACPR
17.4
1780
–2
–30
17.5
17.3
1760
–26
1820 1840 1860
f, FREQUENCY (MHz)
–34
1880
1900
ACPR (dBc)
18.2
–2.2
–2.3
–2.4
PARC (dB)
53
VDD = 28 Vdc, Pout = 28 W (Avg.), IDQA = 400 mA, VGSB = 0.65 Vdc
52
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB
51
@ 0.01% Probability on CCDF
50
D
49
18.3
D, DRAIN
EFFICIENCY (%)
TYPICAL CHARACTERISTICS
–2.5
–36
1920
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 28 Watts Avg.
0
VDD = 28 Vdc, Pout = 34 W (PEP), IDQA = 400 mA
VGSB = 0.65 Vdc, Two--Tone Measurements
(f1 + f2)/2 = Center Frequency of 1840 MHz
–15
IM3--U
–30
IM3--L
IM5--L
–45
IM5--U
–60
–75
IM7--L
1
IM7--U
10
100
200
TWO--TONE SPACING (MHz)
18
0
17.8
17.6
17.4
17.2
17
VDD = 28 Vdc, IDQA = 400 mA, VGSB = 0.65 Vdc
f = 1840 MHz, Single--Carrier W--CDMA
3.84 MHz Channel Bandwidth
D
–28
55
–30
ACPR
50
–1
–2
60
–1 dB = 16 W
–3
–4
–5
10
45
Gps
–2 dB = 26 W
40
–3 dB = 37 W
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
20
30
40
Pout, OUTPUT POWER (WATTS)
PARC
50
–32
–34
ACPR (dBc)
1
D DRAIN EFFICIENCY (%)
18.2
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
–36
35
–38
30
60
–40
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T18H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
1880 MHz
1805 MHz
Gps
Single--Carrier W--CDMA, 3.84 MHz Channel
Bandwidth, Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
1
55
–15
45
35
1840 MHz 1880 MHz
1805 MHz
12
10
ACPR
1805 MHz
1880 MHz
1840 MHz
14
–5
1840 MHz
18
16
65
10
Pout, OUTPUT POWER (WATTS) AVG.
100
25
15
5
200
–25
–35
–45
ACPR (dBc)
20
Gps, POWER GAIN (dB)
D
VDD = 28 Vdc, IDQA = 400 mA
VGSB = 0.65 Vdc
D, DRAIN EFFICIENCY (%)
22
–55
–65
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
24
21
Gain
GAIN (dB)
18
15
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 400 mA
VGSB = 0.65 Vdc
12
9
6
1500
1600
1700
1800 1900 2000
f, FREQUENCY (MHz)
2100
2200
2300
Figure 7. Broadband Frequency Response
A2T18H160--24SR3
6
RF Device Data
Freescale Semiconductor, Inc.
Table 7. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 408 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1805
2.25 – j8.58
2.61 + j7.74
1840
2.88 – j9.59
2.95 + j8.30
1880
4.30 – j10.4
3.95 + j8.89
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
4.68 – j7.50
20.1
48.7
73
61.5
–15
4.73 – j8.14
20.0
48.7
75
61.6
–15
4.76 – j8.44
20.0
48.6
72
60.2
–15
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
2.25 – j8.58
2.53 + j8.36
4.68 – j8.41
18.0
49.4
87
62.3
–22
1840
2.88 – j9.59
2.91 + j9.02
4.71 – j8.78
17.9
49.4
87
62.6
–23
1880
4.30 – j10.4
4.06 + j9.90
4.89 – j9.14
18.0
49.3
85
61.3
–22
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 8. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, IDQA = 408 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
2.25 – j8.58
2.13 + j7.81
7.94 – j3.73
22.2
47.2
52
71.5
–27
1840
2.88 – j9.59
2.33 + j8.41
7.67 – j3.36
22.1
47.0
50
71.9
–29
1880
4.30 – j10.4
3.13 + j9.13
7.25 – j3.56
22.3
46.9
49
71.0
–29
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
7.63 – j6.11
19.8
48.4
70
72.0
–31
2.41 + j8.94
7.53 – j5.64
19.7
48.3
67
72.3
–32
3.27 + j9.86
6.95 – j5.06
19.8
48.0
63
71.1
–34
f
(MHz)
Zsource
()
Zin
()
1805
2.25 – j8.58
2.17 + j8.29
1840
2.88 – j9.59
1880
4.30 – j10.4
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T18H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
7
Table 9. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 0.65 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1805
2.70 – j9.87
2.49 + j9.58
1840
3.29 – j10.6
2.89 + j10.3
1880
5.01 – j11.4
4.06 + j11.3
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
3.97 – j9.45
15.5
50.5
112
56.5
–30
3.81 – j9.81
15.4
50.5
113
55.7
–31
4.09 – j10.1
15.5
50.5
111
56.0
–31
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
2.70 – j9.87
2.51 + j10.1
3.84 – j9.87
13.3
51.2
132
56.6
–38
1840
3.29 – j10.6
2.95 + j10.8
3.92 – j10.2
13.3
51.2
133
57.0
–39
1880
5.01 – j11.4
4.34 + j12.1
4.17 – j10.5
13.4
51.1
129
56.7
–39
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 10. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, VGSB = 0.65 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
2.70 – j9.87
2.08 + j9.49
8.64 – j6.58
16.8
48.9
78
69.4
–35
1840
3.29 – j10.6
2.35 + j10.1
8.17 – j6.08
16.8
48.9
77
69.8
–36
1880
5.01 – j11.4
3.22 + j11.2
7.22 – j5.33
16.8
48.7
73
69.7
–36
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
8.72 – j7.75
14.6
49.7
92
67.9
–43
2.54 + j10.8
8.30 – j7.39
14.7
49.7
94
68.6
–44
3.64 + j12.1
7.94 – j6.26
14.8
49.4
87
68.3
–45
f
(MHz)
Zsource
()
Zin
()
1805
2.70 – j9.87
2.17 + j10.0
1840
3.29 – j10.6
1880
5.01 – j11.4
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T18H160--24SR3
8
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL CARRIER LOAD PULL CONTOURS — 1840 MHz
0
0
46
E
–4
–6
48.5
–8
48
–2
46.5
IMAGINARY ()
IMAGINARY ()
50 45.5
45
44.5
–2
47
47.5
P
E
–4
–6
70
–8
P
48
–10
–12
2
64
–10
47.5
47
4
6
8
REAL ()
12
10
–12
14
66
68
56
2
4
58
6
60
62
8
REAL ()
12
10
14
Figure 9. P1dB Load Pull Efficiency Contours (%)
Figure 8. P1dB Load Pull Output Power Contours (dBm)
0
0
23.5
–2
E
–4
IMAGINARY ()
IMAGINARY ()
–2
–6
21.5
–8
22
P
20.5
–10
–12
23
22.5
19.5
2
4
6
–4
–26
–24
–6
–22
–8
–20
P
21
–18
–10
20
8
REAL ()
10
12
14
Figure 10. P1dB Load Pull Gain Contours (dB)
NOTE:
–30
–28
E
–12
–16
–14
2
4
6
8
REAL ()
10
12
14
Figure 11. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
9
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 1840 MHz
0
0
46
45.5
64
46.5
–2
–2
47
IMAGINARY ()
IMAGINARY ()
–4
E
–6
48
47.5
–8
P
49
–4
–12
8
REAL ()
12
10
14
Figure 12. P3dB Load Pull Output Power Contours (dBm)
4
2
6
8
REAL ()
60
12
10
14
20.5
19.5
17.5 18.5
18
19
20
–2
21
IMAGINARY ()
–4
E
–6
–8
–36
–34
–4
–32
E
–6
–30
–8
P
P
–10
–10
–12
62
60
0
17
IMAGINARY ()
56 58
Figure 13. P3dB Load Pull Efficiency Contours (%)
0
–2
64
P
48.5
–12
6
66
70
–10
4
68
72
–8
–10
2
E
–6
2
4
6
8
REAL ()
10
12
14
Figure 14. P3dB Load Pull Gain Contours (dB)
NOTE:
–12
–20
2
–24
–22
4
–28
–26
6
8
REAL ()
10
12
14
Figure 15. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H160--24SR3
10
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL PEAKING LOAD PULL CONTOURS — 1840 MHz
0
0
46.5
–2
–2
47.5
–4
48
–6
E
48.5
–8
49
50
P
–10
0
2
4
10
12
14
–2
–2
–4
–4
E
IMAGINARY ()
IMAGINARY ()
0
16.5
–8
P
–14
16
0
2
60
4
6
8
REAL ()
10
12
14
Figure 18. P1dB Load Pull Gain Contours (dB)
NOTE:
58
56
0
2
4
6
8
REAL ()
–44
10
54
12
14
–42
–40
–38
–36
–6
E
–34
–8
–14
–32
P
–12
15.5
15
62
P
–10
14.5
13 14
13.5
68
Figure 17. P1dB Load Pull Efficiency Contours (%)
0
–12
E
–8
–14
Figure 16. P1dB Load Pull Output Power Contours (dBm)
–10
66
–6
–12
6
8
REAL ()
–6
64
–4
–10
49.5
–12
–14
IMAGINARY ()
IMAGINARY ()
62
47
–30
0
2
4
6
8
REAL ()
10
12
14
Figure 19. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
11
P3dB – TYPICAL PEAKING LOAD PULL CONTOURS — 1840 MHz
0
0
47
47.5
–2
48
–4
IMAGINARY ()
IMAGINARY ()
–2
48.5
–6
–10
P
–12
–14
49
E
–8
2
51
4
50
10
6
8
REAL ()
12
14
–14
–2
–4
–4
–6
14.5
E
–8
IMAGINARY ()
IMAGINARY ()
–2
–14
12
0
2
60
58
0
2
14
12.5
4
6
8
REAL ()
6
8
REAL ()
10
10
12
14
Figure 22. P3dB Load Pull Gain Contours (dB)
NOTE:
54
12
14
–48
–46
–6
–44
E
–8
–14
–42
–40
P
–38
–12
13.5
13
4
56
54
–50
–10
P
11.5
62
Figure 21. P3dB Load Pull Efficiency Contours (%)
0
11
68
P
52
49.5
0
–12
E
–8
–12
Figure 20. P3dB Load Pull Output Power Contours (dBm)
–10
64
–6
–10
50.5
0
66
–4
–36
0
2
4
6
8
REAL ()
10
12
14
Figure 23. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H160--24SR3
12
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2T18H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
13
A2T18H160--24SR3
14
RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
 AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
 EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
 Electromigration MTTF Calculator
 RF High Power Model
 s2p File
Development Tools
 Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.freescale.com/rf
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
Nov. 2015
Description
 Initial Release of Data Sheet
A2T18H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
15
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Document Number:
A2T18H160--24S
A2T18H160-24SR3
Rev. 0, 11/2015
16
RF Device Data
Freescale Semiconductor, Inc.