Data Sheet

Freescale Semiconductor
Technical Data
Document Number: A2T18H100--25S
Rev. 0, 10/2014
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 18 W asymmetrical Doherty RF power LDMOS transistor is designed for
cellular base station applications covering the frequency range of 1805 to
1995 MHz.
1800 MHz
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 230 mA, VGSB = 0.3 Vdc, Pout = 18 W Avg., Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
ACPR
(dBc)
1805 MHz
18.1
50.2
7.7
–31.0
1840 MHz
18.2
49.6
7.8
–33.0
1880 MHz
18.1
49.8
7.9
–34.4
A2T18H100--25SR3
1805–1995 MHz, 18 W AVG., 28 V
AIRFAST RF POWER LDMOS
TRANSISTOR
1900 MHz
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 210 mA, VGSB = 0.3 Vdc, Pout = 18 W Avg., Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
ACPR
(dBc)
1930 MHz
18.8
51.0
8.1
–31.3
1960 MHz
18.7
50.2
7.9
–32.7
1990 MHz
18.6
50.1
7.8
–33.3
NI--780S--4L4S
1
RFinA/VGSA
2
7 RFoutA/VDSA
RFinB/VGSB 3
6 RFoutB/VDSB
Features
 Advanced High Performance In--Package Doherty
 Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
 Designed for Digital Predistortion Error Correction Systems
 In Tape and Reel. R3 Suffix = 250 Units, 44 mm Tape Width, 13--inch Reel.
 Freescale Semiconductor, Inc., 2014. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
8 VBWA(1)
N.C.
N.C.
Carrier
4 Peaking
5 VBWB(1)
(Top View)
Figure 1. Pin Connections
1. Device cannot operate with the VDD current
supplied through pin 5 and pin 8.
A2T18H100--25SR3
1
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain--Source Voltage
Rating
VDSS
–0.5, +65
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
Case Operating Temperature Range
TC
–40 to +150
C
TJ
–40 to +225
C
CW
135
1.8
W
W/C
Operating Junction Temperature Range
(1,2)
CW Operation @ TC = 25C
Derate above 25C
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 78C, 18 W Avg. W--CDMA, 28 Vdc, IDQA = 230 mA, VGSB = 0.3 Vdc,
1840 MHz
Symbol
Value (2,3)
Unit
RJC
0.74
C/W
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
2
Machine Model (per EIA/JESD22--A115)
B
Charge Device Model (per JESD22--C101)
IV
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 40 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Gate Quiescent Voltage
(VDD = 28 Vdc, IDA = 230 mAdc, Measured in Functional Test)
VGS(Q)
1.5
1.8
2.3
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 0.4 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 60 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 0.6 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Characteristic
Off Characteristics (4)
On Characteristics -- Side A (4) (Carrier)
On Characteristics -- Side B (4) (Peaking)
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf.
Select Documentation/Application Notes -- AN1955.
4. Each side of device measured separately.
(continued)
A2T18H100--25SR3
2
RF Device Data
Freescale Semiconductor, Inc.
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests (1,2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 230 mA, VGSB = 0.3 Vdc, Pout = 18 W Avg.,
f = 1805 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in
3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
17.6
18.1
20.6
dB
Drain Efficiency
D
48.3
50.2
—
%
PAR
7.3
7.7
—
dB
ACPR
—
–31.0
–28.6
dBc
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Load Mismatch (2) (In Freescale Doherty Test Fixture, 50 ohm system) IDQA = 230 mA, VGSB = 0.3 Vdc, f = 1840 MHz
No Device Degradation
VSWR 10:1 at 32 Vdc, 100 W Pulse Output Power
(3 dB Input Overdrive from 72 W Pulse Rated Power)
Typical Performance (2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 230 mA, VGSB = 0.3 Vdc,
1805–1880 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
72
—
W
Pout @ 3 dB Compression Point (3)
P3dB
—
112
—
W

—
–13.5
—

VBWres
—
110
—
MHz
Gain Flatness in 75 MHz Bandwidth @ Pout = 18 W Avg.
GF
—
0.1
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.01
—
dB/C
P1dB
—
0.004
—
dB/C
AM/PM
(Maximum value measured at the P3dB compression point across
the 1805–1880 MHz frequency range)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30C to +85C) (4)
1. Part internally matched both on input and output.
2. Measurements made with device in an asymmetrical Doherty configuration.
3. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
4. Exceeds recommended operating conditions. See CW operation data in Maximum Ratings table.
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
3
VGGA
VDDA
C10
R2
C1
A2T18H100--25S
Rev. 1
C12
R3
C2
C14
C13
C
C5
P
R1
C7 C6
C8
CUT OUT AREA
C4 C3
Z1
C11
C15
C16
C18
C17
C21
C19
C20
D60962
R4
C9
C23
C22
R5
C24
VGGB
VDDB
Figure 2. A2T18H100--25SR3 Test Circuit Component Layout
Table 5. A2T18H100--25SR3 Test Circuit Component Designations and Values
Part
C1, C9, C11, C13, C21, C23
Description
10 F Chip Capacitors
Part Number
Manufacturer
C5750X7S2A106M230KB
TDK
C2, C4, C5, C8, C12, C17, C22 12 pF Chip Capacitors
ATC600F120JT250XT
ATC
C3, C6
2.0 pF Chip Capacitors
ATC600F2R0BT250XT
ATC
C7, C14, C15
0.2 pF Chip Capacitors
ATC600F0R2BT250XT
ATC
C10, C24
220 F Electrolytic Capacitors
227CKS050M
Illinois Capacitor
C16
15 pF Chip Capacitor
ATC600F150JT250XT
ATC
C18
1.5 pF Chip Capacitor
ATC600F1R5BT250XT
ATC
C19
0.3 pF Chip Capacitor
ATC600F0R3BT250XT
ATC
C20
0.5 pF Chip Capacitor
ATC600F0R5BT250XT
ATC
R1
50 , 4 W Chip Resistor
C10A50Z4
Anaren
R2, R5
10 K, 1/4 W Chip Resistors
CRCW120610K0JNEA
Vishay
R3, R4
5.6 , 1/4 W Chip Resistors
CRCW12065R60FKEA
Vishay
Z1
1700–2000 MHz Band, 90, 5 dB Directional Coupler
X3C19P1--05S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D60962
MTL
A2T18H100--25SR3
4
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS — 1805–1880 MHz
52
51
D
18
50
49
Gps
17.9
PARC
17.8
17.7
17.4
1760
1780
1800
1820
1840
–30
–2.1
–34
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF
17.5
–2
–32
ACPR
17.6
–28
1860
1880
–36
–38
1920
1900
–2.2
–2.3
–2.4
PARC (dB)
18.2
18.1
D, DRAIN
EFFICIENCY (%)
18.3
Gps, POWER GAIN (dB)
53
VDD = 28 Vdc, Pout = 18 W (Avg.), IDQA = 230 mA
VGSB = 0.3 Vdc, Single--Carrier W--CDMA
ACPR (dBc)
18.4
–2.5
f, FREQUENCY (MHz)
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 18 Watts Avg.
–10
VDD = 28 Vdc, Pout = 11 W (PEP), IDQA = 230 mA
VGSB = 0.3 Vdc, Two--Tone Measurements
(f1 + f2)/2 = Center Frequency of 1840 MHz
–20
–30
IM3–U
–40
IM3–L
IM5–U
IM5–L
–50
IM7–L
–60
–70
1
IM7–U
10
300
100
TWO–TONE SPACING (MHz)
18.4
0
18.2
18
17.8
17.6
17.4
VDD = 28 Vdc, IDQA = 230 mA, VGSB = 0.3 Vdc
f = 1840 MHz, Single--Carrier W--CDMA
PARC
D
ACPR
–1
55
–30
45
Gps
–2 dB = 17.8 W
–3
–28
50
–1 dB = 10 W
–2
60
40
–3 dB = 25.5 W
–4
–5
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
6
12
18
24
30
36
–32
–34
ACPR (dBc)
1
D DRAIN EFFICIENCY (%)
18.6
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
–36
35
–38
30
42
–40
Pout, OUTPUT POWER (WATTS)
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS —1805–1880 MHz
D
1880 MHz
1805 MHz 1840 MHz
1880 MHz
1840 MHz
1805 MHz
1
60
–10
40
14
10
0
ACPR 50
1805 MHz
1840 MHz
16
1880 MHz
12
70
30
Gps
20
10
100
10
–20
–30
–40
ACPR (dBc)
VDD = 28 Vdc, IDQA = 230 mA, VGSB = 0.3 Vdc
Single--Carrier W--CDMA, 3.84 MHz Channel
20 Bandwidth, Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
18
D, DRAIN EFFICIENCY (%)
Gps, POWER GAIN (dB)
22
–50
–60
Pout, OUTPUT POWER (WATTS) AVG.
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
20
Gain
18
GAIN (dB)
16
14
12
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 230 mA
VGSB = 0.3 Vdc
10
8
1520
1640
1760
1880
2000
2120
2240
f, FREQUENCY (MHz)
Figure 7. Broadband Frequency Response
A2T18H100--25SR3
6
RF Device Data
Freescale Semiconductor, Inc.
Table 6. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 220 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1805
3.10 – j9.64
2.64 + j8.40
1840
3.86 – j10.4
3.15 + j9.05
1880
5.48 – j12.0
4.24 + j9.95
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
7.58 – j6.56
20.7
47.1
51
60.1
–17
7.84 – j7.07
20.8
47.1
52
60.9
–17
7.86 – j7.57
20.5
47.1
51
60.0
–18
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
3.10 – j9.64
2.63 + j9.04
7.90 – j7.83
18.7
47.9
62
62.4
–24
1840
3.86 – j10.4
3.22 + j9.82
8.27 – j8.61
18.7
47.9
61
62.3
–23
1880
5.48 – j12.0
4.50 + j11.0
8.12 – j8.81
18.4
47.8
60
61.0
–24
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 7. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, IDQA = 220 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
3.10 – j9.64
2.11 + j8.69
13.4 + j2.62
23.5
44.8
30
70.7
–31
1840
3.86 – j10.4
2.41 + j9.41
9.97 + j2.82
23.2
44.7
30
70.7
–34
1880
5.48 – j12.0
3.44 + j10.5
11.2 + j1.90
23.1
44.8
30
69.3
–32
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
11.4 + j1.85
21.2
45.5
36
70.7
–40
2.68 + j9.75
10.7 – j2.03
20.4
46.6
46
71.2
–33
3.61 + j11.0
10.0 – j1.27
20.4
46.3
42
69.8
–36
f
(MHz)
Zsource
()
Zin
()
1805
3.10 – j9.64
2.00 + j9.01
1840
3.86 – j10.4
1880
5.48 – j12.0
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
7
Table 8. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 0.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1805
2.70 – j9.87
2.73 + j10.3
1840
3.29 – j10.6
3.49 + j11.2
1880
4.36 – j11.7
4.91 + j12.4
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
5.16 – j7.84
15.4
48.6
73
62.6
–32
4.48 – j8.40
15.2
48.8
76
61.3
–31
4.66 – j8.54
15.3
48.7
74
62.1
–33
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
2.70 – j9.87
2.83 + j11.0
5.72 – j8.86
13.5
49.4
87
66.3
–40
1840
3.29 – j10.6
3.66 + j12.0
4.98 – j8.96
13.3
49.5
90
64.8
–40
1880
4.36 – j11.7
5.52 + j13.6
4.98 – j9.54
13.2
49.4
87
62.9
–41
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 9. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, VGSB = 0.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
2.70 – j9.87
1.83 + j10.1
11.6 + j1.19
16.5
45.3
34
75.3
–47
1840
3.29 – j10.6
2.54 + j10.9
9.30 – j2.73
16.6
46.7
46
75.4
–41
1880
4.36 – j11.7
3.68 + j12.3
7.61 – j3.66
16.5
46.9
49
74.9
–42
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
9.02 – j5.68
14.5
48.2
66
75.1
–48
3.02 + j11.8
8.66 – j5.26
14.5
48.1
64
75.8
–50
4.41 + j13.5
8.13 – j4.93
14.5
47.8
60
75.0
–53
f
(MHz)
Zsource
()
Zin
()
1805
2.70 – j9.87
2.44 + j10.9
1840
3.29 – j10.6
1880
4.36 – j11.7
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T18H100--25SR3
8
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 1840 MHz
10
10
43
43.5
5
IMAGINARY ()
E
0
44.5
46
–5
P
45
45.5
46.5
47
–10
E
70
0
68
66
–5
64
P
62
60
–10
56
58
54
REAL ()
54 56
10
15
REAL ()
Figure 8. P1dB Load Pull Output Power Contours (dBm)
Figure 9. P1dB Load Pull Efficiency Contours (%)
–15
IMAGINARY ()
44
0
10
5
15
20
–15
25
10
10
5
5
24
E
IMAGINARY ()
IMAGINARY ()
5
0
23
–5
P
–10
–15
23.5
22
5
10
15
REAL ()
5
–34
0
–32
–30
–22
–5
–20
–18
–10
25
25
–24
P
20
20
–28
–26
E
22.5
20.5
21 21.5
20
0
0
–15
0
5
10
15
20
25
REAL ()
Figure 10. P1dB Load Pull Gain Contours (dB)
NOTE:
Figure 11. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
9
P3dB – TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 1840 MHz
10
10
44
5
44.5
IMAGINARY ()
IMAGINARY ()
5
0
45
E
45.5
46
–5
47.5
P
–10
0
E
0
10
5
15
20
–15
25
62
60
P
–10
58
56
–15
64
66
–5
46.5
47
68
70
0
10
5
56
58
15
20
25
REAL ()
Figure 12. P3dB Load Pull Output Power Contours (dBm)
Figure 13. P3dB Load Pull Efficiency Contours (%)
10
10
5
5
IMAGINARY ()
IMAGINARY ()
REAL ()
0
21.5
E
21
–5
P
–10
17.5
–15
0
20
10
15
REAL ()
25
–30
–28
E
–5
–26
–15
–24
P
–10
20
–32
–34
0
20.5
18.5
19.5
19
18
5
–36
–22
–20
0
5
10
15
20
25
REAL ()
Figure 14. P3dB Load Pull Gain Contours (dB)
NOTE:
Figure 15. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H100--25SR3
10
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 1840 MHz
10
10
5
5
45
0
45.5
E
46
–5
P
–10
–15
IMAGINARY ()
IMAGINARY ()
62
48.5
47
48
0
46.5
0
E
72
74
–5
68
66
P
–10
64
47.5
10
5
15
20
–15
25
70
0
10
5
60
62
15
20
25
REAL ()
REAL ()
Figure 16. P1dB Load Pull Output Power Contours (dBm)
Figure 17. P1dB Load Pull Efficiency Contours (%)
10
12.5 13.5
13
5
10
14.5
15
14
15.5
–46
5
IMAGINARY ()
IMAGINARY ()
16
0
16.5
E
–5
P
–10
–15
0
–44
–42
0
10
15
REAL ()
20
25
–38
–5
–36
–15
–34
P
–10
5
–40
E
–32
–30
0
5
10
15
20
25
REAL ()
Figure 18. P1dB Load Pull Gain Contours (dB)
NOTE:
Figure 19. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
11
10
10
5
5
45.5
0
IMAGINARY ()
IMAGINARY ()
P3dB – TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 1840 MHz
46
–5
E
P
–10
–15
47
48 47.5
49
0
46.5
0
74
–5
E
70
68
64
66
62
P
–10
60
48.5
10
5
72
15
20
–15
25
60
0
10
5
15
20
25
REAL ()
REAL ()
Figure 20. P3dB Load Pull Output Power Contours (dBm)
Figure 21. P3dB Load Pull Efficiency Contours (%)
10
5
10.5 11.5
11 12
10
12.5
13 13.5
–54
5
–52
–50
0
IMAGINARY ()
IMAGINARY ()
14
14.5
–5
E
0
–48
–5
–46
E
–44
P
–10
–15
0
5
–10
10
15
REAL ()
20
25
–15
–42
P
–40
–38
0
5
10
15
20
25
REAL ()
Figure 22. P3dB Load Pull Gain Contours (dB)
NOTE:
Figure 23. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H100--25SR3
12
RF Device Data
Freescale Semiconductor, Inc.
VGGA
VDDA
C10
R2
C1
A2T18H100--25S
Rev. 1
C2
C11
R3
C3
Z1
C
C4
R1
C6
C5
C7
P
CUT OUT AREA
C13
C14
C16
C17
C15
C18
C19
C20
C12
R4
D63198
C9
C8
R5
C21
VGGB
VDDB
Figure 24. A2T18H100–25SR3 Test Circuit Component Layout — 1930–1990 MHz
Table 10. A2T18H100–25SR3 Test Circuit Component Designations and Values — 1930–1990 MHz
Part
C1, C8, C9, C11, C13, C15
Description
10 F Chip Capacitors
Part Number
Manufacturer
C5750X7S2A106M230KB
TDK
C2, C4, C5, C7, C12, C14, C17 10 pF Chip Capacitors
ATC600F100JT250XT
ATC
C3, C6, C18, C19, C20
1.0 pF Chip Capacitors
ATC600F1R0BT250XT
ATC
C10, C21
220 F Electrolytic Capacitors
227CKS050M
Illinois Capacitor
C16
6.8 pF Chip Capacitor
ATC600F6R8JT250XT
ATC
R1
50 , 4 W Chip Resistor
C10A50Z4
Anaren
R2, R5
10 K,1/4 W Chip Resistors
CRCW120610K0JNEA
Vishay
R3, R4
5.6 , 1/4 W Chip Resistors
CRCW12065R60FKEA
Vishay
Z1
1700–2000 MHz Band, 90, 5 dB Directional Coupler
X3C19P1--05S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D63198
MTL
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
13
TYPICAL CHARACTERISTICS — 1930–1990 MHz
Gps, POWER GAIN (dB)
18.6
52
51
18.5
50
Gps
18.4
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @
0.01% Probability on CCDF
18.3
18.2
49
ACPR
18.1
18
17.8
1880
1900
1920
–1.7
–28
–1.8
–30
–32
PARC
17.9
–26
–34
1940
1960
1980
2000
2020
–1.9
–2
–2.1
PARC (dB)
D
D, DRAIN
EFFICIENCY (%)
18.7
53
VDD = 28 Vdc, Pout = 18 W (Avg.), IDQA = 210 mA
VGSB = 0.3 Vdc, Single--Carrier W--CDMA
ACPR (dBc)
18.8
–2.2
–36
2040
f, FREQUENCY (MHz)
Figure 25. Single--Carrier Output Peak--to--Average Ratio
Compression (PARC) Broadband Performance @ Pout = 18 Watts Avg.
VDD = 28 Vdc, IDQA = 210 mA, VGSB = 0.3 Vdc
Single--Carrier W--CDMA
1930 MHz
1990 MHz
18
16
ACPR
1930 MHz
1960 MHz
1960 MHz
1930 MHz
50
30
Gps
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
10
–10
40
1990 MHz
12
60
1960 MHz
1990 MHz
14
0
1
100
10
20
10
200
–20
–30
–40
ACPR (dBc)
Gps, POWER GAIN (dB)
20
70
D
D, DRAIN EFFICIENCY (%)
22
–50
–60
Pout, OUTPUT POWER (WATTS) AVG.
Figure 26. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
22
20
Gain
GAIN (dB)
18
16
14
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 210 mA
VGSB = 0.3 Vdc
12
10
1650
1750
1850
1950
2050
2150
2250
f, FREQUENCY (MHz)
Figure 27. Broadband Frequency Response
A2T18H100--25SR3
14
RF Device Data
Freescale Semiconductor, Inc.
Table 11. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 225 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1930
6.95 – j11.7
6.81 + j11.8
8.24 – j7.42
20.9
46.9
49
59.7
–17
1960
9.04 – j12.5
9.10 + j12.5
8.42 – j7.78
20.9
46.9
49
59.2
–17
1990
12.4 – j12.5
12.4 + j12.5
8.77 – j8.20
20.9
46.9
49
59.2
–17
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1930
6.95 – j11.7
7.67 + j13.2
8.88 – j8.79
18.8
47.7
59
61.0
–23
1960
9.04 – j12.5
10.7 + j14.0
9.21 – j9.12
18.8
47.6
58
60.4
–24
1990
12.4 – j12.5
15.2 + j13.7
9.53 – j9.42
18.8
47.6
58
60.2
–23
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 12. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, IDQA = 225 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1930
6.95 – j11.7
5.67 + j12.7
9.34 + j1.29
23.6
44.8
30
69.3
–30
1960
9.04 – j12.5
7.70 + j14.1
8.67 + j1.27
23.7
44.7
29
68.7
–32
1990
12.4 – j12.5
11.3 + j14.7
8.79 – j0.32
23.4
45.2
33
68.5
–29
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
9.40 – j2.09
20.7
46.5
45
70.0
–34
9.05 + j15.0
8.90 – j1.90
20.7
46.3
43
69.6
–36
13.5 + j15.9
8.85 – j2.14
20.8
46.3
43
69.4
–36
f
(MHz)
Zsource
()
Zin
()
1930
6.95 – j11.7
6.47 + j13.6
1960
9.04 – j12.5
1990
12.4 – j12.5
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
15
Table 13. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 0.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1930
7.81 – j13.5
8.18 + j14.2
1960
10.9 – j13.4
11.7 + j14.6
1990
15.1 – j12.6
16.9 + j13.0
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
5.37 – j9.73
15.2
48.7
74
62.3
–35
5.10 – j10.0
15.0
48.6
73
61.2
–34
5.22 – j10.2
15.1
48.6
73
61.4
–34
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1930
7.81 – j13.5
9.83 + j15.5
5.37 – j10.2
13.1
49.4
87
63.0
–43
1960
10.9 – j13.4
14.9 + j15.5
5.58 – j11.1
12.9
49.3
85
61.6
–42
1990
15.1 – j12.6
21.3 + j11.5
5.66 – j11.2
12.9
49.3
85
61.7
–42
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 14. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, VGSB = 0.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1930
7.81 – j13.5
6.12 + j14.4
7.59 – j4.05
16.3
46.8
48
74.5
–42
1960
10.9 – j13.4
9.00 + j15.9
7.52 – j4.23
16.3
46.8
47
74.4
–41
1990
15.1 – j12.6
13.3 + j17.0
6.67 – j3.25
16.2
46.1
40
73.7
–45
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
7.55 – j5.06
14.3
47.7
58
74.6
–55
12.1 + j17.4
7.63 – j4.65
14.3
47.4
55
74.4
–54
19.7 + j16.0
7.35 – j5.75
14.2
47.6
58
73.5
–53
f
(MHz)
Zsource
()
Zin
()
1930
7.81 – j13.5
7.85 + j16.0
1960
10.9 – j13.4
1990
15.1 – j12.6
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T18H100--25SR3
16
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 1960 MHz
10
10
43
45
45.5
46
–5
46.5
P
–10
43
2
IMAGINARY ()
IMAGINARY ()
44
44.5
E
0
–15
5
43.5
5
66
–5
62
58
–10
64
60
56
54
43.5
4
6
8
REAL ()
10
–15
14
12
2
4
6
8
REAL ()
10
52
12
14
Figure 29. P1dB Load Pull Efficiency Contours (%)
10
10
5
5
24.5
24
E
0
23.5
23
22.5
–5
P
22
21.5
–10
4
6
8
REAL ()
10
–26
0
–24
–22
–20
–5
–18
–10
12
14
Figure 30. P1dB Load Pull Gain Contours (dB)
NOTE:
–32 –30 –28
E
P
21
20.5
2
IMAGINARY ()
IMAGINARY ()
68
P
Figure 28. P1dB Load Pull Output Power Contours (dBm)
–15
E
0
–15
–16
2
4
6
8
REAL ()
10
12
14
Figure 31. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
17
P3dB – TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 1960 MHz
10
10
43.5
44
44.5
45
45.5
0
E
46
46.5
–5
47
–5
43.5
4
6
8
REAL ()
10
12
–15
14
10
5
5
E
21
20.5
–5
6
8
REAL ()
10
58
4
6
8
REAL ()
10
60
54
12
14
–36
–38
–34
–32
–30
–28
0
E
–5
–26
–24
P
–22
12
14
Figure 34. P3dB Load Pull Gain Contours (dB)
NOTE:
2
–10
19
18.5
18
4
20
19.5
P
–10
IMAGINARY ()
22
21.5
0
2
62
P
Figure 33. P3dB Load Pull Efficiency Contours (%)
10
–15
66
64
56
Figure 32. P3dB Load Pull Output Power Contours (dBm)
IMAGINARY ()
E
–10
44
2
68
0
47.5
P
–10
–15
5
IMAGINARY ()
IMAGINARY ()
5
–15
2
4
6
8
REAL ()
10
12
14
Figure 35. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H100--25SR3
18
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 1960 MHz
0
–2
0
45
44.5
45.5
–2
46
E
–4
46.5
IMAGINARY ()
IMAGINARY ()
–4
–6
47
–8
–10
–14
48
48.5
0
4
2
6
8
REAL ()
47.5
10
72
70
68
–8
66
P
64
–12
12
–14
14
Figure 36. P1dB Load Pull Output Power Contours (dBm)
0
2
4
62
60
58
6
8
REAL ()
10
12
14
Figure 37. P1dB Load Pull Efficiency Contours (%)
0
0
14 14.5
13.5
15.5
15
16
–4
12.5
–8
–10
–14
–14
6
8
REAL ()
10
12
14
Figure 38. P1dB Load Pull Gain Contours (dB)
NOTE:
–38
–36
–8
–12
4
–42
–6
–12
2
–40
E
–34
–10
P
0
–46
–4
E
13
–6
–44
–2
IMAGINARY ()
–2
IMAGINARY ()
E
–6
–10
P
–12
74
P
–32
0
2
4
6
8
REAL ()
10
12
14
Figure 39. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
19
P3dB – TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 1960 MHz
0
0
45.5
–2
–2
–4
E
47
–6
47.5
–8
48
48.5
49
–10
0
4
2
6
8
REAL ()
10
12
–14
14
72
70
68
66
P
58 60
0
4
2
64
62
6
8
REAL ()
10
12
14
Figure 41. P3dB Load Pull Efficiency Contours (%)
0
0
12.5
11.5
–4
13.5
14
13
–4
E
11
–6
–2
IMAGINARY ()
12
–2
IMAGINARY ()
E
–8
–12
Figure 40. P3dB Load Pull Output Power Contours (dBm)
10.5
–8
–10
–56
–52
–54
–50
E
–48
–6
–46
–8
–44
–10
P
–12
–14
74
–6
–10
P
–12
–14
IMAGINARY ()
–4
IMAGINARY ()
46
46.5
0
2
4
6
8
REAL ()
10
12
14
Figure 42. P3dB Load Pull Gain Contours (dB)
NOTE:
–14
–42
P
–12
–40
0
2
–40
4
6
8
REAL ()
10
12
14
Figure 43. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T18H100--25SR3
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RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2T18H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
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A2T18H100--25SR3
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RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
 AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
 EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
 Electromigration MTTF Calculator
 RF High Power Model
 .s2p File
Development Tools
 Printed Circuit Boards
For Software and Tools, do a Part Number search at http://www.freescale.com, and select the “Part Number” link. Go to
Software & Tools on the part’s Product Summary page to download the respective tool.
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
Oct. 2014
Description
 Initial Release of Data Sheet
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RF Device Data
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A2T18H100--25SR3
Document Number: A2T18H100--25S
Rev. 0, 10/2014
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RF Device Data
Freescale Semiconductor, Inc.