Data Sheet

Freescale Semiconductor
Technical Data
Document Number: A2T23H160--24S
Rev. 0, 11/2015
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 28 W asymmetrical Doherty RF power LDMOS transistor is designed for
cellular base station applications covering the frequency range of 2300 to
2400 MHz.
A2T23H160--24SR3
2300 MHz
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 350 mA, VGSB = 0.7 Vdc, Pout = 28 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
ACPR
(dBc)
2300 MHz
17.7
48.8
7.9
–33.5
2350 MHz
17.7
48.4
8.0
–37.2
2400 MHz
17.8
48.2
7.9
–37.0
2300–2400 MHz, 28 W AVG., 28 V
AIRFAST RF POWER LDMOS
TRANSISTOR
Features
 Advanced High Performance In--Package Doherty
 Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
 Designed for Digital Predistortion Error Correction Systems
NI--780S--4L2L
6 VBWA(1)
Carrier
RFinA/VGSA 1
5 RFoutA/VDSA
RFinB/VGSB 2
4 RFoutB/VDSB
Peaking
3 VBWB(1)
(Top View)
Figure 1. Pin Connections
1. Device cannot operate with VDD current
supplied through pin 3 and pin 6.
 Freescale Semiconductor, Inc., 2015. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
A2T23H160--24SR3
1
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain--Source Voltage
Rating
VDSS
–0.5, +65
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
Case Operating Temperature Range
TC
–40 to +150
C
(1,2)
TJ
–40 to +225
C
Characteristic
Symbol
Value (2,3)
Unit
RJC
0.49
C/W
Operating Junction Temperature Range
Table 2. Thermal Characteristics
Thermal Resistance, Junction to Case
Case Temperature 73C, 28 W Avg., W--CDMA, 28 Vdc, IDQA = 350 mA,
VGSB = 0.7 Vdc, 2350 MHz
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
2
Machine Model (per EIA/JESD22--A115)
B
Charge Device Model (per JESD22--C101)
IV
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 60 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Gate Quiescent Voltage
(VDD = 28 Vdc, ID = 350 mAdc, Measured in Functional Test)
VGSA(Q)
1.4
1.8
2.2
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 0.6 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 100 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 1.0 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Characteristic
Off Characteristics
(4)
On Characteristics -- Side A, Carrier
On Characteristics -- Side B, Peaking
1.
2.
3.
4.
Continuous use at maximum temperature will affect MTTF.
MTTF calculator available at http://www.freescale.com/rf/calculators.
Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf and search for AN1955.
Each side of device measured separately.
(continued)
A2T23H160--24SR3
2
RF Device Data
Freescale Semiconductor, Inc.
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests (1,2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 350 mA, VGSB = 0.7 Vdc, Pout = 28 W Avg.,
f = 2300 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in
3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
17.1
17.7
20.1
dB
Drain Efficiency
D
46.5
48.8
—
%
PAR
7.4
7.9
—
dB
ACPR
—
–33.5
–30.0
dBc
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Load Mismatch (2) (In Freescale Doherty Test Fixture, 50 ohm system) IDQA = 350 mA, VGSB = 0.7 Vdc, f = 2350 MHz
No Device Degradation
VSWR 10:1 at 32 Vdc, 151 W CW Output Power
(3 dB Input Overdrive from 120 W CW Rated Power)
Typical Performance (2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 350 mA, VGSB = 0.7 Vdc,
2300–2400 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
120
—
W
Pout @ 3 dB Compression Point (3)
P3dB
—
178
—
W

—
–18
—

VBWres
—
150
—
MHz
Gain Flatness in 100 MHz Bandwidth @ Pout = 28 W Avg.
GF
—
0.5
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.009
—
dB/C
P1dB
—
0.006
—
dB/C
AM/PM
(Maximum value measured at the P3dB compression point across
the 2300–2400 MHz frequency range)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30C to +85C)
Table 5. Ordering Information
Device
A2T23H160--24SR3
Tape and Reel Information
R3 Suffix = 250 Units, 44 mm Tape Width, 13--inch Reel
Package
NI--780S--4L2L
1. Part internally matched both on input and output.
2. Measurements made with device in an asymmetrical Doherty configuration.
3. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
A2T23H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
3
VDDA
VGGA
C20
R4
C18
C22
C14
R2
Z1
C6
C2
C11
C10
R3
C15
CUT OUT AREA
C5
C1
R1
C24
C16
C
C4
C13
C8
P C3
C7
C12
C17
C9
C19
D63616
C23
A2T23H160--24S
Rev. 1
VGGB
VDDB
R5
C21
Figure 2. A2T23H160--24SR3 Test Circuit Component Layout
Table 6. A2T23H160--24SR3 Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1, C2, C3, C9, C22, C23,
C24
9.1 pF Chip Capacitors
ATC600F9R1JT250XT
ATC
C4
6.8 pF Chip Capacitor
ATC600F6R8JT250XT
ATC
C5, C6
0.4 pF Chip Capacitors
ATC600F0R4BT250XT
ATC
C7, C8
0.2 pF Chip Capacitors
ATC600F0R2BT250XT
ATC
C10
0.3 pF Chip Capacitor
ATC600F0R3BT250XT
ATC
C11
1.0 pF Chip Capacitor
ATC600F1R0BT250XT
ATC
C12
0.9 pF Chip Capacitor
ATC600F0R9BT250XT
ATC
C13
0.6 pF Chip Capacitor
ATC600F0R6BT250XT
ATC
C14, C15, C16, C17, C18,
C19
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C20, C21
470 F, 50 V Electrolytic Capacitors
477CKS050M
Illinois
R1
50 , 20 W Chip Resistor
C20N50Z4
Anaren
R2, R3
2.2 , 1/4 W Chip Resistors
CRCW12062R20JNEA
Vishay
R4, R5
10 K, 1/4 W Chip Resistors
CRCW120610K0JNEA
Vishay
Z1
2300–2700 MHz Band, 90, 2 dB Directional Coupler
X3C25P1-02S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D63616
MTL
A2T23H160--24SR3
4
RF Device Data
Freescale Semiconductor, Inc.
17.95
Gps, POWER GAIN (dB)
48.8
D
48.6
VDD = 28 Vdc, Pout = 28 W (Avg.), IDQA = 350 mA
VGSB = 0.7 Vdc, Single--Carrier W--CDMA, 3.84 MHz
Channel Bandwidth, Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
17.9
17.85
17.8
48.4
48.2
Gps
17.75
17.7
PARC
17.65
17.6
2305
2320
2335 2350 2365
f, FREQUENCY (MHz)
2380
–1.6
–34
–1.8
–35
–36
–37
ACPR
17.55
2290
–33
ACPR (dBc)
18
2395
–2
–2.2
–2.4
PARC (dB)
49
18.05
D, DRAIN
EFFICIENCY (%)
TYPICAL CHARACTERISTICS
–2.6
–38
2410
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 28 Watts Avg.
–10
VDD = 28 Vdc, Pout = 56 W (PEP), IDQA = 350 mA
VGSB = 0.7 Vdc, Two--Tone Measurements
(f1 + f2)/2 = Center Frequency of 2350 MHz
–20
IM3--U
–30
IM3--L
–40
IM5--L IM5--U
–50
–60
IM7--U
IM7--L
1
300
100
10
TWO--TONE SPACING (MHz)
19
0
18.5
18
17.5
17
16.5
VDD = 28 Vdc, IDQA = 350 mA, VGSB = 0.7 Vdc, f = 2350 MHz
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
ACPR
90
–25
80
–30
70
–1
–2 –1 dB = 20.9 W
–2 dB = 29.6 W
D
–3 dB = 39.7 W
–3
60
50
Gps
–4
–5
10
PARC
20
30
40
50
Pout, OUTPUT POWER (WATTS)
60
–35
–40
ACPR (dBc)
1
D DRAIN EFFICIENCY (%)
19.5
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
–45
40
–50
30
70
–55
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T23H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
Gps, POWER GAIN (dB)
20
18
16
Gps
2300 MHz
D
14
ACPR
12
10
1
2400 MHz
60
2300 MHz 50
2350 MHz
40
2400 MHz 2350 MHz
30
2300 MHz
2400 MHz 2350 MHz
20
10
0
100
10
Pout, OUTPUT POWER (WATTS) AVG.
0
–10
–20
–30
–40
ACPR (dBc)
VDD = 28 Vdc, IDQA = 350 mA, VGSB = 0.7 Vdc
Single--Carrier W--CDMA, 3.84 MHz Channel
Bandwidth, Input Signal PAR = 9.9 dB @
0.01% Probability on CCDF
D, DRAIN EFFICIENCY (%)
22
–50
–60
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
22
20
Gain
GAIN (dB)
18
16
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 350 mA
VGSB = 0.7 Vdc
14
12
10
1900
2000
2100
2200 2300 2400
f, FREQUENCY (MHz)
2500
2600
2700
Figure 7. Broadband Frequency Response
A2T23H160--24SR3
6
RF Device Data
Freescale Semiconductor, Inc.
Table 7. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 348 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
11.3 – j16.2
18.4
48.2
66
55.7
–13
10.6 – j15.1
18.6
48.2
66
55.4
–14
18.8
48.2
66
56.2
–14
f
(MHz)
Zsource
()
Zin
()
2300
8.42 – j15.0
10.6 + j13.0
2350
10.8 – j13.6
11.8 + j11.0
2400
11.0 – j11.3
11.5 + j8.59
9.72 – j14.0
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2300
8.42 – j15.0
12.1 + j13.1
11.3 – j17.2
16.3
49.0
80
57.0
–17
2350
10.8 – j13.6
13.1 + j10.2
10.8 – j16.9
16.3
49.0
79
56.0
–18
2400
11.0 – j11.3
12.3 + j7.27
10.3 – j15.7
16.6
49.0
79
57.2
–18
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 8. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, IDQA = 348 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2300
8.42 – j15.0
10.6 + j13.6
15.7 – j1.67
21.8
46.0
40
66.3
–23
2350
10.8 – j13.6
11.6 + j11.4
14.0 – j3.17
21.7
46.2
42
65.8
–22
2400
11.0 – j11.3
11.4 + j8.97
11.5 – j4.73
21.6
46.5
44
65.8
–22
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
15.6 – j4.42
19.3
47.2
52
67.0
–29
12.9 + j10.6
13.5 – j4.16
19.5
47.1
51
66.4
–31
12.1 + j7.68
11.3 – j5.87
19.3
47.4
55
66.6
–30
f
(MHz)
Zsource
()
Zin
()
2300
8.42 – j15.0
11.9 + j13.5
2350
10.8 – j13.6
2400
11.0 – j11.3
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T23H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
7
Table 9. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 0.7 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
2300
17.3 – j13.1
17.6 + j14.6
2350
18.5 – j7.85
18.1 + j8.23
2400
13.5 – j2.90
14.2 + j4.26
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
7.80 – j12.4
13.8
50.3
108
54.2
–29
7.39 – j12.6
14.0
50.5
111
55.4
–31
7.22 – j12.8
14.1
50.5
112
56.0
–31
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2300
17.3 – j13.1
19.5 + j12.5
8.19 – j13.6
11.6
51.2
132
56.5
–35
2350
18.5 – j7.85
17.9 + j5.56
7.94 – j13.6
11.8
51.2
132
57.1
–38
2400
13.5 – j2.90
12.7 + j2.79
7.79 – j14.0
11.9
51.2
132
56.6
–38
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 10. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, VGSB = 0.7 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2300
17.3 – j13.1
17.3 + j16.6
15.9 – j5.99
14.8
49.0
79
66.1
–33
2350
18.5 – j7.85
19.2 + j10.7
13.2 – j4.39
15.1
48.7
75
67.8
–36
2400
13.5 – j2.90
16.0 + j5.29
10.3 – j4.95
15.1
48.7
75
68.5
–38
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
15.1 – j10.9
12.5
50.3
108
65.9
–38
18.9 + j6.52
14.0 – j8.10
12.9
50.0
100
67.4
–42
14.0 + j3.01
11.5 – j6.61
13.0
49.7
94
68.0
–45
f
(MHz)
Zsource
()
Zin
()
2300
17.3 – j13.1
19.7 + j13.6
2350
18.5 – j7.85
2400
13.5 – j2.90
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T23H160--24SR3
8
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL CARRIER LOAD PULL CONTOURS — 2350 MHz
44
44.5
IMAGINARY ()
0
5
45
0
E
–5
46
–10
46.5
–15
P
46
–25
5
10
60
–15
15
20
25
–25
58
30
56
P
54
52
5
10
15
50
20
25
30
REAL ()
REAL ()
Figure 8. P1dB Load Pull Output Power Contours (dBm)
Figure 9. P1dB Load Pull Efficiency Contours (%)
5
5
22.5
22
0
21.5
E
–5
21
20.5
–10
20
–15
P
19.5
–20
–25
5
10
15
20
–28
–20
E
–5
–18
–16
–10
–14
–15
P
–20
19
18.5
–26
–24 –22
0
IMAGINARY ()
IMAGINARY ()
62
64
–10
–20
47.5
46.5
54
E
–5
47
48
47
–20
56
45.5
IMAGINARY ()
5
–12
25
30
–25
5
10
15
20
25
REAL ()
REAL ()
Figure 10. P1dB Load Pull Gain Contours (dB)
Figure 11. P1dB Load Pull AM/PM Contours ()
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
30
Gain
Drain Efficiency
Linearity
Output Power
A2T23H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
9
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 2350 MHz
5
5
45
46
IMAGINARY ()
IMAGINARY ()
0
46.5
E
–5
47
–10
48
47.5
–15
P
E
–5
64
66
62
60
–15
58
56
P
–20
47
5
47.5
10
15
20
25
–25
30
56
–10
48.5
–20
–25
58
45.5
0
52
50
5
10
54
15
20
25
30
REAL ()
REAL ()
Figure 12. P3dB Load Pull Output Power Contours (dBm)
Figure 13. P3dB Load Pull Efficiency Contours (%)
5
5
20
19
18.5
–10
18
–15
P
–20
–25
5
10
15
20
–24
–22
E
–5
–20
–10
–18
–15
–16
–20
17
16.5
–26
P
17.5
16
–30
–28
19.5
E
–5
–32
0
IMAGINARY ()
IMAGINARY ()
0
25
30
–25
5
10
15
20
25
REAL ()
REAL ()
Figure 14. P3dB Load Pull Gain Contours (dB)
Figure 15. P3dB Load Pull AM/PM Contours ()
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
30
Gain
Drain Efficiency
Linearity
Output Power
A2T23H160--24SR3
10
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL PEAKING LOAD PULL CONTOURS — 2350 MHz
5
5
47.5
0
48
E
–5
IMAGINARY ()
IMAGINARY ()
47
46.5
0
48.5
–10
P
–15
49.5
50
–20
–25
10
5
15
66
64
62
–10
60
58
P
56
–15
54
52
–20
49
48.5
E
–5
20
25
–25
30
10
5
15
20
25
30
REAL ()
Figure 16. P1dB Load Pull Output Power Contours (dBm)
Figure 17. P1dB Load Pull Efficiency Contours (%)
5
5
0
0
E
–5
IMAGINARY ()
IMAGINARY ()
REAL ()
15
–10
14.5
P
14
–15
–25
12
11 11.5
5
12.5
–40
–36
–38
–34
E
–5
–32
–10
P
–15
–30
13.5
–20
–44 –42
–20
13
10
15
20
25
30
–25
5
10
15
20
25
REAL ()
REAL ()
Figure 18. P1dB Load Pull Gain Contours (dB)
Figure 19. P1dB Load Pull AM/PM Contours ()
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
30
Gain
Drain Efficiency
Linearity
Output Power
A2T23H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
11
P3dB – TYPICAL PEAKING LOAD PULL CONTOURS — 2350 MHz
5
5
47
47.5
48
0
0
–5
50.5
–20
49.5
50
P
–15
–25
49
E
–10
IMAGINARY ()
IMAGINARY ()
48.5
51
–5
62
66
E
–10
64
60
P
–15
56
58
54
52
–20
10
5
15
20
25
–25
30
10
5
15
20
25
30
REAL ()
REAL ()
Figure 20. P3dB Load Pull Output Power Contours (dBm)
Figure 21. P3dB Load Pull Efficiency Contours (%)
5
5
0
0
–46
–48
–5
E
–10
12.5
P
–15
12
11.5
–20
–25
IMAGINARY ()
IMAGINARY ()
13
9 9.5 10
5
10.5
–42
–40
E
–10
–38
P
–15
–36
–20
11
10
–44
–5
–34
15
20
25
30
–25
5
10
15
20
25
REAL ()
REAL ()
Figure 22. P3dB Load Pull Gain Contours (dB)
Figure 23. P3dB Load Pull AM/PM Contours ()
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
30
Gain
Drain Efficiency
Linearity
Output Power
A2T23H160--24SR3
12
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2T23H160--24SR3
RF Device Data
Freescale Semiconductor, Inc.
13
A2T23H160--24SR3
14
RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
 AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
 EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
 Electromigration MTTF Calculator
 RF High Power Model
 s2p File
Development Tools
 Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.freescale.com/rf
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
Nov. 2015
Description
 Initial Release of Data Sheet
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RF Device Data
Freescale Semiconductor, Inc.
15
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A2T23H160--24SR3
Document Number: A2T23H160--24S
Rev. 0, 11/2015
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RF Device Data
Freescale Semiconductor, Inc.