Data Sheet

Freescale Semiconductor
Technical Data
Document Number: A2T21H100--25S
Rev. 0, 6/2015
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 18 W asymmetrical Doherty RF power LDMOS transistor is designed for
cellular base station applications covering the frequency range of 2110 to
2170 MHz.
A2T21H100--25SR3
2100 MHz
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 250 mA, VGSB = 0.2 Vdc, Pout = 18 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
2110 MHz
17.3
52.1
8.2
–32.4
2140 MHz
17.4
51.0
8.0
–33.1
2170 MHz
17.4
50.5
8.0
–35.0
2110–2170 MHz, 18 W AVG., 28 V
AIRFAST RF POWER LDMOS
TRANSISTOR
ACPR
(dBc)
Features
 Advanced High Performance In--Package Doherty
 Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
 Designed for Digital Predistortion Error Correction Systems
NI--780S--4L4S
8 VBWA(1)
N.C.
1
RFinA/VGSA
2
7 RFoutA/VDSA
RFinB/VGSB
3
6 RFoutB/VDSB
4 Peaking
5 VBWB(1)
N.C.
Carrier
(Top View)
Figure 1. Pin Connections
1. Device cannot operate with the VDD current
supplied through pin 5 and pin 8.
 Freescale Semiconductor, Inc., 2015. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
A2T21H100--25SR3
1
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain--Source Voltage
Rating
VDSS
–0.5, +65
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
Case Operating Temperature Range
TC
–40 to +150
C
TJ
–40 to +225
C
CW
193
2.9
W
W/C
Operating Junction Temperature Range
(1,2)
CW Operation @ TC = 25C
Derate above 25C
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 72C, 18 W Avg., W--CDMA, 28 Vdc, IDQA = 250 mA, VGSB = 0.2 Vdc,
2140 MHz
Symbol
Value (2,3)
Unit
RJC
0.76
C/W
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
2
Machine Model (per EIA/JESD22--A115)
B
Charge Device Model (per JESD22--C101)
III
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 40 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Gate Quiescent Voltage
(VDD = 28 Vdc, IDA = 250 mAdc, Measured in Functional Test)
VGSA(Q)
1.5
1.8
2.3
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 0.4 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 60 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 0.6 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Characteristic
Off Characteristics
(4)
On Characteristics -- Side A, Carrier
On Characteristics -- Side B, Peaking
1.
2.
3.
4.
Continuous use at maximum temperature will affect MTTF.
MTTF calculator available at http://www.freescale.com/rf/calculators.
Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf and search for AN1955.
Each side of device measured separately.
(continued)
A2T21H100--25SR3
2
RF Device Data
Freescale Semiconductor, Inc.
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests (1,2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 250 mA, VGSB = 0.2 Vdc, Pout = 18 W Avg.,
f = 2170 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in
3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
16.5
17.4
19.5
dB
Drain Efficiency
D
47.3
50.5
—
%
PAR
7.3
8.0
—
dB
ACPR
—
–35.0
–29.8
dBc
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Load Mismatch (2) (In Freescale Doherty Test Fixture, 50 ohm system) IDQA = 250 mA, VGSB = 0.2 Vdc, f = 2140 MHz, 12 sec(on),
12% Duty Cycle
VSWR 10:1 at 32 Vdc, 126 W Pulsed CW Output Power
(3 dB Input Overdrive from 78 W Pulsed CW Rated Power)
No Device Degradation
Typical Performance (2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 250 mA, VGSB = 0.2 Vdc,
2110–2170 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
75
—
W
(3)
P3dB
—
112
—
W
AM/PM
(Maximum value measured at the P3dB compression point across
the 2110–2170 MHz frequency range)

—
–21.9
—

VBWres
—
120
—
MHz
Gain Flatness in 60 MHz Bandwidth @ Pout = 18 W Avg.
GF
—
0.17
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.01
—
dB/C
P1dB
—
0.006
—
dB/C
Pout @ 3 dB Compression Point
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30C to +85C) (4)
Table 5. Ordering Information
Device
A2T21H100--25SR3
Tape and Reel Information
R3 Suffix = 250 Units, 44 mm Tape Width, 13--inch Reel
Package
NI--780S--4L4S
1. Part internally matched both on input and output.
2. Measurements made with device in an asymmetrical Doherty configuration.
3. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
4. Exceeds recommended operating conditions. See CW operation data in Maximum Ratings table.
A2T21H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
3
VGGA
VDDA
C9
R2
A2T21H100--25S
Rev. 1
C1
C10
C11
R3
C12
C3
C4
Z1
R1
C5
C6
C7
CUT OUT AREA
C2
C13
C
P
C14
C15
D60961
R4
C16
C8
C18
C17
R5
C19
VGGB
VDDB
Figure 2. A2T21H100--25SR3 Test Circuit Component Layout
Table 6. A2T21H100--25SR3 Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1, C8, C10, C11, C16, C18
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C2, C4, C5, C7, C12, C13,
C14, C17
10 pF Chip Capacitors
ATC600F100JT250XT
ATC
C3, C6, C15
0.5 pF Chip Capacitors
ATC600F0R5BT250XT
ATC
C9, C19
220 F, 50 V Electrolytic Capacitors
227CKS050M
Illinois Capacitor
R1
50 , 10 W Chip Resistor
C10A50Z4
Anaren
R2, R5
10 K, 1/4 W Chip Resistors
CRCW120610K0JNEA
Vishay
R3, R4
5.6 , 1/4 W Chip Resistors
CRCW12065R60FKEA
Vishay
Z1
2000–2300 MHz Band, 90, 5 dB Directional Coupler
X3C21P1-05S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D60961
MTL
A2T21H100--25SR3
4
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS — 2110–2170 MHz
17.6
52
D
17.5
50
Gps
17.4
17.3
17.2
–28
–1.4
–30
–1.6
–32
PARC
–34
17.1
Input Signal PAR = 9.9 dB @
0.01% Probability on CCDF
17
16.9
2060
2080
2100
2120
2140
–36
ACPR
2160
2180
2200
–38
2220
–1.8
–2
–2.2
PARC (dB)
Gps, POWER GAIN (dB)
17.7
ACPR (dBc)
17.8
D, DRAIN
EFFICIENCY (%)
58
VDD = 28 Vdc, Pout = 18 W (Avg.), IDQA = 250 mA, VGSB = 0.2 Vdc
56
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
54
17.9
–2.4
f, FREQUENCY (MHz)
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 18 Watts Avg.
0
VDD = 28 Vdc, Pout = 11 W (PEP), IDQA = 250 mA
VGSB = 0.2 Vdc, Two--Tone Measurements
(f1 + f2)/2 = Center Frequency of 2140 MHz
IM3--L
–15
–30
IM3--U
IM5--L
–45
IM7--U
–60
IM7--L
IM5--U
–75
–90
1
100
10
300
TWO--TONE SPACING (MHz)
17.4
0
17.2
17
16.8
16.6
16.4
–1 dB = 13 W
VDD = 28 Vdc, IDQA = 250 mA, VGSB = 0.2 Vdc
f = 2140 MHz, Single--Carrier W--CDMA, 3.84
MHz Channel Bandwidth
–1
ACPR
–2
–26
60
–28
55
50
–3 dB = 25.6 W
D
–3
–2 dB = 19 W
–4
–5
65
Gps
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
10
15
20
45
–30
–32
ACPR (dBc)
1
D DRAIN EFFICIENCY (%)
17.6
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
–34
40
–36
35
40
–38
PARC
25
30
35
Pout, OUTPUT POWER (WATTS)
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T21H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS — 2110–2170 MHz
2170 MHz
14
2110 MHz
2140 MHz
2170 MHz
12
Gps
30
15
0
–10
–20
–30
–40
ACPR (dBc)
90
VDD = 28 Vdc, IDQA = 250 mA, VGSB = 0.2 Vdc, Single--Carrier
W--CDMA, 3.84 MHz Channel Bandwidth, Input Signal
20 PAR = 9.9 dB @ 0.01% Probability on CCDF
2110 MHz 75
2140 MHz
2170 MHz
18
60
2110 MHz
2140 MHz
ACPR
16
45
D, DRAIN EFFICIENCY (%)
Gps, POWER GAIN (dB)
22
–50
D
10
1
10
100
0
200
–60
Pout, OUTPUT POWER (WATTS) AVG.
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
18
17
Gain
GAIN (dB)
16
15
14
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 250 mA
VGSB = 0.2 Vdc
13
12
1850
1950
2050
2150
2250
2350
2450
f, FREQUENCY (MHz)
Figure 7. Broadband Frequency Response
A2T21H100--25SR3
6
RF Device Data
Freescale Semiconductor, Inc.
Table 7. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 237 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
16.2 – j20.6
14.5 + j19.4
13.0 – j11.6
19.9
46.6
45
57.2
–15
2140
22.6 – j22.0
18.4 + j19.4
11.3 – j8.94
19.7
46.6
46
57.7
–16
2170
30.0 – j15.0
25.1 + j17.0
12.1 – j10.2
19.6
46.7
47
58.1
–15
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
16.2 – j20.6
16.6 + j21.3
12.8 – j12.8
17.7
47.4
55
58.3
–21
2140
22.6 – j22.0
22.3 + j20.9
12.2 – j11.4
17.5
47.4
55
58.5
–22
2170
30.0 – j15.0
30.4 + j16.9
12.7 – j12.3
17.4
47.5
56
58.8
–20
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 8. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, IDQA = 237 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
15.5 + j2.97
22.7
44.8
30
68.7
–28
16.6 + j23.8
13.6 + j2.89
22.4
44.8
30
68.6
–30
24.7 + j23.1
13.3 + j1.92
22.2
45.0
31
68.8
–27
f
(MHz)
Zsource
()
Zin
()
2110
16.2 – j20.6
11.6 + j22.0
2140
22.6 – j22.0
2170
30.0 – j15.0
Zload
()
(1)
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload
()
(2)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
16.2 – j20.6
13.0 + j23.6
14.4 + j1.73
20.3
45.6
36
69.0
–37
2140
22.6 – j22.0
18.9 + j25.5
12.6 + j1.63
20.1
45.5
36
68.7
–39
2170
30.0 – j15.0
29.3 + j24.0
13.3 + j0.91
20.0
45.7
37
69.0
–35
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T21H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
7
Table 9. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 0.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
9.12 – j16.9
10.8 + j19.0
6.94 – j11.9
14.2
48.6
72
61.8
–31
2140
12.3 – j17.6
15.2 + j19.5
7.25 – j12.4
14.1
48.5
70
60.8
–32
2170
17.3 – j16.3
21.2 + j18.5
7.13 – j12.8
14.0
48.4
70
60.3
–31
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
9.12 – j16.9
12.8 + j20.5
7.33 – j13.3
12.2
49.2
83
62.3
–38
2140
12.3 – j17.6
18.7 + j20.4
7.57 – j13.9
12.0
49.1
82
61.1
–39
2170
17.3 – j16.3
26.4 + j17.2
7.78 – j15.1
11.9
49.1
81
60.0
–38
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 10. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, VGSB = 0.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
13.9 – j3.44
15.6
46.2
42
73.9
–40
11.4 + j21.4
13.0 – j3.73
15.5
46.3
42
73.1
–40
16.4 + j23.3
12.0 – j1.88
15.2
45.7
37
72.8
–43
f
(MHz)
Zsource
()
Zin
()
2110
9.12 – j16.9
7.84 + j19.6
2140
12.3 – j17.6
2170
17.3 – j16.3
Zload
()
(1)
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload
()
(2)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
9.12 – j16.9
9.75 + j21.2
12.6 – j3.97
13.6
46.9
49
74.0
–54
2140
12.3 – j17.6
15.7 + j22.5
12.1 – j6.94
13.4
47.6
57
72.9
–49
2170
17.3 – j16.3
23.6 + j22.1
11.2 – j6.81
13.2
47.5
57
72.7
–50
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T21H100--25SR3
8
RF Device Data
Freescale Semiconductor, Inc.
P1dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 2140 MHz
10
10
5
5
E
E
--5
P
--10
44
42.5
46.5
--15
43
--20
45
0
5
62
P
--10
60
64
66
--5
58
56
--15
46
43.5 44.5
--25
--5
54
52
--20
45.5
10
15
20
--25
--5
30
25
0
5
10
15
20
30
25
REAL ()
REAL ()
Figure 8. P1dB Load Pull Output Power Contours (dBm)
Figure 9. P1dB Load Pull Efficiency Contours (%)
10
10
23
5
E
22.5
IMAGINARY ()
22
21.5
P
21
20.5
--15
19.5
--20
0
5
10
15
–22
–20
--5
–18
P
--10
–16
--15
20
--20
19
--25
--5
E
0
--5
--10
–26
–30
–24
–28
5
0
IMAGINARY ()
68
0
IMAGINARY ()
IMAGINARY ()
0
20
30
25
--25
--5
–14
0
REAL ()
5
10
15
20
25
30
REAL ()
Figure 10. P1dB Load Pull Gain Contours (dB)
NOTE:
Figure 11. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T21H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
9
P3dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 2140 MHz
10
10
5
5
E
--5
--10
43.5
--15
P
45
--25
--5
46
47
44.5 45.5
0
66
--5
5
64
62
60
--10
P
58
--15
44
--20
68
E
0
IMAGINARY ()
IMAGINARY ()
0
56
54
--20
46.5
10
15
20
--25
--5
30
25
0
5
10
20
15
52
30
25
REAL ()
REAL ()
Figure 12. P3dB Load Pull Output Power Contours (dBm)
Figure 13. P3dB Load Pull Efficiency Contours (%)
10
10
21
5
20
--5
19.5
--10
P
19
18.5
--15
17.5
--20
–28
–26
--5
–24
--10
P
–22
--15
18
–30
–32
–36
E
0
IMAGINARY ()
IMAGINARY ()
20.5
E
0
–34
5
–20
--20
17
--25
--5
0
5
10
15
20
30
25
--25
--5
0
REAL ()
5
10
15
20
25
30
REAL ()
Figure 14. P3dB Load Pull Gain Contours (dB)
NOTE:
Figure 15. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T21H100--25SR3
10
RF Device Data
Freescale Semiconductor, Inc.
P1dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 2140 MHz
5
5
44.5
0
45
45.5
E
--5
46.5
46
--10
P
47.5
48
--15
IMAGINARY ()
IMAGINARY ()
0
47
72
E
--5
68
70
64
66
--10
62
P
60
--15
58
--20
--20
--25
0
5
10
15
20
--25
30
25
0
5
10
15
20
25
30
REAL ()
REAL ()
Figure 16. P1dB Load Pull Output Power Contours (dBm)
Figure 17. P1dB Load Pull Efficiency Contours (%)
5
5
0
0
IMAGINARY ()
IMAGINARY ()
E
--5
--10
15
P
--15
11.5
12
--25
0
5
–36
–34
--10
P
–32
--15
14.5
13
--20
–38
E
--5
–40
–42
–44
13.5
12.5
--20
14
14
10
15
20
25
30
--25
–30
0
5
REAL ()
10
15
20
25
30
REAL ()
Figure 18. P1dB Load Pull Gain Contours (dB)
NOTE:
Figure 19. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T21H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
11
P3dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 2140 MHz
5
5
45
0
0
E
--15
48
48.5
P
46
46.5
--10
IMAGINARY ()
IMAGINARY ()
45.5
--5
47
47.5
49
--5
E
--10
66
62
64
P
--15
60
58
--20
--20
--25
--25
0
68
70
72
5
10
15
20
30
25
56
0
5
10
15
20
25
30
REAL ()
Figure 20. P3dB Load Pull Output Power Contours (dBm)
Figure 21. P3dB Load Pull Efficiency Contours (%)
5
5
0
0
--5
--5
IMAGINARY ()
IMAGINARY ()
REAL ()
E
--10
--15
9.5
--20
0
11.5
10.5
5
–50
E
10
–48
–46
–44
--10
–42
–40
P
--15
12.5
11
10
--25
13
P
–52
–38
--20
12
15
20
25
30
--25
–36
0
5
REAL ()
10
15
20
25
30
REAL ()
Figure 22. P3dB Load Pull Gain Contours (dB)
NOTE:
Figure 23. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T21H100--25SR3
12
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2T21H100--25SR3
RF Device Data
Freescale Semiconductor, Inc.
13
A2T21H100--25SR3
14
RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
 AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
 EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
 Electromigration MTTF Calculator
 RF High Power Model
 .s2p File
Development Tools
 Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.freescale.com/rf
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
June 2015
Description
 Initial Pre--release of Data Sheet
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RF Device Data
Freescale Semiconductor, Inc.
15
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A2T21H100--25SR3
Document Number: A2T21H100--25S
Rev. 0, 6/2015
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RF Device Data
Freescale Semiconductor, Inc.