P5506BVG N-Channel Logic Level Enhancement NIKO-SEM SOP-8 Lead-Free Mode Field Effect Transistor D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID 60 55mΩ 5.5A 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage VDS 60 V Gate-Source Voltage VGS ±20 V TC = 25 °C Continuous Drain Current TC = 70 °C Pulsed Drain Current 5.5 ID 1 4.5 IDM TC = 25 °C Power Dissipation 20 2.5 PD TC = 70 °C Junction & Storage Temperature Range A W 1.3 Tj, Tstg -55 to 150 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL Junction-to-Ambient TYPICAL MAXIMUM UNITS 50 °C / W RθJA 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% 2 ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN UNIT TYP MAX STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage V(BR)DSS VGS = 0V, ID = 250µA 60 VGS(th) VDS = VGS, ID = 250µA 1.0 IGSS 2.5 V VDS = 0V, VGS = ±20V ±100 nA VDS = 48V, VGS = 0V 1 10 Zero Gate Voltage Drain Current IDSS VDS = 40V, VGS = 0V, TJ = 55 °C On-State Drain Current1 ID(ON) VDS = 5V, VGS = 10V Drain-Source Resistance1 On-State Forward Transconductance1 1.5 20 A VGS = 4.5V, ID = 4.5A 55 75 RDS(ON) VGS = 10V, ID = 5.5A 42 55 gfs VDS = 10V, ID = 5.5A 14 1 µA mΩ S SEP-30-2004 N-Channel Logic Level Enhancement NIKO-SEM P5506BVG SOP-8 Lead-Free Mode Field Effect Transistor DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge 2 Qg Gate-Source Charge2 2 650 VGS = 0V, VDS = 25V, f = 1MHz pF 80 35 VDS = 0.5V(BR)DSS, VGS = 10V, Qgs ID = 5.5A 12.5 18 nC 2.4 Qgd 2.6 Turn-On Delay Time2 td(on) 11 20 2 tr VDD = 30V 8 18 Turn-Off Delay Time2 td(off) ID ≅ 1A, VGS = 10V, RGEN = 6Ω 19 35 6 15 Gate-Drain Charge Rise Time Fall Time 2 tf nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS 1.3 Pulsed Current3 ISM 2.6 A Forward Voltage1 VSD 1 V IF = IS A, VGS = 0V Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “P5506BVG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. 2 SEP-30-2004 P5506BVG N-Channel Logic Level Enhancement SOP-8 Lead-Free Mode Field Effect Transistor Body Diode Forward Voltage Variation with Source Current and Temperature 100 V GS = 0V 10 Is - Reverse Drain Current(A) NIKO-SEM T A = 125° C 1 25° C 0.1 -55° C 0.01 0.001 0.0001 0 3 0.6 0.2 0.4 0.8 VSD - Body Diode Forward Voltage(V) 1.0 1.2 SEP-30-2004 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor 4 P5506BVG SOP-8 Lead-Free SEP-30-2004 P5506BVG N-Channel Logic Level Enhancement NIKO-SEM SOP-8 Lead-Free Mode Field Effect Transistor SOIC-8(D) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. Max. A 4.8 4.9 5.0 B 3.8 3.9 C 5.8 D 0.38 E Min. Typ. Max. H 0.5 0.715 0.83 4.0 I 0.18 0.254 0.25 6.0 6.2 J 0.445 0.51 K 1.27 0.22 0° 4° 8° L F 1.35 1.55 1.75 M G 0.1 0.175 0.25 N J F D E I G B H K C A 5 SEP-30-2004