NIKO-SEM P8006EVG P-Channel Logic Level Enhancement SOP-8 Lead-Free Mode Field Effect Transistor D PRODUCT SUMMARY V(BR)DSS RDS(ON) ID -55V 80mΩ -4.5A 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS Drain-Source Voltage VDS -55 V Gate-Source Voltage VGS ±20 V TC = 25 °C Continuous Drain Current TC = 70 °C Pulsed Drain Current -4.5 ID 1 -3.5 IDM TC = 25 °C Power Dissipation 2.5 PD TC = 70 °C Operating Junction & Storage Temperature Range 1 Lead Temperature ( /16” from case for 10 sec.) A -20 W 1.3 Tj, Tstg -55 to 150 TL 275 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL Junction-to-Ambient RθJA TYPICAL MAXIMUM UNITS 50 °C / W 1 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% 2 ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNIT MIN TYP MAX STATIC Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA -55 VGS(th) VDS = VGS, ID = -250µA -1 Gate-Body Leakage IGSS VDS = 0V, VGS = ±20V Zero Gate Voltage Drain Current IDSS Gate Threshold Voltage On-State Drain Current1 ID(ON) Drain-Source On-State Resistance1 RDS(ON) Forward Transconductance1 gfs V -1.5 -2.5 ±250 nA VDS = -44V, VGS = 0V 1 VDS = -36V, VGS = 0V, TJ = 125 °C 10 VDS = -5V, VGS = -10V -20 µA A VGS = -4.5V, ID = -3.5A 90 150 VGS = -10V, ID = -4.5A 60 80 VDS = -10V, ID = -4.5A 9 mΩ S SEP-30-2004 1 NIKO-SEM P8006EVG P-Channel Logic Level Enhancement SOP-8 Lead-Free Mode Field Effect Transistor DYNAMIC Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 40 Total Gate Charge2 Qg 15 2 760 VGS = 0V, VDS = -30V, f = 1MHz Qgs VDS = 0.5V(BR)DSS, VGS = -10V, 2.5 Gate-Drain Charge2 Qgd ID = -4.5A 3.0 Turn-On Delay Time2 td(on) 2 tr Turn-Off Delay Time2 td(off) Gate-Source Charge Rise Time Fall Time2 pF 90 nC 7 14 VDS = -20V, 10 20 ID ≅ -1A, VGS = -10V, RGS = 6Ω 19 34 12 22 tf nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS -1.3 Pulsed Current ISM -2.6 Forward Voltage1 VSD IF = IS, VGS = 0V Reverse Recovery Time trr IF = -3.5 A, dlF/dt = 100A / µS Reverse Recovery Charge Qrr 3 -1 A V 15.5 nS 7.9 nC Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. 1 2 REMARK: THE PRODUCT MARKED WITH “P8006EVG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. SEP-30-2004 2 NIKO-SEM P8006EVG P-Channel Logic Level Enhancement SOP-8 Lead-Free Mode Field Effect Transistor TYPICAL PERFORMANCE CHARACTERISTICS Body Diode Forward Voltage Variation with Source Current and Temperature 100 V GS = 0V -Is - Reverse Drain Current(A) 10 1 T A = 125° C 0.1 25° C -55° C 0.01 0.001 0 0.2 0.6 0.8 1.0 0.4 -VSD - Body Diode Forward Voltage(V) 1.2 1.4 SEP-30-2004 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P8006EVG SOP-8 Lead-Free SEP-30-2004 4 NIKO-SEM P8006EVG P-Channel Logic Level Enhancement SOP-8 Lead-Free Mode Field Effect Transistor SOIC-8(D) MECHANICAL DATA mm mm Dimension Dimension Min. Typ. Max. A 4.8 4.9 5.0 B 3.8 3.9 C 5.8 D 0.38 E Min. Typ. Max. H 0.5 0.715 0.83 4.0 I 0.18 0.254 0.25 6.0 6.2 J 0.445 0.51 K 1.27 0.22 0° 4° 8° L F 1.35 1.55 1.75 M G 0.1 0.175 0.25 N SEP-30-2004 5