NTHC5513 D

NTHC5513
Power MOSFET
20 V, +3.9 A / −3.0 A,
Complementary ChipFET
Features
•
•
•
•
•
•
•
Complementary N−Channel and P−Channel MOSFET
Small Size, 40% Smaller than TSOP−6 Package
Leadless SMD Package Featuring Complementary Pair
ChipFET Package Provides Great Thermal Characteristics Similar to
Larger Packages
Low RDS(on) in a ChipFET Package for High Efficiency Performance
Low Profile (< 1.10 mm) Allows Placement in Extremely Thin
Environments Such as Portable Electronics
Pb−Free Package is Available
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V(BR)DSS
RDS(on) TYP
N−Channel
20 V
60 m @ 4.5 V
P−Channel
−20 V
130 m @ −4.5 V
3.9 A
80 m @ 2.5 V
−3.0 A
200 m @ −2.5 V
S2
D1
Applications
•
•
•
•
ID MAX
Load Switch Applications Requiring Level Shift
DC−DC Conversion Circuits
Drive Small Brushless DC Motors
Designed for Power Management Applications in Portable, Battery
Powered Products
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Value
Unit
Drain−to−Source Voltage
VDSS
20
V
Gate−to−Source Voltage
VGS
±12
V
ID
2.9
A
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
ChipFET
CASE 1206A
STYLE 2
N−Ch
Steady
State
TA = 25°C
TA = 85°C
2.1
t5
TA = 25°C
3.9
P−Ch
Steady
State
TA = 25°C
TA = 85°C
−1.6
D1
8
1
S1
1
8
t5
TA = 25°C
−3.0
D1
7
2
G1
2
7
N−Ch
t = 10 s
D2
6
3
S2
3
P−Ch
t = 10 s
D2
5
4
G2
4
Steady
State
TA = 25°C
t5
TA = 25°C
Operating Junction and Storage
Temperature
Lead Temperature for Soldering Purposes
(1/8” from case for 10 seconds)
ID
IDM
PIN
CONNECTIONS
A
12
−9.0
PD
 Semiconductor Components Industries, LLC, 2004
MARKING
DIAGRAM
A
−2.2
6
5
W
1.1
C1 = Specific Device Code
M = Month Code
2.1
TJ,
TSTG
−55 to
150
°C
TL
260
°C
ORDERING INFORMATION
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
October, 2004 − Rev. 4
P−Channel MOSFET
C1 M
Pulsed Drain Current
(Note 1)
D2
S1
N−Channel MOSFET
Symbol
Parameter
G2
G1
1
Package
Shipping†
NTHC5513T1
ChipFET
3000/Tape & Reel
NTHC5513T1G
ChipFET
(Pb−Free)
3000/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTHC5513/D
NTHC5513
THERMAL RESISTANCE RATINGS
Parameter
Junction−to−Ambient (Note 1)
Steady State
TA = 25°C
t5
Symbol
Max
Unit
RJA
110
°C/W
60
2. Surface Mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
N/P
V((BR)DSS
)
N
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS (Note 3)
Drain−to−Source Breakdown Voltage
VGS = 0 V
P
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
ID = 250 A
20
ID = −250 A
−20
V
A
N
VGS = 0 V, VDS = 16 V
1.0
P
VGS = 0 V, VDS = −16 V
−1.0
N
VGS = 0 V, VDS = 16 V, TJ = 85 °C
5
P
VGS = 0 V, VDS = −16 V, TJ = 85 °C
−5
VDS = 0 V, VGS = ±12 V
±100
nA
V
IGSS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
VGS(TH)
( )
N
VGS = VDS
P
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
gFS
ID = 250 A
0.6
1.2
ID = −250 A
−0.6
−1.2
N
VGS = 4.5 V , ID = 2.9 A
0.058
0.080
P
VGS = −4.5 V , ID = −2.2 A
0.130
0.155
N
VGS = 2.5 V , ID = 2.3 A
0.077
0.115
P
VGS = −2.5 V, ID = −1.7 A
0.200
0.240
N
VDS = 10 V, ID = 2.9A
6.0
P
VDS = −10 V , ID = −2.2 A
6.0
S
CHARGES AND CAPACITANCES
Input Capacitance
Output Capacitance
CISS
COSS
N
VDS = 10 V
180
P
VDS = −10 V
185
VDS = 10 V
80
VDS = −10 V
95
N
VDS = 10 V
25
P
VDS = −10 V
30
N
P
Reverse Transfer Capacitance
Total Gate Charge
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
CRSS
QG(TOT)
(
)
QGS
QGD
f = 1 MHz
MHz, VGS = 0 V
pF
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
2.6
4.0
P
VGS = −4.5 V, VDS = −10 V, ID = −2.2 A
3.0
6.0
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
0.6
P
VGS = −4.5 V, VDS = −10 V, ID = −2.2 A
0.5
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
0.7
P
VGS = −4.5 V, VDS = −10 V, ID = −2.2 A
0.9
3. Pulse Test: Pulse Width 250 s, Duty Cycle 2%.
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2
nC
NTHC5513
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
N/P
Test Conditions
Min
Typ
Max
Unit
5.0
10
ns
9.0
18
10
20
tf
3.0
6.0
td(ON)
7.0
12
13
25
33
50
27
40
IS = 2.6 A
0.8
1.15
IS = −2.1 A
−0.8
−1.15
N
IS = 1.5 A
12.5
P
IS = −1.5 A
32
N
IS = 1.5 A
9.0
IS = −1.5 A
10
IS = 1.5 A
3.5
P
IS = −1.5 A
22
N
IS = 1.5 A
6.0
P
IS = −1.5 A
15
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
td(ON)
tr
td(OFF)
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
N
tr
td(OFF)
Fall Time
P
VDD = 16 V, VGS = 4.5 V, ID = 2.9 A,
RG = 2.5 VDD = −16 V, VGS = −4.5 V, ID = −2.2 A,
RG = 2.5 tf
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage (Note 5)
VSD
N
VGS = 0 V
P
Reverse Recovery Time (Note 4)
Charge Time
tRR
ta
P
Discharge Time
Reverse Recovery Charge
tb
QRR
N
VGS = 0 V,
dIS / dt = 100 A/s
4. Switching characteristics are independent of operating junction temperatures.
5. Pulse Test: Pulse Width 250 s, Duty Cycle 2%.
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3
V
ns
nC
NTHC5513
TYPICAL N−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
8
VGS = 5 V to 3 V
VGS = 2.4 V
2V
2.2 V
6
4
1.8 V
2
1.6 V
1.4 V
4
2
TC = −55°C
100°C
0
1
2
3
4
5
6
7
8
9
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
0.5
1
1.5
2
2.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
6
25°C
0
0.15
ID = 2.7 A
TJ = 25°C
0.1
0.05
0
2
4
1
3
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
6
3
0.1
TJ = 25°C
VGS = 2.5 V
0.07
VGS = 4.5 V
0.04
3
1
5
7
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.7
100
ID = 2.7 A
VGS = 4.5 V
VGS = 0 V
1.5
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
VDS ≥ 10 V
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
8
1.3
1.1
TJ = 100°C
10
0.9
0.7
−50
1
−25
0
25
50
75
100
125
150
2
4
6
8
10
12
14
16
18
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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20
NTHC5513
TYPICAL N−CHANNEL PERFORMANCE CURVES
C, CAPACITANCE (pF)
CISS
VDS = 0 V
VGS = 0 V
TJ = 25°C
5
300
20
QG
4.5
4
16
3.5
CRSS
3
12
2.5
200
2
8
QGD
QGS
1.5
100
COSS
1
ID = 2.7 A
TJ = 25°C
0.5
0
10
5
VGS
0
VDS
5
10
15
20
0
0
0.5
1.5
2
2.5
0
3
QG, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
7
100
IS, SOURCE CURRENT (AMPS)
VDD = 16 V
ID = 2.7 A
VGS = 4.5 V
t, TIME (ns)
1
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
400
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
(TJ = 25°C unless otherwise noted)
tr
10
td(OFF
)
td(ON)
tf
1
1
10
VGS = 0 V
TJ = 25°C
6
5
4
3
2
1
0
0.3
100
0.45
0.6
0.75
0.9
1.05
RG, GATE RESISTANCE (OHMS)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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1.2
NTHC5513
TYPICAL P−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
VGS = −6 V to −3 V
VGS = −2.4 V
−2.2 V
4
TJ = 25°C
−2 V
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
4
3
−1.8 V
2
−1.6 V
1
−1.4 V
VDS ≥ −10 V
3
2
TC = −55°C
1
25°C
100°C
−1.2 V
0
2
1
4
3
5
7
6
0
0.5
8
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
1.5
2
2.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. On−Region Characteristics
Figure 12. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0
0.5
ID = −2.1 A
TJ = 25°C
0.4
0.3
0.2
0.1
0
1
6
2
4
3
5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.25
TJ = 25°C
0.225
VGS = −2.5 V
0.2
0.175
0.15
VGS = −4.5 V
0.125
0.1
0.5
1.5
2.5
3.5
−ID, DRAIN CURRENT (AMPS)
Figure 14. On−Resistance vs. Drain Current
and Gate Voltage
Figure 13. On−Resistance vs. Gate−to−Source
Voltage
1.6
10000
ID = −2.1 A
VGS = −4.5 V
VGS = 0 V
1.4
−IDSS, LEAKAGE (A)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
3
1.2
1
TJ = 150°C
1000
TJ = 100°C
100
0.8
0.6
−50
10
−25
0
25
50
75
100
125
150
2
4
6
8
10
12
14
16
18
20
−TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 15. On−Resistance Variation with
Temperature
Figure 16. Drain−to−Source Leakage Current
vs. Voltage
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NTHC5513
TYPICAL P−CHANNEL PERFORMANCE CURVES
VDS = 0 V
TJ = 25°C
CISS
500
C, CAPACITANCE (pF)
VGS = 0 V
−VGS, GATE−TO−SOURCE VOLTAGE (V)
600
400
CRSS
300
200
COSS
100
0
10
5
−VGS
0
−VDS
5
10
15
20
5
15
QT
−VDS
4
−VGS
12
3
9
QGS
QGD
2
6
1
3
ID = −2.1 A
TJ = 25°C
0
0
0
1
2
3
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
(TJ = 25°C unless otherwise noted)
4
QG, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 18. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 17. Capacitance Variation
1000
−IS, SOURCE CURRENT (AMPS)
2.5
t, TIME (ns)
100
td(OFF)
tf
tr
10
td(ON)
1
1
VDD = −16 V
ID = −2.1 A
VGS = −4.5 V
10
100
VGS = 0 V
TJ = 25°C
2
1.5
1
0.5
0
0.3
0.5
0.7
0.9
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
RG, GATE RESISTANCE (OHMS)
Figure 19. Resistive Switching Time Variation
vs. Gate Resistance
Figure 20. Diode Forward Voltage vs. Current
TYPICAL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
Notes:
PDM
0.2
t1
0.1
t2
0.1
t1
1. Duty Cycle, D = t
2
2. Per Unit Base = RthJA = 90°C/W
3. TJM − TA = PDMZJA(t)
4. Surface Mounted
0.05
0.02
0.01
10−4
Single Pulse
10−3
10−2
10 −1
1
Square Wave Pulse Duration (sec)
Figure 21. Thermal Response
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7
10
100
600
NTHC5513
SOLDERING FOOTPRINT*
2.032
0.08
2.032
0.08
0.457
0.018
0.635
0.025
1.092
0.043
0.635
0.025
0.178
0.007
0.457
0.018
0.711
0.028
0.66
0.026
0.254
0.010
0.66
0.026
Figure 23. Style 2
Figure 22. Basic
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
lead−frame) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
The basic pad layout with dimensions is shown in
Figure 22. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in
Figure 23 improves the thermal area of the drain
connections (pins 5, 6, 7, 8) while remaining within the
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8
NTHC5513
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
A
8
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
M
6
K
5
S
5
6
7
8
4
3
2
1
B
1
2
3
L
4
D
J
G
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
C
0.05 (0.002)
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SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
DIM
A
B
C
D
G
J
K
L
M
S
MILLIMETERS
MIN
MAX
2.95
3.10
1.55
1.70
1.00
1.10
0.25
0.35
0.65 BSC
0.10
0.20
0.28
0.42
0.55 BSC
5 ° NOM
1.80
2.00
INCHES
MIN
MAX
0.116
0.122
0.061
0.067
0.039
0.043
0.010
0.014
0.025 BSC
0.004
0.008
0.011
0.017
0.022 BSC
5 ° NOM
0.072
0.080
NTHC5513
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NTHC5513/D