NTHS5441T1 Power MOSFET P-Channel ChipFET 3.9 Amps, 20 Volts Features • • • • http://onsemi.com Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature ChipFET Surface Mount Package 3.9 AMPS 20 VOLTS RDS(on) = 55 m Applications • Power Management in Portable and Battery–Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards S G MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol 5 secs Steady State Unit Drain–Source Voltage VDS –20 V Gate–Source Voltage VGS 12 V Continuous Drain Current (TJ = 150°C) (Note 1.) TA = 25°C TA = 85°C ID IS Maximum Power Dissipation (Note 1.) TA = 25°C TA = 85°C PD Operating Junction and Storage Temperature Range –2.1 A –1.1 A ChipFET CASE 1206A STYLE 1 W 2.5 1.3 TJ, Tstg 3.9 2.8 20 IDM Continuous Source Current (Note 1.) P–Channel MOSFET A 5.3 3.8 Pulsed Drain Current D 1.3 0.7 °C –55 to +150 MARKING DIAGRAM PIN CONNECTIONS 1. Surface Mounted on 1″ x 1″ FR4 Board. 8 1 D 1 8 D 7 2 D 2 7 D 6 3 D 3 6 S 5 4 G 4 5 A3 D A3 = Specific Device Code ORDERING INFORMATION Semiconductor Components Industries, LLC, 2001 May, 2001 – Rev. 2 1 Device Package Shipping NTHS5441T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHS5441T1/D NTHS5441T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction–to–Ambient (Note 2.) t 5 sec Steady State RthJA Maximum Junction–to–Foot (Drain) Steady State RthJF Typ Max 40 80 50 95 15 20 Unit °C/W °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = –250 µA –0.6 – 1.2 V Gate–Body Leakage IGSS VDS = 0 V, VGS = 12 V – – 100 nA Zero Gate Voltage Drain Current IDSS VDS = –16 V, VGS = 0 V – – –1.0 µA VDS = –16 V, VGS = 0 V, TJ = 85°C – – –5.0 ID(on) VDS –5.0 V, VGS = –4.5 V –20 – – A rDS(on) VGS = –3.6 V, ID = –3.7 A VGS = –4.5 V, ID = –3.9 A – – 0.050 0.046 0.06 0.055 Ω Static Gate Threshold Voltage On–State Drain Current (Note 3.) Drain–Source On–State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) VGS = –2.5 V, ID = –3.1 A – 0.070 0.083 gfs VDS = –10 V, ID = –3.9 A – 12 – mhos VSD IS = –1.1 A, VGS = 0 V – –0.8 –1.2 V – 11 22 nC – 3.0 – – 2.5 – – 710 – – 400 – – 140 – – 14 30 – 22 55 – 42 100 – 35 70 – 30 60 Dynamic (Note 4.) Total Gate Charge Qg Gate–Source Charge Qgs Gate–Drain Charge Qgd Input Capacitance Ciss VDS = –10 10 V V, VGS = –4.5 45V V, ID = –3.9 A Output Capacitance Coss Reverse Transfer Capacitance Crss Turn–On Delay Time td(on) Rise Time Turn–Off Delay Time tr td(off) Fall Time tf Source–Drain Reverse Recovery Time trr VDS = –5.0 5 0 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz VDD = –10 V, RL = 10 Ω ID –1.0 –1 0 A, A VGEN = –4 –4.5 5V V, RG = 6 Ω IF = –1.1 A, di/dt = 100 A/µs 2. Surface Mounted on 1″ x 1″ FR4 Board. 3. Pulse Test: Pulse Width 300 µs, Duty Cycle 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 pF ns NTHS5441T1 TYPICAL ELECTRICAL CHARACTERISTICS 3.5 V TJ = 25°C 16 4.5 V 4V 2.5 V 12 8 2V 4 TJ = –55°C 16 25°C 125°C 12 8 4 VGS = 1.5 V 0 0 0 0.5 1 1.5 2 2.5 3 0 1.5 2 2.5 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics 0.2 ID = –3.9 A TJ = 25°C 0.15 0.1 0.05 0 0 1 0.5 –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 1 3 2 4 5 TJ = 25°C 0.15 VGS = 2.5 V 0.1 VGS = 3.6 V 0.05 VGS = 4.5 V 0 2 6 10 14 18 –ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Gate–to–Source Voltage Figure 4. On–Resistance versus Drain Current and Gate Voltage 1.6 ID = –3.9 A VGS = –4.5 V 1.4 1.2 1 0.8 0.6 –50 –25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) Figure 5. On–Resistance Variation with Temperature http://onsemi.com 3 3 0.2 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) 20 3V –ID, DRAIN CURRENT (AMPS) 5V RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) –ID, DRAIN CURRENT (AMPS) 20 150 20 NTHS5441T1 1500 TJ = 25°C VGS = 0 C, CAPACITANCE (pF) 1200 900 Ciss 600 Coss 300 Crss 0 0 4 8 12 20 16 –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE Figure 6. Capacitance Variation 5 25 QT 4 20 VGS 15 3 Q1 Q2 10 2 ID = –3.9 A TJ = 25°C 1 VDS 5 0 0 0 2 4 6 8 10 Qg, TOTAL GATE CHARGE (nC) –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) TYPICAL ELECTRICAL CHARACTERISTICS Figure 7. Gate–to–Source and Drain–to–Source Voltage versus Total Charge 1 Duty Cycle = 0.5 0.2 0.1 0.1 PDM 0.05 t1 0.02 t2 DUTY CYCLE, D = t1/t2 PER UNIT BASE = RθJA = 80°C/W TJM - TA = PDMZθJA(t) SURFACE MOUNTED Single Pulse 0.01 0.001 0.01 0.1 1 10 SQUARE WAVE PULSE DURATION (sec) Figure 8. Normalized Thermal Transient Impedance, Junction–to–Ambient 5 –IS, SOURCE CURRENT (AMPS) 0.0001 4 VGS = 0 V TJ = 25°C 3 2 1 0 0.1 0.3 0.5 0.7 0.9 –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 9. Diode Forward Voltage versus Current http://onsemi.com 4 100 1000 NTHS5441T1 PACKAGE DIMENSIONS ChipFET CASE 1206A–03 ISSUE C A 8 7 M 6 K 5 S 5 6 7 8 4 3 2 1 B 1 2 3 L 4 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 7. 1206A-01 AND 1206A-02 OBSOLETE. NEW STANDARD IS 1206A-03. J G DIM A B C D G J K L M S C 0.05 (0.002) MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.20 0.28 0.42 0.55 BSC 5 ° NOM 1.80 2.00 STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. http://onsemi.com 5 DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.011 0.017 0.022 BSC 5 ° NOM 0.072 0.080 NTHS5441T1 80 mm 80 mm 18 mm 25 mm 68 mm 28 mm 28 mm 26 mm 26 mm Figure 1. Figure 2. BASIC PAD PATTERNS the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 1. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 2 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the confines of http://onsemi.com 6 NTHS5441T1 Notes http://onsemi.com 7 NTHS5441T1 ChipFET is a trademark of Vishay Siliconix ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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