ONSEMI NTHD4P02F

NTHD4P02F
Power MOSFET and
Schottky Diode
−20 V, −3.0 A, Single P−Channel with
3.0 A Schottky Barrier Diode, ChipFET
Features
• Leadless SMD Package Featuring a MOSFET and Schottky Diode
• 40% Smaller than TSOP−6 Package with Similar Thermal
•
•
•
Characteristics
Independent Pinout to each Device to Ease Circuit Design
Ultra Low VF Schottky
Pb−Free Package is Available
MOSFET
ID MAX
RDS(on) TYP
V(BR)DSS
−130 m @ −4.5 V
−20 V
−3.0 A
200 m @ −2.5 V
SCHOTTKY DIODE
Applications
•
•
•
•
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Li−Ion Battery Charging
High Side DC−DC Conversion Circuits
High Side Drive for Small Brushless DC Motors
Power Management in Portable, Battery Powered Products
VR MAX
VF TYP
IF MAX
20 V
0.510 V
3.0 A
A
S
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Value
Units
Drain−to−Source Voltage
VDSS
−20
V
Gate−to−Source Voltage
VGS
±12
V
ID
−2.2
A
Continuous Drain
Current
Steady
State
TJ = 25°C
t5s
TJ = 25°C
Pulsed Drain
Current
TJ = 85°C
ID
−3.0
A
IDM
−9.0
A
PD
1.1
W
Steady
State
TJ = 25°C
TJ = 85°C
0.6
t5s
TJ = 25°C
2.1
Continuous Source Current (Body Diode)
−2.1
A
TJ, TSTG
−55 to 150
°C
TL
260
°C
Parameter
Peak Repetitive Reverse Voltage
DC Blocking Voltage
2
7
 Semiconductor Components Industries, LLC, 2004
S
4
Symbol
Value
Unit
VRRM
20
V
VR
20
V
IF
2.2
A
TJ = 25°C
25 C
t5s
C
1
8
C
2
7
D
3
D
4
6
G
3.0
A
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
October, 2004 − Rev. 4
8
MARKING
DIAGRAM
6
3
(TJ = 25°C unless otherwise noted)
Steady
State
1
A
A
SCHOTTKY DIODE MAXIMUM RATINGS
Average Rectified
Forward Current
ChipFET
CASE 1206A
STYLE 3
PIN
CONNECTIONS
IS
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
SCHOTTKY DIODE
C3 M
Operating Junction and Storage
Temperature
C
D
P−Channel MOSFET
−1.6
tp = 10 s
Power Dissipation
G
1
5
5
C2 = Specific Device Code
M = Month Code
ORDERING INFORMATION
Device
Package
Shipping†
NTHD4P02FT1
ChipFET
3000/Tape & Reel
NTHD4P02FT1G
ChipFET
(Pb−free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTHD4P02F/D
NTHD4P02F
THERMAL RESISTANCE RATINGS
Parameter
Junction−to−Ambient (Note
(
1))
Steady State
t5s
Symbol
Max
Units
RJA
110
°C/W
TJ = 25°C
60
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces).
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
Typ
V(BR)DSS
VGS = 0 V, ID = −250 A
−20
−23
IDSS
VDS = −16 V, VGS = 0 V, TJ = 25°C
Max
Units
−1.0
A
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage
g Drain Current
V
VDS = −16 V, VGS = 0 V, TJ = 85°C
−5.0
IGSS
VDS = 0 V, VGS = ±12 V
±100
nA
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = −250 A
−0.75
−1.2
V
Drain−to−Source On− Resistance
RDS(on)
VGS = −4.5, ID = −2.2 A
0.130
0.155
VGS = −2.5, ID = −1.7 A
0.200
0.240
VDS = −10 V, ID = −1.7 A
5.0
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 2)
Forward Transconductance
gFS
−0.6
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
pF
185
300
95
150
CRSS
30
50
Total Gate Charge
QG(TOT)
3.0
6.0
nC
Threshold Gate Charge
QG(TH)
0.2
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
0.9
td(ON)
7.0
12
ns
tr
13
25
33
50
27
40
−0.85
−1.15
V f = 1.0
1 0 MHz,
MH
VGS = 0 V,
VDS = −10 V
VGS = −4.5 V, VDS = −10 V,
ID = −2.2 A
0.5
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(OFF)
VGS = −4.5 V, VDD = −16 V,
ID = −2.2 A, RG = 2.5 tf
DRAIN−SOURCE DIODE CHARACTERISTICS (Note 2)
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = −2.1 A
V
ns
32
10
VGS = 0 V, IS = −2.1 A ,
dIS/dt = 100 A/s
22
QRR
15
nC
SCHOTTKY DIODE ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Maximum Instantaneous Forward Voltage
g
VF
IF = 0.1 A
0.425
IF = 0.5 A
0.480
IF = 1.0 A
0.510
Maximum Instantaneous Reverse Current
IR
Typ
Max
0.575
1.0
VR = 20 V
5.0
dv/dt
VR = 20 V
Non−Repetitive Peak Surge Current
IFSM
Halfwave, Single Pulse, 60 Hz
2. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
3. Switching characteristics are independent of operating junction temperatures.
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Units
V
VR = 10 V
Maximum Voltage Rate of Change
2
Min
10,000
A
V/ns
23
A
NTHD4P02F
TYPICAL MOSFET PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
VGS = −6 V to −3 V
VGS = −2.4 V
−2.2 V
4
TJ = 25°C
−2 V
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
4
3
−1.8 V
2
−1.6 V
1
−1.4 V
VDS ≥ −10 V
3
2
TC = −55°C
1
25°C
100°C
−1.2 V
0
1
2
4
3
5
7
6
0
0.5
8
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
1.5
2
2.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0
0.5
ID = −2.1 A
TJ = 25°C
0.4
0.3
0.2
0.1
0
1
6
2
4
3
5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.25
TJ = 25°C
0.225
VGS = −2.5 V
0.2
0.175
0.15
VGS = −4.5 V
0.125
0.1
0.5
1.5
2.5
3.5
−ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.6
10000
ID = −2.1 A
VGS = −4.5 V
VGS = 0 V
1.4
−IDSS, LEAKAGE (A)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
3
1.2
1
TJ = 150°C
1000
TJ = 100°C
100
0.8
0.6
−50
10
−25
0
25
50
75
100
125
150
2
4
6
8
10
12
14
16
18
−TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
20
NTHD4P02F
600
VDS = 0 V
TJ = 25°C
CISS
500
C, CAPACITANCE (pF)
VGS = 0 V
400
CRSS
300
200
COSS
100
0
5
10
−VGS
0
−VDS
5
15
10
5
15
QT
−VGS
−VDS
4
12
3
9
QGD
QGS
2
6
1
0
20
0
1
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
2
3
4
0
QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
2.5
−IS, SOURCE CURRENT (AMPS)
VDD = −16 V
ID = −2.1 A
VGS = −4.5 V
100
t, TIME (ns)
3
ID = −2.1 A
TJ = 25°C
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL MOSFET PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
td(OFF)
tf
tr
10
td(ON)
1
1
10
100
VGS = 0 V
TJ = 25°C
2
1.5
1
0.5
0
0.3
0.5
0.9
0.7
RG, GATE RESISTANCE ()
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
0.1
D = 0.5
0.2
0.1
Normalized to ja at 10s.
0.05
Chip
0.02
0.0175 0.0710 0.2706 0.5776 0.7086 0.0154 F
0.0854 F
0.3074 F
1.7891 F
107.55 F
0.01
SINGLE PULSE
0.01
1.0E−03
1.0E−02
1.0E−01
1.0E+00
t, TIME (s)
Figure 11. Thermal Response
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4
1.0E+01
1.0E+02
Ambient
1.0E+03
NTHD4P02F
TYPICAL SCHOTTKY PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
10
IF, INSTANTANEOUS FORWARD
CURRENT (AMPS)
IF, INSTANTANEOUS FORWARD
CURRENT (AMPS)
10
TJ = 150°C
1
TJ = 25°C
TJ = −55°C
0.1
0.20
0.40
0.60
TJ = 150°C
1
TJ = 25°C
0.1
0.20
0.80
VF, INSTANTANEOUS FORWARD VOLTAGE (VOLTS)
IR, MAXIMUM REVERSE CURRENT (AMPS)
IR, REVERSE CURRENT (AMPS)
0.80
Figure 13. Maximum Forward Voltage
TJ = 150°C
100E−6
TJ = 100°C
10E+0
TJ = 150°C
1E+0
TJ = 100°C
100E−3
10E−6
1E−6
100E−9
TJ = 25°C
10E−3
1E−3
TJ = 25°C
100E−6
10E−9
20
10
VR, REVERSE VOLTAGE (VOLTS)
0
PFO, AVERAGE POWER DISSIPATION (WATTS)
freq = 20 kHz
dc
2.5
square wave
2
Ipk/Io = 1.5
Ipk/Io = 5
1
Ipk/Io = 10
Ipk/Io = 20
0.5
0
25
45
65
85
105
125
20
Figure 15. Maximum Reverse Current
3.5
3
10
VR, REVERSE VOLTAGE (VOLTS)
0
Figure 14. Typical Reverse Current
IO, AVERAGE FORWARD CURRENT (AMPS)
0.60
VF, MAXIMUM INSTANTANEOUS FORWARD
VOLTAGE (VOLTS)
Figure 12. Typical Forward Voltage
1E−3
0.40
145
165
TL, LEAD TEMPERATURE (°C)
1.8
1.6
1.4
square wave
dc
Ipk/Io = 1.2
1
Ipk/Io = 5
0.8
Ipk/Io = 10
0.6
Ipk/Io = 20
0.4
0.2
0
0
Figure 16. Current Derating
0.5
1
1.5
2
2.5
3
IO, AVERAGE FORWARD CURRENT (AMPS)
Figure 17. Forward Power Dissipation
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5
3.5
NTHD4P02F
2.032
0.08
2.032
0.08
0.457
0.018
0.711
0.028
0.635
0.025
1.092
0.043
0.178
0.007
0.457
0.018
0.711
0.028
0.66
0.026
SCALE 20:1
mm inches
0.66
0.026
0.254
0.010
SCALE 20:1
mm inches
Figure 19. Style 3
Figure 18. Basic
BASIC PAD PATTERNS
of the basic footprint. The drain copper area is 0.0019 sq.
in. (or 1.22 sq. mm). This will assist the power dissipation
path away from the device (through the copper lead−frame)
and into the board and exterior chassis (if applicable) for
the single device. The addition of a further copper area
and/or the addition of vias to other board layers will
enhance the performance still further.
The basic pad layout with dimensions is shown in
Figure 18. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 19 improves the thermal area of the drain
connections (pins 5, 6) while remaining within the confines
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6
NTHD4P02F
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
A
8
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
M
6
K
5
S
5
6
7
8
4
3
2
1
B
1
2
3
L
4
D
J
G
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
C
0.05 (0.002)
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7
A
A
S
G
D
D
C
C
DIM
A
B
C
D
G
J
K
L
M
S
MILLIMETERS
MIN
MAX
2.95
3.10
1.55
1.70
1.00
1.10
0.25
0.35
0.65 BSC
0.10
0.20
0.28
0.42
0.55 BSC
5 ° NOM
2.00
1.80
INCHES
MIN
MAX
0.116
0.122
0.061
0.067
0.039
0.043
0.010
0.014
0.025 BSC
0.004
0.008
0.011
0.017
0.022 BSC
5 ° NOM
0.072
0.080
NTHD4P02F
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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For additional information, please contact your
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NTHD4P02F/D