PTFA180701E PTFA180701F Thermally-Enhanced High Power RF LDMOS FETs 70 W, 1805 – 1880 MHz Description The PTFA180701E and PTFA180701F are 70-watt LDMOS FETs designed for GSM and GSM EDGE power amplifier applications in the 1805 MHz to 1880 MHz band. Features include input and output matching, and thermallyenhanced packages with slotted or earless flanges. Manufactured with Infineon's advanced LDMOS process, these devices provide excellent thermal performance and superior reliability. PTFA180701E Package H-36265-2 PTFA180701F Package H-37265-2 Features EDGE EVM Performance VDD = 28 V, IDQ = 550 mA, ƒ = 1836.6 MHz 50 5 Efficiency 3 30 2 20 10 1 EVM 0 0 30 32 34 36 38 40 42 Thermally-enhanced packages, Pb-free and RoHS-compliant • Broadband internal matching • Typical EDGE performance - Average output power = 44 dBm - Gain = 16.5 dB - Efficiency = 40.5% - EVM = 2.0% • Typical CW performance - Output power at P–1dB = 72 W - Gain = 15.5 dB - Efficiency = 59% • Integrated ESD protection: Human Body Model, Class 2 (minimum) • Excellent thermal stability, low HCI drift • Capable of handling 10:1 VSWR @ 28 V, 70 W (CW) output power 40 Drain Efficiency (%) EVM RMS (avg. %) . 4 • 44 46 Output Power, avg. (dBm) RF Characteristics EDGE Measurements (not subject to production test—verified by design/characterization in Infineon test fixture) VDD = 28 V, IDQ = 550 mA, POUT = 44 dBm, ƒ = 1836.6 MHz Characteristic Symbol Min Typ Max Unit EVM RMS — 2.0 — % @ 400 kHz ACPR — –62 — dBc @ 600 kHz ACPR — –76 — dBc Gain Gps — 16.5 — dB Drain Efficiency ηD — 40.5 — % Error Vector Magnitude Modulation Spectrum All published data at TCASE = 25°C unless otherwise indicated *See Infineon distributor for future availability. ESD: Electrostatic discharge sensitive device—observe handling precautions! Data Sheet 1 of 11 Rev. 03.1, 2009-02-20 PTFA180701E PTFA180701F RF Characteristics (cont.) Two-tone Measurements (tested in Infineon test fixture) VDD = 28 V, IDQ = 550 mA, POUT = 60 W PEP, ƒ = 1840 MHz, tone spacing = 1 MHz Characteristic Symbol Min Typ Max Unit Gain Gps 15.5 16.5 — dB Drain Efficiency ηD 44 45 — % Intermodulation Distortion IMD — –30 –29 dBc DC Characteristics Characteristic Conditions Symbol Min Typ Max Unit Drain-Source Breakdown Voltage VGS = 0 V, IDS = 10 mA V(BR)DSS 65 — — V Drain Leakage Current VDS = 28 V, V GS = 0 V IDSS — — 1.0 µA VDS = 63 V, V GS = 0 V IDSS — — 10.0 µA On-State Resistance VGS = 10 V, V DS = 0.1 V RDS(on) — 0.125 — Ω Operating Gate Voltage VDS = 28 V, ID = 550 mA VGS 2.0 2.5 3.0 V Gate Leakage Current VGS = 10 V, V DS = 0 V IGSS — — 1.0 µA Maximum Ratings Parameter Symbol Value Unit Drain-Source Voltage VDSS 65 V Gate-Source Voltage VGS –0.5 to +12 V Junction Temperature TJ 200 °C Total Device Dissipation PD 201 W 1.15 W/°C Above 25°C derate by Storage Temperature Range TSTG –40 to +150 °C Thermal Resistance (TCASE = 70°C, 70 W CW) RθJC 0.87 °C/W Ordering Information Type and Version Package Type Package Description Marking PTFA180701E V4 H-36265-2 Thermally-enhanced slotted flange, single-ended PTFA180701E PTFA180701E V4 H-37265-2 Thermally-enhanced earless flange, single-ended PTFA180701F *See Infineon distributor for future availability. Data Sheet 2 of 11 Rev. 03.1, 2009-02-20 PTFA180701E PTFA180701F Typical Performance (measurements taken in production test fixture) Edge EVM and Modulation Spectrum vs. Quiescent Current Three-Carrier CDMA2000 Performance VDD = 28 V, IDQ = 550 mA, ƒ = 1840 MHz 2.4 -20 2.2 -30 EVM -40 1.8 400 kHz -50 1.6 -60 1.4 -70 1.2 600 kHz 1.0 0.40 0.50 -80 50 -45 40 -50 ACP Up 30 20 -65 -70 0 30 34 36 38 40 42 44 46 Intermodulation Distortion vs. Output Power VDD = 28 V, IDQ = 550 mA, ƒ = 1840 MHz, tone spacing = 1 MHz VDD = 28 V, IDQ = 550 mA, ƒ = 1836.6 MHz -40 50 Efficiency 40 400 kHz 30 -70 20 600 kHz 10 -25 70 -30 60 3rd Order -35 IMD (dBc) -50 Drain Efficiency (%) Modulation Spectrum (dBc) 32 Output Power, Avg. (dBm) EDGE Modulation Spectrum Performance -80 -60 Efficiency Quiescent Current (A) -60 -55 ALT Up 10 -90 0.70 0.60 -40 ACP Low -40 50 40 5th 7th -45 30 -50 20 -55 -90 32 34 36 38 40 42 44 -60 46 0 30 Output Power (dBm) Data Sheet 10 Efficiency 0 30 Efficiency (%) 2.0 60 Adj. Ch. Power Ratio (dBc) -10 Drain Efficiency (%) 2.6 Modulation Spectrum (dBc) EVM RMS (avg. %) . VDD = 28 V, ƒ = 1836.6 MHz, POUT = 44 dBm 35 40 45 50 Output Power, PEP (dBm) 3 of 11 Rev. 03.1, 2009-02-20 PTFA180701E PTFA180701F Typical Performance (cont.) Broadband Test Fixture Performance (P–1dB) CW Broadband Performance VDD = 28 V, IDQ = 550mA VDD = 28 V, IDQ = 550 mA, POUT = 43 dBm 70 17 50 Output Power 16 40 15 Gain 14 1760 1800 1840 30 Gain 45 40 10 0 35 -10 30 Return Loss -20 -30 20 1760 1780 1800 1820 1840 1860 1880 1900 1920 Frequency (MHz) Frequency (MHz) IM3 vs. Output Power at Selected Biases Power Sweep VDD = 28 V, ƒ1 = 1849, ƒ2 = 1840 MHz VDD = 28 V, ƒ = 1880 MHz 18.0 -20 -25 Power Gain (dB) -35 IDQ = 825 mA -40 -45 -50 IDQ = 825 mA 17.5 IDQ = 275 mA -30 IMD (dBc) 20 Efficiency 25 20 1920 1880 30 50 Efficiency (%) 60 Output Power (dBm) & Efficiency (%) Gain (dB) 18 40 55 Drain Efficiency Gain, Return Loss (dB) 19 IDQ = 550 mA 17.0 16.5 IDQ = 550 mA 16.0 15.5 15.0 -55 IDQ = 275 mA 14.5 -60 26 30 34 38 42 35 46 39 41 43 45 47 49 Output Power (dBm) Output Power, Avg. (dBm) Data Sheet 37 4 of 11 Rev. 03.1, 2009-02-20 PTFA180701E PTFA180701F Typical Performance (cont.) Gain & Efficiency vs. Output Power Output Power (P–1dB) vs. Drain Voltage VDD = 28 V, IDQ = 550 mA, ƒ = 1880 MHz 19 58 Efficiency 52 Gain 17 46 40 16 34 15 28 14 22 13 16 12 10 0 10 20 30 40 50 60 70 50 Output Power (dBm) 64 Drain Efficiency (%) 20 18 Gain (dB) IDQ = 550 mA, ƒ = 1880 MHz 49 48 47 46 24 80 26 Voltage normalized to typical gate voltage, series show current Drain Efficiency (%) 35 30 -30 1.03 0.15 A -35 1.02 0.44 A 1.01 0.73 A -40 ACP ƒ C – 0.75 MHz -45 25 -50 20 -55 15 -60 10 ACPR ƒ C + 1.98 MHz 5 0 -65 -70 Normalized Bias Voltage (V) Efficiency Adj. Ch. Power Ratio (dBc) TCASE = 25°C 40 -75 30 32 34 36 38 40 42 44 1.10 A 1.00 2.20 A 0.99 3.30 A 0.98 4.41 A 0.97 5.51 A 0.96 0.95 -20 46 0 20 40 60 80 100 Case Temperature (°C) Output Power, Avg. (dBm) Data Sheet 32 Bias Voltage vs. Temperature IS-95 CDMA Performance VDD = 28 V, IDQ = 550 mA, ƒ = 1840 MHz TCASE = 90°C 30 Drain Voltage (V) Output Power (W) 45 28 5 of 11 Rev. 03.1, 2009-02-20 PTFA180701E PTFA180701F Broadband Circuit Impedance 0 .1 Z0 = 50 Ω D G Z Load 0.3 0.2 1920 MHz 0.1 Z Load 0.0 Z Source 1760 MHz S 0.1 MHz R jX R jX 1760 7.9 –10.3 4.6 –1.4 1800 7.4 –10.0 4.5 –1.1 1840 7.0 –9.7 4.5 –0.8 1880 6.5 –9.3 4.4 –0.3 1920 6.1 –8.9 4.3 –0.1 Z Source VEL Z Load Ω 1920 MHz WA <--- Z Source Ω Frequency 1760 MHz 0. 2 See next page for circuit information Data Sheet 6 of 11 Rev. 03.1, 2009-02-20 PTFA180701E PTFA180701F Reference Circuit C1 0.001µF R2 1.3KV R1 1.2KV QQ1 LM7805 VDD Q1 BCP56 C2 0.001µF C3 0.001µF R4 2K V R5 10 V C4 10µF 35V R6 1K V C5 R7 0.1µF 1KV C6 0.01µF C7 10pF R8 10 V l1 C10 1µF C11 100µF 50V l12 l6 C8 10pF RF_IN C9 10pF l7 l10 C13 10pF DUT l2 l3 l4 l5 l8 l9 l13 l11 l 14 C12 1.2pF RF_OUT l15 a 18 070 1 e f _ s ch R3 2K V Reference circuit schematic for 1840 MHz Circuit Assembly Information DUT PTFA180701E or PTFA180701F PCB 0.76 mm [.030"], εr = 3.48 Microstrip l1 l2 l3 l4 l5 l6 l7 l8 l9 l10, l11 l12 l13 l14 l15 LDMOS Transistor Rogers, RO4350 Electrical Characteristics at 1840 MHz1 Dimensions: L x W ( mm) 0.034 λ, 50.0 3.33 x 1.70 0.149 λ, 50.0 14.68 x 1.70 0.014 λ, 10.2 1.27 x 13.28 0.044 λ, 7.1 3.86 x 19.61 0.014 λ, 7.1 1.27 x 19.61 0.012 λ, 78.0 1.22 x 0.74 0.115 λ, 65.0 11.51 x 1.07 0.016 λ, 8.9 1.37 x 15.34 0.090 λ, 8.9 8.13 x 15.34 0.020 λ, 21.8 1.91 x 5.36 0.162 λ, 64.0 16.18 x 1.12 0.042 λ, 50.0 4.11 x 1.70 0.074 λ, 50.0 7.29 x 1.70 0.032 λ, 50.0 3.12 x 1.70 1 oz. copper Dimensions: L x W (in.) 0.131 x 0.067 0.578 x 0.067 0.050 x 0.523 0.152 x 0.772 0.050 x 0.772 0.048 x 0.029 0.453 x 0.042 0.054 x 0.604 0.320 x 0.604 0.075 x 0.211 0.637 x 0.044 0.162 x 0.067 0.287 x 0.067 0.123 x 0.067 1Electrical characteristics are rounded Data Sheet 7 of 11 Rev. 03.1, 2009-02-20 PTFA180701E PTFA180701F Reference Circuit (cont.) R5 C5 QQ1 R4 C4 R6 LM R3 R1 R7 R2 VDD C1 C3 C2 C10 Q1 C11 C9 C6 R8 C7 RF_IN RF_OUT C12 C8 C13 A180701_01 RO4350 a180701ef _assy Reference circuit assembly diagram* (not to scale) Component C1, C2, C3 C4 C5 C6 C7, C9 C8, C13 C10 C11 C12 Q1 QQ1 R1 R2 R3 R4 R5, R8 R6, R7 Description Capacitor, 0.001 µF Tantalum capacitor, 10 µF, 35 V Capacitor, 0.1 µF Capacitor, 0.01 µF Ceramic capacitor, 10 pF Ceramic capacitor, 10 pF Ceramic capacitor, 1 µF Electrolytic capacitor, 100 µF, 50 V Ceramic capacitor, 1.2 pF Transistor Voltage regulator Chip resistor 1.2 k-ohms Chip resistor 1.3 k-ohms Chip resistor 2 k-ohms Potentiometer 2 k-ohms Chip resistor 10 ohms Chip resistor 1 k-ohms Suggested Manufacturer Digi-Key Digi-Key Digi-Key ATC ATC ATC Digi-Key Digi-Key ATC Infineon Technologies National Semiconductor Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key P/N or Comment PCC1772CT-ND 399-1655-2-ND PCC104BCT-ND 200B 103 100B 100 100A 100 445-1411-1-ND PCE3718CT-ND 100B 1R2 BCP56 LM7805 P1.2KGCT-ND P1.3KGCT-ND P2KECT-ND 3224W-202ETR-ND P10ECT-ND P1KECT-ND *Gerber files for this circuit available on request. Data Sheet 8 of 11 Rev. 03.1, 2009-02-20 PTFA180701E PTFA180701F Package Outline Specifications Package H-36265-2 2X 7.11 [.280] (45° X 2.03 [.080]) CL D 2.59±0.51 [.102±.020] S C L FLANGE 9.78 [.385] 15.34±0.51 [.604±.020] LID 10.16±0.25 [.400±.010] G 2x 7.11 [.280] 2X R1.60 [R.063] 4X R1.52 [R.060] 15.23 [.600] 10.16±0.25 [.400±.010] SPH 1.57 [.062] 3.56±0.38 [.140±.015 0.0381 [.0015] -A- 20.31 [.800] 2 0 0 7 1 - 1 1 - 6 _ h 3 - 6 + 3 7 2 6 5 _ P O s v. s d _ h 3 - 6 2 6 5 2 - 1.02 [.040] Diagram Notes—unless otherwise specified: 1. Lead thickness: 0.10 +0.051/–0.025 [.004 +.002/–.001]. 2. All tolerances ± 0.127 [.005] unless specified otherwise. 3. Pins: D = drain, S = source, G = gate. 4. Interpret dimensions and tolerances per ASME Y14.5M-1994. 5. Primary dimensions are mm. Alternate dimensions are inches. 6. Gold plating thickness: S, D, G - flange & leads: 1.14 ± 0.38 micron [45 ± 15 microinch] Find the latest and most complete information about products and packaging at the Infineon Internet page http://www.infineon.com/products Data Sheet 9 of 11 Rev. 03.1, 2009-02-20 PTFA180701E PTFA180701F Package Outline Specifications (cont.) Package H-37265-2 (45° X 2.03 [.080]) CL 2.59±0.51 [.102±.020] D LID 10.16±0.25 [.400±.010] FLANGE 10.16 [.400] CL 15.34±.51 [.604±.020] 10.16 [.400] G 2X 7.11 [.280] FLANGE 4X R0.63 [R.025] MAX LID 10.16±0.25 [.400±.010] SPH 1.57 [.062] | 0.025 [.001]| -A3.56±.38 [.140±.015] S 10.16 [.400] 1.02 [.040] 0 7 1 1 1 9 _ h - 3 6 + 3 7 2 6 5 _ P O s _ h - 3 7 2 6 5 - 2 Diagram Notes—unless otherwise specified: 1. Lead thickness: 0.10 +0.051/–0.025 [.004 +.002/–.001]. 2. All tolerances ± 0.127 [.005] unless specified otherwise. 3. Pins: D = drain, S = source, G = gate. 4. Interpret dimensions and tolerances per ASME Y14.5M-1994. 5. Primary dimensions are mm. Alternate dimensions are inches. 6. Gold plating thickness: S, D, G - flange & leads: 1.14 ± 0.38 micron [45 ± 15 microinch] Find the latest and most complete information about products and packaging at the Infineon Internet page http://www.infineon.com/products Data Sheet 10 of 11 Rev. 03.1, 2009-02-20 PTF180701E/F Confidential, Limited Internal Distribution Revision History: 2009-02-20 Previous Version: 2006-08-10, Data Sheet Data Sheet Page Subjects (major changes since last revision) 1, 3, 9, 10 Update to product V4, with new package technologies. Update package outline diagrams. 8 Fixed typing error We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] To request other information, contact us at: +1 877 465 3667 (1-877-GO-LDMOS) USA or +1 408 776 0600 International GOLDMOS® is a registered trademark of Infineon Technologies AG. Edition 2009-02-20 Published by Infineon Technologies AG 81726 Munich, Germany © 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com/rfpower). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet 11 of 11 Rev. 03.1, 2009-02-20