INFINEON TUA6024-2

Wireless Components
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier
TUA6024-2 Version 2.0
Specification July 2001
Confidential
Revision History: Current Version: Preliminary Datasheet, V 1.1, August 2000
Previous Version:Target Data Sheet
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
all
all
version to 1.1, status to preliminary
5-2
5-2
Bus input/output SDA max changed to 6V,
Bus input SCL max changed to 6V,
ADC input added
5-3
5-3
new reference for ESD protection
5-5
5-5
Current consumption for LOW/MID band and HIGH band added,
tbf’s replaced by data
Charge Pump output voltage VCP = 1.3 V min
5 - 10
5 - 10
Table 5 - 4, Bit Allocation Read/Write in Status Byte A2, A1, A0 added
Revision History: Current Version: Datasheet, V 2.0, July 2001
Previous Version:Preliminary Datasheet V 1.1, August 2000
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
all
all
version to 2.0, preliminary deleted
5-2
5- 2
definition of thermal properties changed
5-5
5-5
current consumtion changed
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TUA6024-2
Product Info
Product Info
General Description
Features
The TUA6024-2 is a 5 V mixer/oscilla- Package
tor and synthesizer for TV and VCR
tuners.
General
■
Suitable for analog tuners and for
digital CATV tuners
■
Compatible with TUA6024-S and
TUA6024-K in normal mode
■
New features in extended mode
■
Full ESD protection
Mixer/Oscillator
■
High impedance mixer input for
LOW/MID band
■
Low impedance mixer input for
HIGH band
■
4 pin oscillator for LOW/MID band
■
4 pin oscillator for HIGH band
IF-Amplifier
Application
■
balanced SAW preamplifier
■
Low output impedance
■
PLL
■
PLL with short lock-in time
■
High voltage VCO tuning output
■
Fast I 2C bus
■
3 NPN bandswitch buffers
■
Internal LOW-MID/HIGH switch
■
Lock-in flag
■
Power-down reset
■
4 programmable reference divider
ratios: 24, 64, 80, 128
■
4 programmable charge pump currents
The IC is suitable for PAL tuners in TV- and VCR-sets or CATV set-top
receivers for analog TV and digital cable TV.
Ordering Information
Wireless Components
Type
Ordering Code
Package
TUA6024-2
Q67037--A1161 ( tape and reel)
P-TSSOP-28-1
Product Info
Specification, July 2001
1
Table of Contents
1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2
2.1
2.2
2.3
2.4
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3
3.1
3.2
3.3
3.4
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
4
4.1
4.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Evaluation board, low phase noise application . . . . . . . . . . . . . . . . . . 4-3
5
5.1
5.1.1
5.1.2
5.1.3
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-16
Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-16
Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-17
Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-18
Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.5
5.5.1
5.5.2
5.5.3
5.5.4
Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Input admittance (S11) of the LOW/MID band mixer input . . . . . . . . 5-19
Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-19
Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-20
Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-20
2
Product Description
Contents of this Chapter
2.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TUA6024-2
Product Description
2.1 General Description
The TUA6024-2 device combines a digitally programmable phase locked loop
(PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV and VCR tuners.
The PLL block with four selectable chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise
setting of the frequency of the tuner oscillator up to 1024 MHz in increments of
31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has three output ports. A flag is set when the
loop is locked. It can be read by the processor via the I2C bus.
The mixer-oscillator block includes two balanced mixers (one mixer with highimpedance input and one mixer with a balanced low-impedance input), two frequency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an
IF amplifier, a low-noise reference voltage source, and a band switch.
2.2 Features
General
■
Suitable for analog tuners and for digital CATV tuners
■
Compatible with TUA6024-S and TUA6024-K in normal mode
■
New features in extended mode
■
Full ESD protection
Mixer/Oscillator
■
High impedance mixer input for LOW/MID band
■
Low impedance mixer input for HIGH band
■
4 pin oscillator for LOW/MID band
■
4 pin oscillator for HIGH band
IF-Amplifier
■
balanced SAW preamplifier
■
Low output impedance
PLL
Wireless Components
■
PLL with short lock-in time
■
High voltage VCO tuning output
■
Fast I2C bus
■
3 NPN bandswitch buffers
■
Internal LOW-MID/HIGH switch
2-2
Specification, July 2001
TUA6024-2
Product Description
■
Lock-in flag
■
Power-down reset
■
4 programmable reference divider ratios: 24, 64, 80, 128
■
4 programmable charge pump currents
2.3 Application
■
The IC is suitable for PAL tuners in TV- and VCR-sets or CATV set-top
receivers for analog TV and digital cable TV.
2.4 Package Outlines
P-TSSOP-28-1
Wireless Components
2-3
Specification, July 2001
3
Functional Description
Contents of this Chapter
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4
3.4.1
3.4.2
3.4.3
3.4.4
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TUA6024-2
Functional Description
3.1 Pin Configuration
OSCHIGHIN
1
28
HIGHIN
OSCHIGHOUT
2
27
HIGHIN
OSCHIGHOUT
3
26
LOW/MIDIN
OSCHIGHIN
4
25
VCC
OSCLOW/MIDIN
5
24
MIXOUT
OSCLOW/MIDOUT
6
23
MIXOUT
OSCLOW/MIDOUT
7
22
PLLGND
OSCLOW/MIDIN
8
21
SDA
RFGND
TUA6024-2
9
20
SCL
ADC
10
19
AS
IFOUT
11
18
XTAL
IFOUT
12
17
PHIGH
VT
13
16
PMID
CP
14
15
PLOW
TUA6024-2_pin_config
Figure 3-1
Wireless Components
Pin Configuration
3-2
Specification, July 2001
TUA6024-2
Functional Description
3.2 Internal Pin Configuration
Table 3-1 Pin Definition and Function
Pin No.
Symbol
Equivalent I/O-Schematic
Average DC voltage
LOW/MID
HIGH
1
OSCHIGHIN
0.0 V
1.6 V
2
OSCHIGHOUT
0.0 V
2.8 V
3
OSCHIGHOUT
0.0 V
2.8 V
4
OSCHIGHIN
0.0 V
1.6 V
1.6 V
0.0 V
2.3 V
0.0 V
2.3 V
0.0 V
1.6 V
0.0 V
5
OSCLOW/
MIDIN
6
OSCLOW/
MIDOUT
7
OSCLOW/
MIDOUT
8
OSCLOW/
MIDIN
Wireless Components
2
3
1
4
6
7
5
8
3-3
Specification, July 2001
TUA6024-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
Symbol
9
RFGND
10
ADC
Equivalent I/O-Schematic
Average DC voltage
analog ground
LOW/MID
HIGH
0.0 V
0.0 V
VADC
VADC
2.3 V
2.3 V
2.3 V
2.3 V
VT
VT
2.1 V
2.1 V
10
11
IFOUT
11
12
IFOUT
13
VT
12
14
14
CP
13
Wireless Components
3-4
Specification, July 2001
TUA6024-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
15
Symbol
Equivalent I/O-Schematic
PLOW
16
PMID
17
PHIGH
18
XTAL
15
16
17
Average DC voltage
LOW/MID
HIGH
5 V or V CE
5V
5 V or V CE
5V
5V
V CE
3.0 V
3.0 V
VAS
VAS
n.a.
n.a.
18
19
AS
19
20
SCL
20
Wireless Components
3-5
Specification, July 2001
TUA6024-2
Functional Description
Table 3-1 Pin Definition and Function (continued)
Pin No.
21
Symbol
Equivalent I/O-Schematic
Average DC voltage
SDA
LOW/MID
HIGH
n.a.
n.a.
0.0 V
0.0 V
3.8 V
3.8 V
3.8 V
3.8 V
5.0 V
5.0 V
1.8 V
0.0 V
0.0 V
0.9 V
0.0 V
0.9 V
21
22
PLLGND
23
MIXOUT
digital ground
IF A m p.
23
24
24
MIXOUT
O scilla to r
25
VCC
26
LOW/MIDIN
supply voltage
26
27
HIGHIN
28
HIGHIN
Wireless Components
27
28
3-6
Specification, July 2001
TUA6024-2
Functional Description
HIGHIN
HIGHIN
LOW/MIDIN
VCC
MIXOUT
MIXOUT
PLLGND
SDA
SCL
AS
XTAL
PHIGH
PMID
PLOW
3.3 Block Diagram
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I2C Bus
LOW
or MID
RF Input
HIGH
HIGH
RF Input
LOW/MID
PORTS
FL
Lock
Detector
Crystal
Oscillator
LOW
or MID
Mixer
HIGH
HIGH
Mixer
LOW/MID
ADC
Reference
Divider
Prog.
Divider
LOW
or MID
SAW
Driver
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OSCLOW/MIDIN
OSCLOW/MIDOUT
OSCLOW/MIDOUT
OSCLOW/MIDIN
RFGND
ADC
IFOUT
IFOUT
VT
CP
Charge
Pump
OSCHIGHIN
CP,
CM,
OS
OSCHIGHOUT
Oscillator
LOW/MID
OSCHIGHOUT
HIGH
Phase/
Frequency
Comparator
OSCHIGHIN
Oscillator
HIGH
fref
fdiv
Block_diag
Figure 3-2
Wireless Components
Block Diagram
3-7
Specification, July 2001
TUA6024-2
Functional Description
3.4 Circuit Description
3.4.1
General
In the normal mode (see Table 5-7 Test modes on page 31) the IC is compatible with
TUA6024-S and TUA6024-K. An extended mode makes a reference divider
ratio of 24 (see Table 5-8 Reference divider ratio on page 31) and two additional charge
pump currents (see Table 5-9 Charge pump current on page 32) available.
3.4.2
Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced
mixer), two balanced oscillators for LOW and / or MID band and HIGH band, an
IF amplifier, a reference voltage source and a band switch.
Filters between tuner input and IC separate the TV frequency signals into two
bands. The band switching in the tuner front-end is done by using two or three
port outputs. In the selected band the signal passes a tuner input stage with
MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has in case of LOW / MID a high-impedance
input and in case of HIGH a low-impedance input. The input signal is mixed
there with the signal from the activated on chip oscillator to the IF frequency
which is filtered out at the balanced high-impedance output pair by means of a
parallel tuned circuit. The following SAW preamplifier has a low output impedance to drive the SAW filter directly.
3.4.3
PLL block
The oscillator signal is internally DC-coupled as a differential signal to the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital
frequency / phase detector to a reference frequency fref = 31.25, 50, 62.5 or
166.7 kHz.This frequency is derived from an unbalanced, low-impedance 4
MHz crystal oscillator (pin XTAL) divided by R = 128, 80, 64 or 24.
The phase detector has two outputs that drive two current sources of opposite
polarity as charge pump. If the negative edge of the divided VCO signal appears
prior to the negative edge of the reference signal, the positive current source
pulses for the duration of the phase difference. In the reverse case the negative
current source pulses. If the two signals are in phase, the charge pump output
(CP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO
(internal amplifier, external pull-up resistor at TUNE and external RC circuitry).
The charge pump output is also switched into the high-impedance state if the
Wireless Components
3-8
Specification, July 2001
TUA6024-2
Functional Description
control bits T0 = 1 and T1 = 0. Here it should be noted, however, that the tuning
voltage can alter over a long period in the high-impedance state as a result of
self-discharge in the peripheral circuitry. TUNE may be switched off by the control bit OS to allow external adjustments.
If the VCO is not oscillating the PLL locks to a tuning voltage of 33 V .
By means of the control bits CP, CM, T0 and T1 the pump current can be
switched between four values by software. This programmability permits alteration of the control response time of the PLL in the locked-in state. In this way
different VCO gains can be compensated, for example.
The software-switched ports PLOW, PMID and PHIGH are general-purpose
open-collector outputs. The test bits T0 = 0 and T1 = 1 switches the test signals
fref (i.e.fXTAL / 64) and f div (divided input signal) to PLOW and PMID respectively.
The lock detector resets the lock flag FL if the width of the charge pump current
pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL
= 1, the maximum deviation of the input frequency from the programmed frequency is given by
∆f = ± IP (KVCO / fXTAL) (C1+C2) / (C1C2)
where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-2 Evaluation Board, low phase noise application on page 20). As the charge pump pulses at i.e. 62.5
kHz (= fref), it takes a maximum of 16 µs for FL to be reset after the loop has lost
lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive fref periods. Therefore it takes between 128 and
144 µs for FL to be set after the loop regains lock.
3.4.4
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The
clock is generated by the processor (input SCL), while pin SDA functions as an
input or output depending on the direction of the data (open collector, external
pull-up resistor). Both inputs have hysteresis and a low-pass characteristic,
which enhance the noise immunity of the I2C bus.
The data from the processor pass through an I2C bus controller. Depending on
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are HIGH). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH
while SCL remains HIGH. All further information transfer takes place during
SCL = LOW, and the data is forwarded to the control logic on the positive clock
edge.
The table ”Bit Allocation” (see Table 5-4 Bit Allocation Read / Write on page 30) should be
referred to the following description. All telegrams are transmitted byte-by-byte,
followed by a ninth clock pulse, during which the control logic returns the SDA
Wireless Components
3-9
Specification, July 2001
TUA6024-2
Functional Description
line to LOW (acknowledge condition). The first byte is comprised of seven
address bits. These are used by the processor to select the PLL from several
peripheral components (chip select). The LSB bit (R/W) determines whether
data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists the lock flag and the power-on flag.
Four different chip addresses can be set by appropriate DC level at pin AS (see
Table 5-6 Address selection on page 31).
While applying the supply voltage, a power-on reset circuit prevents the PLL
from setting the SDA line to LOW, which would block the bus. The power-on
reset flag POR is set at power-on and when VCC falls below 3.2 V. It will be reset
at the end of a READ operation.
Wireless Components
3 - 10
Specification, July 2001
4
Applications
Contents of this Chapter
4.1
4.2
Evaluation board, PAL application . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Evaluation board, low phase noise application . . . . . . . . . . . . . . . . . . 4-3
TUA6024-2
Applications
4.1 Evaluation board, PAL application
RGen = 75 Ω
HIGH
RGen = 75 Ω
SDA
SCL
AS
PHIGH PMID
PLOW
VCC
LOW/
MID
4n7
1:1*)
100p
100p
4n7
4n7
4n7
4n7
4 MHz
68p
22p
68p
47n
220
220
18p
1n
22p
L4
2p2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10
11
12
13
14
TUA6024-2
2
1p2
3
1p2
4
1p2
5
1p2
L1
6
7
2p7
2p2
L2
L3
8
2p2
9
12p
120p
2:10**)
ADC
1k
1p
15p
C1
47n
100p
2p7
22k
1
C2
2n2
100n
220
BA892
82p
1k8
100k
RLoad = 75 Ω
2k7
33k
560
1k
1n
1k8
BB565
3k3
BB659C
IFoutput
2k7
4n7
+ 33 V
10n
TUA6024-2_application-circuit
Figure 4-1
Evaluation Board, PAL application
Table 4-1 Recommended band limits in MHz
RF input
Table 4-1 Coils
Oscillator
turns
E
wire E
min
max
min
max
L1
1.5
2.4 mm
0.5 mm
LOW
48.25
140.25
87.15
179.15
L2
2.5
3mm
0.5 mm
MID
147.25
423.25
193.15
462.15
L3
8.5
3.2 mm
0.5 mm
HIGH
431.25
855.25
470.15
894.15
L4
14.5
4 mm
0.3 mm
Wireless Components
4-2
*)
TOKO B4F Type 617DB-1023
**)
TOKO 7KL600 GCS-A1010DX
Specification, July 2001
TUA6024-2
Applications
4.2 Evaluation board, low phase noise application
RGen = 75 Ω
HIGH
RGen = 75 Ω
SDA
SCL
AS
PHIGH PMID
PLOW
VCC
LOW/
MID
4n7
1:1*)
100p
100p
4n7
4n7
4n7
4n7
4 MHz
68p
22p
68p
47n
220
220
18p
1n
22p
L4
2p2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10
11
12
13
14
TUA6024-2
2
1p2
3
1p2
4
1p2
5
1p2
L1
6
7
2p7
2p2
L2
L3
8
2p2
9
12p
120p
2:10**)
ADC
1k
1p
15p
C1
100n
100p
2p7
12k
1
C2
2n2
100n
220
82p
1k8
3k3
100k
33k
560
1k
1n
1k8
BB565
BA892
RLoad = 75 Ω
2k7
BB659C
IFoutput
2k7
4n7
22n
560
+ 33 V
47n
TUA6024-2_application-circuit
Figure 4-2
Evaluation Board, low phase noise application
Table 4-1 Recommended band limits in MHz
RF input
Table 4-1 Coils
Oscillator
turns
E
wire E
min
max
min
max
L1
1.5
2.4 mm
0.5 mm
LOW
48.25
140.25
87.15
179.15
L2
2.5
3mm
0.5 mm
MID
147.25
423.25
193.15
462.15
L3
8.5
3.2 mm
0.5 mm
HIGH
431.25
855.25
470.15
894.15
L4
14.5
4 mm
0.3 mm
Wireless Components
4-3
*)
TOKO B4F Type 617DB-1023
**)
TOKO 7KL600 GCS-A1010DX
Specification, July 2001
5
Reference
Contents of this Chapter
5.1
5.1.1
5.1.2
5.1.3
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Table 5-9 Charge pump current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Table 5-10 Bandswitching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Table 5-11 A/D converter levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.3
I2C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Gain (GV) test Set-up in LOW/MID. . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Gain (GV) test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Matching circuit for optimum noise figure in LOW/MID. . . . . . . . . . . 5-16
Noise Figure Test Set-up in LOW/MID . . . . . . . . . . . . . . . . . . . . . . . 5-16
Noise Figure Test Set-up in HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-17
Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-18
Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.5
5.5.1
5.5.2
5.5.3
5.5.4
Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Input admittance (S11) of the LOW/MID band mixer input . . . . . . . . 5-19
Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-19
Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-20
Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-20
TUA6024-2
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T AMB= - 20°C ...TAmax
Parameter 1).
Symbol
Limit Values
min
max
Supply voltage
VCC
-0.3
6
Ambient temperature
TA
-10
TAmax
Unit
Remarks
V
°C
2).
Junction temperature
TJ
Storage temperature
TStg
Temperature difference junction to case 3).
TJC
-40
+125
°C
+125
°C
2
K
PLL
CP
VCHGPMP
-0.3
ICHGPMP
Crystal oscillator pin XTAL
VXTAL
3
V
1
mA
VCC
IXTAL
-5
Bus input/output SDA
VSDA
-0.3
Bus output current SDA
ISDA(L)
Bus input SCL
VSCL
Chip address switch AS
V
mA
6
V
5
mA
-0.3
6
V
VAS
-0.3
VCC
V
VCO tuning output (loop filter)
VT
-0.3
35
V
ADC input
VADC
-0.3
VCC
V
Port outputs PLOW, PMID, PHIGH
VP
-0.3
VCC
V
IP(L)
-1
25
mA
tmax = 0.1 sec.
at 5.5 V
40
mA
tmax = 0.1 sec.
at 5.5 V
Total port output current
Wireless Components
ΣIP(L)
5-2
open collector
Specification, July 2001
TUA6024-2
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature T AMB= - 20°C ... + 85°C (continued)
Parameter 1)
Symbol
Limit Values
Unit
min
max
-0.3
3
V
2
V
-5
6
mA
-0.3
3
V
VCC
V
2
kV
Remarks
Mixer-Oscillator
Mix input LOW/MID
Vi
Mix inputs HIGH
Vi
Ii
VCO base voltage
VB
VCO collector voltage
VC
ESD-Protection 4).
all pins
VESD
1). All values are referred to ground (pin), unless stated otherwise.
Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin.
2).The maximum ambient temperature depends on the mounting conditions of the package. Any application
mounting must guarantee not to exceed the maximum junction temperature of 125 °C. As reference the temperature difference junction to case is given.
3).Referred to top center of package
4). According to EIA/JESD22-A114-B (HBM incircuit test), as a single device incircuit contact discharge test.
Wireless Components
5-3
Specification, July 2001
TUA6024-2
Reference
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit
description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range
Parameter
Symbol
Limit Values
min
max
Unit
Supply voltage
VCC
+4.5
+5.5
Programmable divider factor
N
256
32767
LOW/MID Mixer input frequency
range
fi
30
500
MHz
HIGH Mixer input frequency
range
fi
400
900
MHz
LOW/MID Oscillator frequency
range
fO
65
560
MHz
HIGH Oscillator frequency range
fO
430
950
MHz
Ambient temperature
TAMB
-20
TAmax
°C
Test Conditions
L
Item
V
1).
1).see 5.1.1 Absolute Maximum Ratings on page 2
Wireless Components
5-4
Specification, July 2001
TUA6024-2
Reference
5.1.3
AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified
supply voltage and ambient temperature range. Typical characteristics are the
median of the production.
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC
Symbol
Limit Values
Unit
min
typ
max
Test Conditions
L
Item
Supply
Supply voltage
VCC
4.5
5
5.5
V
Current consumption
ICC
48
61
74
mA
LOW/MID band
51
65
79
mA
HIGH band
4.0
4.8
MHz
series resonance
100
Ω
series resonance
Digital Unit
PLL
Crystal oscillator connections XTAL
Crystal frequency
fXTAL
3.2
Crystal resistance
RXTAL
10
Oscillation frequency
fXTAL
3,99975
4,000
4,00025
MHz
fXTAL = 4 MHz
Input impedance
ZXTAL
-500
-700
-900
Ω
fXTAL = 4 MHz
ICPDH
± 430
± 650
± 860
µA
VCP = 1.8 V
ICPH
± 180
± 250
± 360
µA
VCP = 1.8 V
ICPDL
± 90
± 125
± 180
µA
VCP = 1.8 V
ICPL
± 35
± 50
± 70
µA
VCP = 1.8 V
nA
T0 = 1, T1 = 0
2.5
V
PLL locked
Charge pump output CP
Output current,
see Table 5-9 Charge
pump current on page 12
Tristate current
ICPZ
Output voltage
VCP
±1
1.3
Drive output VT (open collector)
HIGH output current
ITH
10
µA
VTH = 33 V, T0 = 1,
T1 = 0
LOW output voltage
VTL
0.4
V
ITL = 1.0 mA
I2C-Bus
Bus inputs SCL, SDA
HIGH input voltage
VIH
3
5.5
V
LOW input voltage
VIL
0
1.5
V
HIGH input current
IIH
10
µA
VIH = V CC
LOW input current
IIL
µA
VIL = 0 V
Wireless Components
-10
5-5
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC (continued)
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
Bus output SDA (open collector)
HIGH output current
IOH
10
µA
VOH = 5.5 V
LOW output voltage
VOL
0.4
V
IOL = 3 mA
Rise time
tr
300
ns
Fall time
tf
300
ns
400
kHz
Edge speed SCL,SDA
Clock timing SCL
Frequency
fSCL
HIGH pulse width
tH
0.6
µs
LOW pulse width
tL
1.3
µs
Set-up time
tsusta
0.6
µs
Hold time
thsta
0.6
µs
Set up time
tsusto
0.6
µs
Bus free
tbuf
1.3
µs
Set-up time
tsudat
0.1
µs
Hold time
thdat
0
µs
Input hysteresis
SCL, SDA
Vhys
Pulse width of spikes
which are suppressed
tsp
Capacitive load for
each bus line
CL
0
Start condition
Stop condition
Data transfer
200
mV
0
50
ns
400
pF
Port outputs PLOW, PMID, PHIGH (open collector)
HIGH output current
IPOH
1
µA
VPOH = 5 V
LOW output voltage
VPOL
0.5
V
IPOL = 25 mA
HIGH input current
IADCH
10
µA
LOW input current
IADCL
ADC port input
-10
µA
Address selection input AS
HIGH input current
IASH
LOW input current
IASL
Wireless Components
50
-50
5-6
µA
VASH = 5 V
µA
VASL = 0 V
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC (continued)
Symbol
Limit Values
min
Unit
Test Conditions
typ
max
23
26
dB
fRF = 43.25 to 463.25
MHz, fIF = 33.4 to
58.75 MHz
11
dB
fRF = 43.25 to 463.25
MHz
L
Item
Analog Unit
LOW/MID Band Section (including IF amplifier)
Voltage gain
GV
Mixer noise figure
NF
9
Output voltage
causing 0.8% of
crossmodulation in
channel, see 5.4.6 on
page 17
Vi
118
dBµV
fRFw = 48.25 MHz
Vi
117
dBµV
fRFw = 399.25 MHz
Input IP2
IIP2
137
dBµV
fRF1 = 48.25 MHz
fRF2 = 98.50 MHz,
PRF1 = P RF2
IIP2
137
dBµV
fRF1 = 415.25 MHz
fRF2 = 832.50 MHz,
PRF1 = P RF2
IIP3
119
dBµV
fRF1 = 48.25 MHz
fRF2 = 49.25 MHz
PRF1 = P RF2
IIP3
119
dBµV
fRF1 = 252.25 MHz
fRF2 = 253.25 MHz,
PRF1 = P RF2
Output voltage causing 1 dB compression
Vo
121
dBµV
fRF = 48.25 MHz
Vo
121
dBµV
fRF = 252.25 MHz
Mixer input
impedance
Ri
Input IP3
Ci
20
0.5
1
1.5
kΩ
parallel equivalent
circuit,
fRF = 100 MHz
2
3
pF
parallel equivalent
circuit,
fRF = 100 MHz
Oscillator frequency
shift, PLL unlocked
∆fOsc(V)
400
kHz
VCC = 5 V±10%
Oscillator frequency
drift, PLL unlocked
∆fOsc(T)
500
kHz
∆T = 25 °C
Oscillator frequency
drift, PLL unlocked
∆fOsc(t)
100
kHz
t = 5 s up to 15 min
after switching on
Wireless Components
5-7
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC (continued)
Symbol
Oscillator pulling,
PLL unlocked
Vi
Limit Values
Unit
Test Conditions
min
typ
100
108
dBµV
∆f = 10 kHz
fRF = 48.25 MHz
100
108
dBµV
∆f = 10 kHz
fRF = 399.25 MHz
Oscillator
N+5
-50
dBc
fRF = 48.25 MHz,
fRF1 = 83.25 MHz,
PRF=P RF1 = 80dBµV
N+5
-50
dBc
fRF = 399.25 MHz,
fRF1 = 439.25 MHz,
PRF=P RF1 = 80dBµV
ΦOSC
-58
-60
dBc/Hz
fm = 1kHz
-88
-90
dBc/Hz
fm = 10kHz
15
20
dB
VIF = 80 dBµV
phase noise 1).
IF suppression
aIF
Item
max
Vi
N + 5 pulling,
PLL unlocked
L
HIGH Band Section (including IF amplifier)
Voltage gain
GV
Mixer noise figure
NF
31
34
37
dB
fRF = 367.25 MHz to
863.25 MHz,
fIF = 33.4MHz to
58.75 MHz
6
9
dB
fRF = 367.25 to
615.25 MHz
7
10
dB
fRF = 623.25 to
863.25 MHz
Output voltage
causing 0.8% of
crossmodulation in
channel,
see 5.4.7 on page 18
Vi
116
dBµV
fRFw = 503.25 MHz
Vi
117
dBµV
fRFw = 799.25 MHz
Input IP2
IIP2
139
dBµV
fRF1 = 423.25 MHz
fRF2 = 848.50 MHz,
PRF1 = PRF2
Input IP3
IIP3
108
dBµV
fRF1 = 503.25 MHz
fRF2 = 504.25 MHz
PRF1 = PRF2
IIP3
108
dBµV
fRF1 = 799.25 MHz
fRF2 = 800.25 MHz
PRF1 = PRF2
Vo
121
dBµV
fRF = 503.25 MHz
Vo
121
dBµV
fRF = 799.25 MHz
Output voltage causing 1 dB compression
Wireless Components
5-8
Specification, July 2001
TUA6024-2
Reference
Table 5-3 AC/DC Characteristics with TAMB = 25 °C, V CC (continued)
Symbol
Mixer input
impedance
Limit Values
Unit
Test Conditions
min
typ
max
Ri
14
20
26
Ω
serial equivalent circuit, fRF = 600 MHz
Li
6
10
14
nH
serial equivalent circuit, fRF = 600 MHz
Oscillator frequency
shift, PLL unlocked
∆fOsc(V)
400
kHz
VCC = 5 V±10%
Oscillator frequency
drift, PLL unlocked
∆fOsc(T)
800
kHz
∆T = 25 °C
Oscillator frequency
drift, PLL unlocked
∆fOsc(t)
100
kHz
t = 5 s up to 15 min
after switching on
Oscillator pulling,
PLL unlocked
Vi
N + 5 pulling,
PLL unlocked
Oscillator
phase noise
108
dBµV
∆f = 10 kHz
fRF = 375.25 MHz
100
108
dBµV
∆f = 10 kHz
fRF = 847.25 MHz
Vi
-50
dBc
fRF = 471.25 MHz,
fRF1 = 511.25 MHz,
PRF =PRF1 = 80dBµV
Vi
-50
dBc
fRF = 847.25 MHz,
fRF1 = 887.25 MHz,
PRF=P RF1 = 80 dBµV
ΦOSC
-58
-60
dBc/Hz
fm = 1kHz
-88
-90
dBc/Hz
fm = 10kHz
15
20
dB
Vi = 80 dBµV
RIF
125
Ω
LIF
10
nH
serial equivalent
circuit,
fIF = 38.9 MHz
1.)
IF suppression
100
aIF
L
Item
SAW preamplifier
IF output impedance
Rejection at the IF outputs
Divider interference
level
Vo
30
dBµV
2).
Channel S02 beat
a
66
dBc
rejection 3).
fRF = 76.25 MHz
PRF = 80 dBµV
■ This value is only guaranteed in lab.
1). Measured in the evaluation board (see Chapter 4), worst case in band.
2). This is the level of divider interferences close to the IF frequency. For example channel S3:
fOSC = 158.15 MHz, 1/4 fOSC = 39.5375 MHz. Divider interference is measured in the evaluation
board (see Chapter 4).
3). Channel S02 beat is the interfering product of fRF, fIF and fOSC of channel S02, fbeat = 37.35 MHz.
The possible mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC. Measured in the evaluation board
(see Chapter 4).
Wireless Components
5-9
Specification, July 2001
TUA6024-2
Reference
5.2 Programming
Table 5-4 Bit Allocation Read / Write
Byte
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Address Byte
1
1
0
0
0
MA1
MA0
0
A
Progr. Divider
Byte 1
0
N14
N13
N12
N11
N10
N9
N8
A
Progr. Divider
Byte 2
N7
N6
N5
N4
N3
N2
N1
N0
A
Control Byte
1
CP
T1
T0
CM
RSA
RSB
OS
A
Bandswitch
x
x
x
x
P3
P2
P1
P0
A
1
1
0
0
0
MA1
MA0
1
A
POR
FL
x
x
x
A2
A1
A0
A
Remark
Write Data
Byte 1).
Read Data
Address Byte
Status Byte
1). see Table 5-10 Bandswitching on page 12
Table 5-5 Description of symbols
Description
Symbol
MA0, MA1
Address selection bits (see Table 5-6 Address selection on page 11)
N14 to N0
programmable divider bits:
N = 214 x N14 + 213 x N13 + ..... + 23 x N3 + 22 x N2 + 21 x N1 + N0
CP
charge pump current:
T1, T0
test bits (see Table 5-7 Test modes on page 11)
CM
charge pump mode bit (see Table 5-9 Charge pump current on page 12)
RSA, RSB
reference divider bits (see Table 5-8 Reference divider ratio on page 11)
OS
tuning amplifier control bit:
bit = 0: enable VT
bit = 1: disable VT
PLOW, PMID, PHIGH,
see 5-10 on page 12
NPN ports control bits:
bit = 0: NPN open-collector output is inactive
bit = 1: NPN open-collector output is active
A0, A1, A2
ADC bits (see Table 5-11 A/D converter levels on page 13)
FL
PLL lock flag
POR
Power-on reset flag
flag is set at power-on and reset at the end of READ operation
x
don‘t care
Wireless Components
bit = 0: charge pump current = 50 µA
bit = 1: charge pump current = 250µA
bit = 1: loop is locked
5 - 10
Specification, July 2001
TUA6024-2
Reference
Table 5-6 Address selection
Voltage at AS
MA1
MA0
(0...0.1) * V CC
0
0
(0.2...0.3) * VCC or open circuit
0
1
(0.4...0.6) * V CC
1
0
(0.9...1) * V CC
1
1
Table 5-7 Test modes
Mode
Test mode
Normal operation
normal
Charge pump output, CP is in high-impedance state
1).
PMID = fdiv output, PLOW = fref output
Extended operation
extended
T1
T0
0
0
0
1
1
0
1
1
1). In this mode the IC is compatible with TUA6024-S and TUA6024-K
Table 5-8 Reference divider ratio
T1
T0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
RSA
RSB
fref 2).
x
0
50 kHz
0
1
31.25 kHz
1
1
62.5 kHz
0
0
50 kHz
0
1
31.25 kHz
24
1
0
166.7 kHz
64
1
1
62.5 kHz
Reference divider ratio
Mode 1).
80
128
normal
64
80
128
extended
1
1
1). see Table 5-7 Test modes on page 11
2). With a 4 MHz quartz.
Wireless Components
5 - 11
Specification, July 2001
TUA6024-2
Reference
Table 5-9 Charge pump current
Charge pump current
CP
Mode 1).
50 µA
T0
0
0
1
0
50 µA
x
0
0
extended
CM
x
0
normal
250 µA
125 µA
T1
1
1
1
250 µA
1
0
600 µA
1
1
1). see Table 5-7 Test modes on page 11
Table 5-10 Bandswitching
Bit Designation
P3
P2
P1
P0
Active Port
Pin
PHIGH 1).
17
0
0
0
0
PLOW
15
0
0
0
1
PMID
16
0
0
1
0
0
0
1
1
not used
PHIGH
17
0
1
0
0
PLOW
15
0
1
0
1
PMID
16
0
1
1
0
0
1
1
1
not used
PHIGH
17
1
0
0
0
PLOW
15
1
0
0
1
PMID
16
1
0
1
0
1
0
1
1
not used
PHIGH
17
1
1
0
0
PLOW
15
1
1
0
1
PMID
16
1
1
1
0
1
1
1
1
not used
1). Default after power-on
Wireless Components
5 - 12
Specification, July 2001
TUA6024-2
Reference
Table 5-11 A/D converter levels
A2
A1
A0
(0...0.15)*V CC
0
0
0
(0.15...0.3)*V CC
0
0
1
(0.3...0.45)*V CC
0
1
0
(0.45...0.6)*V CC
0
1
1
(0.6...1)*V CC
1
0
0
Voltage at ADC
Wireless Components
5 - 13
Specification, July 2001
Start
Wireless Components
1
5 - 14
MA1 MA0 R/W
DB1= prog. divider byte 1
DB2= prog. divider byte 2
Start-ADB-DB1-DB2-Stop
Start-ADB-CB-BB-Stop
Stop= stop condition
BB= Bandswitch byte
CB= Control byte
ADB= address byte
Start-ADB-CB-BB-DB1-DB2-Stop
2nd Byte Ack. 3rd Byte Ack.
Start= start condition
SCL:
0
Ack.
Start-ADB-DB1-DB2-CB-BB-Stop
0
1st Byte
Abbreviations:
0
Ack.
Telegram examples:
Note: SDA:
1
Addressing
4th Byte
Ack.
Stop
TUA6024-2
Reference
5.3 I2C Bus Timing Diagram
Specification, July 2001
TUA6024-2
Reference
5.4 Test Circuits
5.4.1
Gain (GV) test Set-up in LOW/MID
LOW/
MIDIN
50 Ω
Vmeas
50 Ω
V
RMS
Voltmeter
IFOUT
Device
under
Test
Vi
Transformer
N1
N2
50 Ω
spectrum
analyser
V0
C
V'meas
IFOUT
N1 : N2 = 10 : 2 turns
GVHF2
5.4.2
■
Zi >> 50 Ω => V i = 2 x Vmeas = 80 dBµV
■
Vi = Vmeas + 6dB = 80 dBµV
■
V0 = V’meas + 16 dB (transformer ratio N1:N2 and transformer loss)
■
Gv = 20 log(V0 / Vi)
Gain (GV) test Set-up in HIGH
HIGHIN IFOUT
50 Ω
Vmeas
RMS
Voltmeter
V
50 Ω
Vi
Balun
1:1
Device
under
Test
Transformer
N1
N2
V0
C
V'meas
50 Ω
spectrum
analyser
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
GUHF2
Wireless Components
■
Vi = Vmeas = 70 dBµV
■
V0 = V’meas + 16 dB (transformer ratio N1:N2 and transformer loss)
■
Gv = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun)
5 - 15
Specification, July 2001
TUA6024-2
Reference
5.4.3
Matching circuit for optimum noise figure in LOW/MID
22p
15p
1n
In
1n
In
Out
Out
7 turns
wire ⍪ 0.5 mm
coil ⍪ 5.5 mm
22p
50 τ semi rigid cable
300 mm long
96 pF/m
33dB/100m
22p
NFM
For fRF = 150 MHz
For fRF = 50 MHz
■
loss = 0 dB
■
loss = 1.3 dB
■
image suppression = 16 dB
■
image suppression = 13 dB
5.4.4
Noise
Source
Noise Figure Test Set-up in LOW/MID
IN
OUT
Matching
Circuit
LOW/
MIDIN
IFOUT
Transformer
Device
under
Test
N1
N2
Noise
Figure
Meter
C
IFOUT
N1 : N2 = 10 : 2 turns
NF = NFmeas - loss of matching circuit (dB)
NFVHF2
Wireless Components
5 - 16
Specification, July 2001
TUA6024-2
Reference
5.4.5
Noise Figure Test Set-up in HIGH
Noise
Source
HIGHIN IFOUT
Device
under
Test
Balun
1:1
Noise
Figure
Meter
Transformer
N1
N2
C
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
loss of balun = 1 dB
NF = NFmeas - loss of balun (dB)
NFUHF2
5.4.6
Cross modulation Test Set-up in LOW/MID band
Vmeas
50 Ω
RMS
Voltmeter
unwanted
signal
source
AM = 80 %
A
LOW/
MIDIN
C
50 Ω
Hybrid
Vi
50 Ω
B
wanted
signal
source
V
D
IFOUT
Device
under
Test
Transformer
N1
18 dB
attenuator
N2
38.9 MHz
V0
C
V
V'meas
IFOUT
N1 : N2 = 10 : 2 turns
50 Ω
50 Ω
modulation
analyser
RMS
Votmeter
XVHF2
Wireless Components
■
Zi >> 50 Ω => Vi = 2 x Vmeas
■
V’meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss)
■
wanted output signal at fpix, Vo = 100 dBµV
■
unwanted output signal at fsnd , 80 % AM modulated with 1 kHz
5 - 17
Specification, July 2001
TUA6024-2
Reference
5.4.7
Cross modulation Test Set-up in HIGH band
Vmeas
V
50 Ω
RMS
Voltmeter
unwanted
signal
source
AM = 80 %
A
C
HIGHIN IFOUT
50 Ω
Hybrid
Vi
Device
under
Test
Balun
1:1
50 Ω
B
D
Transformer
N1
N2
38.9 MHz
V0
C
V
V'meas
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
wanted
signal
source
18 dB
attenuator
50 Ω
50 Ω
modulation
analyser
RMS
Votmeter
XUHF2
5.4.8
■
V’meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss)
■
wanted output signal at fpix, Vo = 100 dBµV
■
unwanted output signal at fsnd , 80 % AM modulated with 1 kHz
Measurement of fref and fdiv
VVCC
+5V
Test Mode: T1 = 1, T0 = 0
18p
4 MHz
Device under
Test
5k
PMID
5k
fref
PLOW
fdiv
Counter
Counter
fQ = fref * R
R: reference divider ratio
fVCO = fdiv * N
N: divider ratio
freq_meas_cof
Wireless Components
5 - 18
Specification, July 2001
TUA6024-2
Reference
5.5 Electrical Diagrams
5.5.1
Input admittance (S11) of the LOW/MID band mixer input
0.8
2
0.5
0.6
0.7
1
1.5
0.9
Y0 = 20mS (single ended)
0.4
3
0.3
4
0.2
5
0.1
10
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1
0.9
0.8
1.5
2
3
4
5
10
20
20
0
48.25 MHz
20
10
0.1
407.25 MHz
5
0.2
4
0.3
3
0.7
0.8
0.9
1
1.5
0.6
2
0.5
0.4
5.5.2
Input impedance (S11) of the HIGH band mixer input
1.5
1
0.9
0.8
0.5
2
0.6
0.7
Z0 = 50 Ω (balanced)
0.4
3
0.3
4
5
0.2
855.25 MHz
10
0.1
415.25 MHz
20
10
5
4
3
2
1.5
0.8
0.9
1
0.7
0.6
0.5
0.4
0.3
0.2
0.1
20
0
Rdiff
20
0.1
10
0.2
5
4
0.3
3
Wireless Components
5 - 19
1.5
1
0.8
0.9
0.7
0.6
2
0.5
0.4
Specification, July 2001
TUA6024-2
Reference
5.5.3
Output admittance (S22) of the Mixer output
0.8
2
0.5
0.6
0.7
1
1.5
0.9
Y0 = 20mS (balanced)
0.4
3
0.3
4
0.2
5
0.1
10
0.2
0.3
0.4
0.5
0.6
0.7
1
0.9
0.8
1.5
2
3
4
5
10
0.1
0
20
20
Rdiff
38.9 MHz
20
10
0.1
5
0.2
4
0.3
3
0.7
0.8
0.9
1
1.5
0.6
2
0.5
0.4
5.5.4
Output impedance (S22) of the IF output
1.5
1
0.9
0.8
0.5
2
0.6
0.7
Z0 = 50 Ω (single/ double ended)
0.4
3
0.3
4
5
0.2
10
0.1
Rse
20
10
5
4
3
2
1.5
0.8
0.9
1
0.7
0.6
0.5
0.4
0.3
0.2
0.1
20
0
Rdiff
20
0.1
10
0.2
5
4
0.3
3
Wireless Components
5 - 20
1.5
1
0.8
0.9
0.7
0.6
2
0.5
0.4
Specification, July 2001