INTEGRATED CIRCUITS
DATA SHEET
TDA8000; TDA8000T
Smart card interface
Product specification
Supersedes data of 1995 Feb 01
File under Integrated Circuits, IC02
1996 Dec 12
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
FEATURES
APPLICATIONS
• Two protected I/O lines
• Pay TV
• VCC regulation (5 V ±4%, 100 mA max. with controlled
rise and fall times)
• Telematics
• VPP generation (12.5, 15 or 21 V ±2.5%, 50 mA max.
programmable by two bits, with controlled rise and fall
times)
• Multipurpose card-readers, etc.
• Cashless payment
• Clock generation (up to 8 MHz)
GENERAL DESCRIPTION
• Short-circuit, thermal and card extraction protections
The TDA8000 is a complete, low-cost analog interface
which can be positioned between a smart card or a
memory card (ISO 7816) and a microcontroller. It is
approved for banking, telecom and pay TV applications.
• Two voltage supervisors (digital and analog supplies)
• Automatic activation and deactivation sequences via an
independent internal clock
The complete supply, protection and control functions are
realized with only a few external components, which
makes the TDA8000 very attractive for consumer
applications. Application suggestions and support is
available on request (see examples in
Chapter “Application information”).
• Enhanced ESD protections on card connections
(4 kV min.)
• ISO 7816 approval.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDD
supply voltage
IDD
supply current
CONDITIONS
MIN.
TYP.
MAX.
UNIT
6.7
−
18
V
idle mode; VDD = 12 V
−
25
−
mA
active modes; unloaded
−
32
−
mA
Vth2
threshold voltage on VSUP
4.5
−
4.68
V
VCC
card supply voltage
4.8
5.0
5.2
V
ICC
card supply current
−
−
−100
mA
VH
high voltage supply for VPP
−
−
30
V
IPP
programming current
tde, tact
deactivation/activation cycle
duration
Ptot
continuous total power
dissipation
Tamb
read mode; VPP = 5 V
−
−
−50
mA
write mode; VPP > 5 V
−
−
−50
mA
−
−
500
µs
TDA8000; Tamb = +70 °C;
see Fig.10
−
−
2
W
TDA8000T; Tamb = +70 °C;
see Fig.11
−
−
0.92
W
0
−
+70
°C
operating ambient temperature
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA8000
DIP28
plastic dual in-line package; 28 leads (600 mil)
SOT117-1
TDA8000T
SO28
plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
1996 Dec 12
2
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
BLOCK DIAGRAM
handbook, full pagewidth
ALARM
ALARM
I/O1(µC)
I/O2(µC)
RSTIN
VSUP
DELAY
15
16
VDD
GND
13
12
17
18
VOLTAGE
SUPERVISOR
MAIN
SUPPLY
28
3
PROTECTIONS
AND
ENABLE
27
26
2
4
TDA8000
19
OFF
22
9
CVNC
I/O1
I/O2
RST
PRES
8
PRES
LOGIC
20
PROTECTIONS
START
21
WRITE
INTERNAL
CLOCK
VCC
GENERATOR
14
CLOCK
CIRCUITRY
CLOCK
ENABLE
5
VPP
10
VCC
23
CLKDIV
CLKOUT
PSEL1
PSEL2
25
6
CLK
VPP
GENERATOR
7
OSCILLATOR
1
24
XTAL
CLKIN
11
MBH810
VH
Fig.1 Block diagram.
1996 Dec 12
3
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
PINNING
SYMBOL PIN
DESCRIPTION
XTAL
1
crystal connection
I/O2
2
data line to/from the card
I/O1
3
data line to/from the card
RST
4
card reset output
CLK
5
clock output to the card
PSEL1
6
programming voltage selection input (see Table 1)
PSEL2
7
programming voltage selection input (see Table 1)
PRES
8
card presence contact input (active LOW)
PRES
9
card presence contact input (active HIGH)
VPP
10
fpage
XTAL 1
28 I/O1(µC)
card programming voltage output
I/O2 2
27 I/O2(µC)
I/O1 3
26 RSTIN
RST 4
25 CLKOUT
CLK 5
24 CLKIN
VH
11
high voltage supply for VPP generation
GND
12
ground
VDD
13
positive supply voltage
VCC
14
card supply output voltage
VSUP
15
voltage supervisor input
PSEL1 6
DELAY
16
external capacitor connection for delayed reset timing
PSEL2 7
ALARM
17
open-collector reset output for the microcontroller (active
HIGH)
ALARM
18
open-collector reset output for the microcontroller (active
LOW)
OFF
19
interrupt output to the microcontroller (active LOW)
23 CLKDIV
22 CVNC
PRES 8
TDA8000
TDA8000T 21 WRITE
PRES 9
20 START
VPP 10
19 OFF
VH 11
18 ALARM
START
20
microcontroller input for starting session (active LOW)
GND 12
17 ALARM
WRITE
21
control input for applying programming voltage to the card
(active LOW)
VDD 13
16 DELAY
CVNC
22
internally generated 5 V reference, present when VDD is
on; to be decoupled externally (47 nF)
VCC 14
15 VSUP
CLKDIV
23
input for dividing/not dividing the CLKOUT frequency by
two (active LOW)
CLKIN
24
external clock signal input
CLKOUT
25
clock output to the microcontroller, or another TDA8000
RSTIN
26
card reset input from the microcontroller (active HIGH)
I/O2(µC)
27
data line to/from the microcontroller; must not be left
open-circuit, tie to CVNC if not used
I/O1(µC)
28
data line to/from the microcontroller; must not be left
open-circuit, tie to CVNC if not used
1996 Dec 12
4
MBH809
Fig.2 Pin configuration.
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
FUNCTIONAL DESCRIPTION
In both events the signal is buffered and enabled.
Power supply
Pin CLKOUT may be used to clock a microcontroller.
The signal (1⁄2fxtal or fxtal if CLKDIV is HIGH) is available
when the circuit is powered up.
The circuit operates within a supply voltage range of
6.7 to 18 V. VDD and GND are the supply pins. All card
contacts remain inactive during power-up or power-down,
provided VDD does not rise or fall too fast (0.5 V/ms typ.).
State diagram
Once activated, the circuit has six possible modes of
operation:
POWER-UP
• Idle
The logic part is powered first and is in the reset condition
until VDD reaches Vth1. The sequencer is blocked until VDD
reaches Vth4 + Vhys4.
• Activation
• Read
POWER-DOWN
• Write
When VDD falls below Vth4, an automatic deactivation of
the contacts is performed.
• Fault.
• Deactivation
Figure 5 shows how these modes are accessible.
Voltage supervisor
IDLE MODE
This block surveys the 5 V supply of the microcontroller
(VSUP) in order to deliver a defined reset pulse and to avoid
any transients on card contacts during power-up or
power-down of VSUP.
After reset, the circuit enters the IDLE state. A minimum
number of circuits are active while waiting for the
microcontroller to start a session:
• All card contacts are inactive
The voltage supervisor remains active even if VDD is
powered-down.
• Voltage generators are stopped
• Oscillator is running, providing CLKOUT
POWER-UP
• Voltage supervisor is active
As long as VSUP is below Vth2 + Vhys2 the capacitor CDEL,
connected to the pin DELAY, will be discharged. When
VSUP rises to the threshold level, CDEL will be recharged.
ALARM and ALARM remain active, and the sequencer is
blocked until the voltage on the pin DELAY reaches Vth3.
• Pins I/O1(µC) and I/O2(µC) are high impedance.
The OFF line is HIGH if a card is present (PRES and
PRES active) and LOW if a card is not present.
ACTIVATION SEQUENCE
POWER-DOWN (see Fig.3)
From the IDLE mode, the circuit enters the ACTIVATION
mode when the microcontroller sets the START line
(active LOW). The I/O(µC) signals must not be LOW.
The internal circuitry is activated, the internal clock starts
and the following ISO 7816 sequence is performed:
If VSUP falls below Vth2, CDEL will be discharged, ALARM
and ALARM become active, and an automatic deactivation
of the contacts is performed.
Clock circuitry (see Fig.4)
1. VCC rises from 0 to 5 V
The clock signal (CLK) can be applied to the card by two
different methods:
2. I/Os are enabled
3. VPP rises from 0 to 5 V
1. Generation by a crystal oscillator: the crystal
(3 to 11 MHz) is connected to pin XTAL. Its frequency
is divided by two.
4. No change
5. CLK is enabled
6. RST is enabled.
2. Use of a signal frequency already present in the
system and connected to the pin CLKIN (up to 8 MHz).
Pin XTAL has to be connected to GND via a 1 kΩ
resistor. In this event, the CLKOUT signal remains
LOW.
1996 Dec 12
The typical time interval between two steps is 32 µs for the
first two steps and 64 µs for the other three. Timing is
derived from the internal clock (see Fig.6).
5
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
Between steps 3 and 5, a HIGH level on pin RSTIN allows
the CLK signal to be applied to the card. This feature
facilitates a precise count of CLK periods while waiting for
the card to respond to a reset.
DEACTIVATION SEQUENCE (see Fig.8)
When the session is completed, the microcontroller sets
the START line to its HIGH state.
After step 5, RSTIN has no further action on CLK.
The circuit then executes an automatic deactivation
sequence by counting back the sequencer:
After step 6, RST is set to the complementary value of
RSTIN.
1. Card reset (RST falls to LOW)
READ MODE
3. No change
When the activation sequence is completed and, after the
card has replied to its Answer-to-Reset, theTDA8000
enters the READ mode. Data is exchanged between the
card and the microcontroller via the I/O lines.
4. VPP falls to 0 V
2. CLK is stopped
5. I/O1(µC) and I/O2(µC) become high impedance
6. VCC falls to 0 V.
The circuit returns to the IDLE mode on the next rising
edge of the sequencer clock.
When it is required to write to the internal memory of the
card, the circuit is set to the WRITE mode by the
microcontroller.
PROTECTIONS
Cards with EPROM memory require a programming
voltage (VPP).
Main fault conditions are monitored by the circuit:
VPP GENERATION
• Short-circuit on VPP
• Short-circuit on VCC
• Over current on I/Os
The circuit supports cards with VPP of 12.5, 15 or 21 V.
The selection of P is achieved by PSEL1 and PSEL2
according to Table 1.
Table 1
• Card extraction during transaction
• Overheating problem.
When one of these fault conditions is detected, the circuit
pulls the interrupt line OFF to its active LOW state and
returns to the FAULT mode.
Card programming voltage selection
PSEL1
PSEL2
PROGRAMMING
VOLTAGE P
LOW
LOW
5
LOW
HIGH
12.5
HIGH
LOW
15
HIGH
HIGH
21
FAULT MODE (see Fig.9)
When a fault condition is written to the microcontroller via
the OFF line, the circuit initiates a deactivation sequence.
After the deactivation sequence has been completed, the
OFF line is reset to its HIGH state when the microcontroller
has reset the START line HIGH, except if the fault
condition was due to a card extraction.
In order to respect the ISO7816 slopes, the circuit
generates VPP by charging and discharging an internal
capacitor. The voltage on this capacitor is then amplified
by a power stage gain of 5, powered via an external supply
pin VH [30 V (max.)].
Note
The two other causes of emergency deactivation (Power
failure detected on VDD or VSUP) do not act upon OFF.
WRITE MODE (see Fig.7)
When the microcontroller sets the WRITE line (active
LOW), the circuit enters the WRITE mode. VPP rises from
5 V to the selected value with a typical slew rate of 1 V/µs.
When the write operation is completed, the microcontroller
returns the WRITE line to its HIGH state, and VPP falls
back to 5 V with the same slew rate.
WRITE has no action outside a session.
1996 Dec 12
6
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
Vth2 + Vhys2
handbook, full pagewidth
Vth2
VSUP
Vth3
VDELAY
td
ALARM
MGG818
Fig.3 ALARM and DELAY as a function of VSUP (CDEL fixes the pulse width).
handbook, full pagewidth
ENABLE
÷2
CLKOUT
CLKDIV
INPUT
CLK
ENCLK
OSC
INPUT
XTAL
CLKIN
MGG819
Fig.4 Clock circuitry.
handbook, full pagewidth
ACTIVATION
PDOWN
IDLE
FAULT
WRITE
READ
DEACTIVATION
MGG820
Fig.5 State diagram.
1996 Dec 12
7
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
handbook, full pagewidth PRES
OFF
tact
START
INTERNAL CLOCK
SEQUENCER CLOCK
VCC
I/O
VPP
td(clk)
CLK
ENABLE RESET
INTERNAL
RSTIN
RST
t3
tRST
t5
1
2
3
4
5
6
Fig.6 Activation sequence.
handbook, full pagewidth
START (LOW)
VCC (+5 V)
WRITE
(P)
(+5 V)
VPP (0 V)
CLK
RST (HIGH)
MGG822
Fig.7 Read/Write; Read mode.
1996 Dec 12
8
MGG821
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
tde
handbook, full pagewidth
START
OFF (HIGH)
INTERNAL CLOCK
SEQUENCER CLOCK
VCC
I/O
VPP (+5 V)
CLK
ENABLE RESET
INTERNAL
RESET-IN
RST
6
5
4
3
2
1
MGG823
Fig.8 Deactivation sequence after a normal session.
handbook, full pagewidth
START
PRES
OFF
INTERNAL CLOCK
SEQUENCER CLOCK
VCC
I/O
VPP
CLK
ENABLE RESET
INTERNAL
RESET-IN
RST
6
5
4
3
Fig.9 Deactivation after a card extraction during write mode.
1996 Dec 12
9
2
1
MGG824
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage
−0.3
+18
V
Vx1
voltage on pins PSEL1, PSEL2, PRES,
PRES, WRITE, START, OFF,
ALARM and RSTIN
−0.3
VDD
V
VH
voltage on pin VH
−0.3
+30
V
VPP
voltage on pin VPP
−0.3
VH
V
VSUP
voltage on pin VSUP
−0.3
+12
V
Vx2
voltage on pins ALARM and DELAY
−0.3
VSUP
V
Vx3
voltage on pins XTAL, I/O1(µC), I/O2(µC),
CLKIN, CLKOUT, CLKDIV and CVNC
−0.3
+6.0
V
Vx4
voltage on pins I/O1, I/O2, RST,
CLK and VCC
duration < 1 ms
−0.3
+7.0
V
Ptot
continuous total power dissipation
TDA8000; Tamb = +70 °C;
note 1; see Fig.10
−
2
W
TDA8000T; Tamb = +70 °C;
note 1; see Fig.11
−
0.92
W
Tstg
storage temperature
−55
+150
°C
Ves
electrostatic voltage on pins I/O1, I/O2, VCC,
VPP, RST and CLK
−4
+4
kV
electrostatic voltage on other pins
−2
+2
kV
Note
1. Ptot = VDD × (IDD(unloaded) + ∑Isignals) + ICC × (VDD − VCC) + max.{(VH − VPP) × IPP(read) + (VH − VPP) × IPP(write)}
+ VH × IH(unloaded) + VSUP × ISUP + (VDD − CVNC) × ICVNC.
Where ‘signals’ means all signal pins used, excluding the supply pins.
1996 Dec 12
10
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
MBE256
4
MBE255
3
handbook, halfpage
handbook, halfpage
P tot
P tot
(W)
(W)
3
2
2
1
1
0
0
50
0
50
100
150
Tamb ( o C)
50
Fig.10 Power derating curve (DIP28).
0
50
100
150
Tamb ( o C)
Fig.11 Power derating curve (SO28).
HANDLING
Each pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.
Method 3015 (HBM 1500 Ω, 100 pF) 3 pulses positive and 3 pulses negative; on each pin referenced to ground.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1996 Dec 12
PARAMETER
VALUE
UNIT
SOT117-1
30
K/W
SOT136-1
70
K/W
thermal resistance from junction to ambient in free air
11
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
CHARACTERISTICS
VDD = 12 V; VH = 25 V; VSUP = 5 V; fxtal = 7.16 MHz or fCLKIN = 3.58 MHz; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
IDD
supply current
6.7
−
18
V
idle mode; VDD = 8 V
16
22
30
mA
idle mode; VDD = 18 V
20
28
36
mA
active mode; unloaded
26
32
38
mA
Vth1
threshold voltage for power-on
reset
1.5
3.0
4.0
V
Vth4
threshold voltage on VDD (falling)
6.0
−
6.5
V
Vhys4
hysteresis on Vth4
50
−
200
mV
Voltage supervisor
VSUP
supply voltage for the supervisor
−
5
−
V
ISUP
input current on VSUP
−
1.6
2
mA
Vth2
threshold voltage on VSUP (falling)
4.5
−
4.68
V
Vhys2
hysteresis on Vth2
10
−
80
mV
Vth3
threshold voltage on DELAY
IDEL
output current on DELAY
VDEL
2.35
−
2.65
V
pin grounded (charge)
−4
−
−2.5
µA
VDEL = 4 V (discharge)
6
−
−
mA
−
−
3.5
V
voltage on pin DELAY
ALARM, ALARM (open-collector outputs)
IOH
HIGH level output current on pin
ALARM
VOH = 5 V
−
−
25
µA
VOL
LOW level output voltage on pin
ALARM
IOL = 2 mA
−
−
0.4
V
IOL
LOW level output current on pin
ALARM
VOL = 0 V
−
−
−25
µA
VOH
HIGH level output voltage on pin
ALARM
IOH = −2 mA
VSUP − 1
−
−
V
td
delay between VSUP and ALARM
CDEL = 47 nF; see Fig.3
−
−
10
µs
tpulse
ALARM pulse width
CDEL = 47 nF
30
−
65
ms
Interrupt line OFF (open-collector)
IOH
HIGH level output current
VOH = 5 V
−
−
25
µA
VOL
LOW level output voltage
IOL = 1 mA
−
−
0.4
V
Logic inputs (RSTIN, START, WRITE, CLKDIV, PSEL1, PSEL2, PRES, PRES); note 1
VIL
LOW level input voltage
−
−
0.8
V
VIH
HIGH level input voltage
1.5
−
−
V
IIL
LOW level input current
VIL = 0 V
−
−
−20
µA
IIH
HIGH level input current
VIH = 5 V
−
−
20
µA
1996 Dec 12
12
Philips Semiconductors
Product specification
Smart card interface
SYMBOL
PARAMETER
TDA8000; TDA8000T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reset output to the card (RST)
VIDLE
output voltage in IDLE mode
−
−
0.4
V
VOL
LOW level output voltage
IOL = 200 µA
−
−
0.45
V
VOH
HIGH level output voltage
IOH = −200 µA
4.0
−
VCC
V
IOH = −10 µA
VCC − 0.7
−
VCC
V
tRST
delay between RSTIN and RST
RST enabled; see Fig.6
−
−
2
µs
tr
rise time
CL = 330 pF
−
−
1
µs
tf
fall time
CL = 330 pF
−
−
1
µs
−
−
0.4
V
IOL = 200 µA
−
−
0.4
V
Clock output to card (CLK)
VIDLE
output voltage in IDLE mode
VOL
LOW level output voltage
VOH
HIGH level output voltage
IOH = −200 µA
2.4
−
VCC + 0.3
V
IOH = −20 µA
0.7VCC
−
VCC + 0.3
V
IOH = −10 µA
VCC − 0.7
−
VCC + 0.3
V
tr
rise time
CL = 30 pF; note 2
−
−
18
ns
tf
fall time
CL = 30 pF; note 2
−
−
18
ns
δ
duty factor
CL = 30 pF; (XTAL or
CLKIN used); note 2
45
−
55
%
∆δ/∆θ
thermal drift on duty factor
DIP and SO packages
−
−0.07
−
%/K
0.4
V
VCC + 4%
V
Card programming voltage (VPP)
P
selected voltage
see Table 1
VPP
output voltage
idle mode
−
−
−
IPP
SR
output current
slew rate
read mode
VCC − 4%
write mode; IPP < 50 mA
P − 2.5%(3) −
P + 2.5%(3) V
read mode
−
−
−50
mA
write mode
−
−
−50
mA
write mode; VPP
short-circuited to GND
−
−
−400
mA
up or down
0.80
1.0
1.20
V/µs
−
−
30
V
2
−
3
mA
P=5V
3
−
7
mA
P = 12.5 V
5
−
10
mA
P = 15 V
6
−
11
mA
8
−
13
mA
−
−
2.2
V
High-voltage input (VH)
VH
input voltage
IH
input current at VH
idle mode
active mode; unloaded;
WRITE = 0
P = 21 V
VH − VPP
1996 Dec 12
voltage drop
13
Philips Semiconductors
Product specification
Smart card interface
SYMBOL
PARAMETER
TDA8000; TDA8000T
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Card supply voltage (VCC)
VCC
ICC
SR
output voltage
idle mode
−
−
0.4
V
active mode;
ICC < 100 mA
4.80
−
5.20
V
−
−
−100
mA
VCC connected to GND
−
−
−400
mA
up or down
0.80
1.0
1.20
V/µs
ICVNC < −15 mA
4.5
5.0
5.5
V
3 MHz < fi < 11 MHz;
note 4
−
−
−300
Ω
output current
slew rate
5 V reference output (CVNC)
VCVNC
output voltage at CVNC
Crystal connection (XTAL)
Rxtal(neg)
negative resistance at crystal
Vxtal
DC voltage at crystal
3
−
4
V
fxtal
crystal resonant frequency
3
−
11
MHz
0
−
8
MHz
External clock input (CLKIN)
fext
frequency at CLKIN
VIL
LOW level input voltage
0
−
0.8
V
VIH
HIGH level input voltage
1.5
−
5
V
IIL
LOW level input current
VIL = 0 V
−
−
−20
µA
IIH
HIGH level input current
VIH = 2 V
CI
input capacitance
note 2
−
−
20
µA
−
−
5
pF
Clock output (CLKOUT)
fCLKOUT
frequency on CLKOUT
1
−
8
MHz
VOL
LOW level output voltage
IOL = 1 mA
−
−
0.4
V
VOH
HIGH level output voltage
VOH = −200 µA
3
−
−
V
VOH = −10 µA
4
−
−
V
tr, tf
rise and fall times
CL = 30 pF; note 2
−
−
25
ns
δ
duty factor
CLKDIV = 0;
CL = 30 pF; note 2
45
−
55
%
CLKDIV = 1;
CL = 30 pF; note 2
40
−
60
%
DIP and SO packages
−
−0.1
−
%/C
∆δ/∆θ
1996 Dec 12
thermal drift on duty factor
14
Philips Semiconductors
Product specification
Smart card interface
SYMBOL
TDA8000; TDA8000T
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data lines [I/O1, I/O2, I/O1(µC), I/O2(µC)]; note 5
VOH
HIGH level output voltage on I/O
4.5 < VSUP < 5.5;
4.5 < VI/O(µC) < 5.5;
IOH = −20 µA
4
−
VCC + 0.2
V
4.5 < VSUP < 5.5;
4.5 < VI/O(µC) < 5.5;
IOH = −200 µA
2.4
−
−
V
VOL
LOW level output voltage on I/O
II/O = 1 mA;
I/O(µC) grounded
−
−
65
mV
IIL
LOW level input current on I/O(µC) I/O(µC) grounded;
II/O = 0
−
−
−500
µA
I/O(µC) grounded;
I/O connected to VCC
−
−
−5
mA
VOH
HIGH level output voltage on
I/O(µC)
4.5 < VI/O < 5.5
4
−
VSUP + 0.2
V
VOL
LOW level output voltage on
I/O(µC)
II/O(µC) = 1 mA;
I/O grounded
−
−
70
mV
IIL
LOW level input current on I/O
I/O grounded; II/O(µC) = 0
−
−
−500
µA
I/O grounded; I/O(µC)
connected to VSUP
−
−
−5
mA
VIDLE
voltage on I/O outside a session
−
−
0.4
V
ZIDLE
impedance on I/O(µC) outside a
session
10
−
−
MΩ
Rpu
internal pull-up resistance between
I/O and VCC
17
20
23
kΩ
tr, tf
rise and fall times
−
−
1
µs
Ci = Co = 30 pF
Protections
Tsd
shut-down local temperature
−
135
−
°C
ICC(sd)
shut-down current at VCC
−175
−
−230
mA
IPP(sd)
shut-down current at VPP
−90
−
−140
mA
II/O(sd)
shut-down current at I/O
from I/O to I/O(µC)
3
−
5
mA
tact
activation sequence duration
see Fig.6
250
−
500
µs
tde
deactivation sequence duration
see Fig.8
250
−
500
µs
t3
start of the window for sending
CLK to the card
see Fig.6
−
−
140
µs
Timing
1996 Dec 12
15
Philips Semiconductors
Product specification
Smart card interface
SYMBOL
TDA8000; TDA8000T
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
t5
end of the window for sending CLK see Fig.6
to the card
160
−
−
µs
tst
maximum pulse width on START
before VCC starts rising
−
−
30
µs
td(clk)
delay between RSTIN and CLK
−
−
2
µs
see Fig.6
Notes
1. START, WRITE, CLKDIV and PRES are active LOW; RSTIN and PRES are active HIGH.
t1
2. The transition time and duty factor definitions are shown in Fig.12; δ = --------------.
t1 + t2
3. P is the card programming voltage set by pins PSEL1 and PSEL2.
4. This condition ensures correct start-up of the oscillator with crystals having series resistance up to 100 Ω.
5. The path between I/O and I/O(µC) is as follows (see Fig.13):
a) Clamp to VCC.
b) 20 kΩ pull-up resistor to VCC; thus VOH on I/O.
c) Two opposite npn transistors with sensing pnp transistor.
d) Clamp to VSUP; thus VOH on I/O(µC).
e) The base current of the npn transistor is decreasing when their collector current increases. This means the
voltage drop is very low for small currents and becomes maximum for some mA. Thus VOL on I/O and I/O(µC),
current limits, and high impedance feature. The output current from I/O and I/O(µC) when the line is open-circuit
is the sum of the pull-up current and the base currents.
handbook, full pagewidth
tr
tf
VOH
90%
90%
1.5 V
10%
10%
VOL
t2
t1
Fig.12 Definition of transition times.
1996 Dec 12
16
MBH856
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
INTERNAL PIN CONFIGURATION
handbook, full pagewidth
VSUP
100
µA
XTAL
100
µA
VCC
100
µA
VCC
100
µA
20 kΩ
I/O1(µC)
100
µA
I/O2(µC)
5V
I/O2
as PSEL1
RSTIN
I/O1
VCC
VCC
RST
CLKOUT
5V
5 kΩ
100 Ω
20 kΩ
7 kΩ
1.5 V
TDA8000
VCC
VCC
CLK
CLKIN
VDD
400 µA
as PSEL1
10 k Ω
50 Ω
CLKDIV
CVNC
1350
Ω
as PSEL1
WRITE
as PSEL1
START
650
Ω
20
µA
OFF
1.25 V
PSEL1
ALARM
VSUP
VH
210
Ω
PSEL2
as PSEL1
PRES
as PSEL1
PRES
as PSEL1
2.5 V
2.5
µA
10 kΩ
DELAY
2.5 V
10 kΩ
2.5
kΩ
VH
VDD
ALARM
100
µA
VPP
GND
VSUP
VDD
625
Ω
250
Ω
20
µA
100
µA
20
µA
VSUP
VCC
1.25
kΩ
4690
Ω
1.25 V
1.25
kΩ
5310
Ω
MBE254
Fig.13 Internal pin configuration.
1996 Dec 12
17
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
APPLICATION INFORMATION
handbook, full pagewidth
12 V
5V
47 nF
22 µF
VCC
10 µF
VSUP
VDD
DELAY
GND
ALARM
RST
ALARM
VOLTAGE
SUPERVISOR
MAIN
SUPPLY
CVNC
100 nF
I/O1(µC)
CVNG
I/O1
I/O2(µC)
I/O2
PROTECTIONS
ENABLE
RSTIN
RST
PORT 1
PRES
TDA8000
PRES
LOGIC
OFF
PROTECTIONS
START
INT 1
VCC
GENERATOR
WRITE
INTERNAL
CLOCK
VCC
C1
C5
C2
C6
C3
C7
C4
C8
5.6 V
CLKDIV
80C51
MICROCONTROLLER
CLOCK
ENABLE
CLK
PSEL1
VPP
VPP
PSEL2
GENERATOR
CLOCK
CIRCUITRY
CLKOUT
CARD SOCKET
OSC
MGG825
VH
XTAL
1 kΩ
CLKIN
3.58 MHz
25 V
Fig.14 Typical application within a consumer product.
1996 Dec 12
18
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
12 V 25 V (1)
handbook, full pagewidth
100 nF
VDD
RST
ALARM ALARM VSUP CVNC VDD
INT1
SDA
OFF
SCL
START
PRES
WRITE
VCC
C1
RST
C2
CLK
C3
I/O1(µC)
PORT
COM
PRES
RSTIN
PORT
1
I2C
I/O2(µC)
TDA8000
PSEL1
12 V
10
µF
VH
C4
PSEL2
80C51
MICROCONTROLLER
CVNC
C5
CLKDIV
25 V
10
µF
XTAL1
CLKOUT
XTAL2
VPP
C6
I/O1
C7
I/O2
C8
GND
GND
DELAY
GND
CLKIN
CARD
SOCKET
XTAL
7.16 MHz
47 nF
MGG826
(1) If pin VH is not connected to 25 V, it should be connected to VDD.
Fig.15 Application in a remote card reader; the microcontroller is clocked and powered by the TDA8000 interface
is achieved via the I2C-bus.
1996 Dec 12
19
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
PACKAGE OUTLINES
seating plane
handbook, full
pagewidthdual in-line package; 28 leads (600 mil)
DIP28:
plastic
SOT117-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
15
28
pin 1 index
E
1
14
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.1
0.51
4.0
1.7
1.3
0.53
0.38
0.32
0.23
36.0
35.0
14.1
13.7
2.54
15.24
3.9
3.4
15.80
15.24
17.15
15.90
0.25
1.7
inches
0.20
0.020
0.16
0.066
0.051
0.020
0.014
0.013
0.009
1.41
1.34
0.56
0.54
0.10
0.60
0.15
0.13
0.62
0.60
0.68
0.63
0.01
0.067
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT117-1
051G05
MO-015AH
1996 Dec 12
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-01-14
20
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
HE
v M A
Z
15
28
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
14
e
bp
0
detail X
w M
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
inches
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.71
0.69
0.30
0.29
0.050
0.42
0.39
0.055
0.043
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
Z
(1)
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT136-1
075E06
MS-013AE
1996 Dec 12
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
91-08-13
95-01-24
21
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
SOLDERING
Plastic dual in-line packages
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Plastic small outline packages
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY WAVE
1996 Dec 12
22
Philips Semiconductors
Product specification
Smart card interface
TDA8000; TDA8000T
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Dec 12
23
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/04/pp24
Date of release: 1996 Dec 12
Document order number:
9397 750 01383