PD - 91721C IRFE9110 REPETITIVE AVALANCHE AND dv/dt RATED HEXFET TRANSISTORS SURFACE MOUNT (LCC-18) 100V, P-CHANNEL Product Summary Part Number IRFE9110 BVDSS -100V RDS(on) 1.2Ω ID -2.5A The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. Desinged to be a close replacement for the TO-39 package, the LCC will give designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference. LCC-18 Features: n n n n n n n n Surface Mount Small Footprint Alternative to TO-39 Package Hermetically Sealed Dynamic dv/dt Rating Avalanche Energy Rating Simple Drive Requirements Light Weight Absolute Maximum Ratings Parameter ID @ VGS = -10V, TC = 25°C ID @ VGS = -10V, TC = 100°C IDM PD @ TC = 25°C VGS EAS I AR EAR dv/dt TJ TSTG Units Continuous Drain Current Continuous Drain Current Pulsed Drain Current ➀ Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy ➁ Avalanche Current ➀ Repetitive Avalanche Energy ➀ Peak Diode Recovery dv/dt ➂ Operating Junction Storage Temperature Range -2.5 -1.6 -10 15 0.12 ±20 102 -14 -55 to 150 Pckg. Mounting Surface Temp. Weight 300 (for 5 S) 0.42(typical) A W W/°C V mJ A mJ V/ns o C g For footnotes refer to the last page www.irf.com 1 10/03/01 IRFE9110 Electrical Characteristics @ Tj = 25°C (Unless Otherwise Specified) Parameter Min Drain-to-Source Breakdown Voltage -100 Typ Max Units — — V — -0.08 — V/°C — — -2.0 0.9 — — — — — — — — 1.2 1.38 -4.0 — -25 -250 Ω VGS(th) gfs IDSS Temperature Coefficient of Breakdown Voltage Static Drain-to-Source On-State Resistance Gate Threshold Voltage Forward Transconductance Zero Gate Voltage Drain Current IGSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS + LD Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (‘Miller’) Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance — — — — — — — — — — — — — — — — — — — 6.1 -100 100 15 7.0 8.0 30 60 40 40 — Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance — — — 214 100 20 — — RDS(on) Test Conditions VGS = 0V, ID = -1.0mA Reference to 25°C, ID = -1.0mA nC VGS = -10V, ID = -1.6A➃ VGS = -10V, ID = -2.5A ➃ VDS = VGS, ID = -250µA VDS > -15V, IDS = -1.6A➃ VDS= -80V, VGS= 0V VDS =-80V VGS = 0V, TJ = 125°C VGS =-20V VGS =20V VGS =-10V, ID= -2.5A VDS =-50V ns VDD =-50V, ID = -2.5A, VGS =-10V, RG =7.5Ω V S( ) Ω BVDSS ∆BVDSS/∆TJ µA nA nH pF Measured from the center of drain pad to center of source pad VGS = 0V, VDS = -25V f = 1.0MHz Source-Drain Diode Ratings and Characteristics Parameter Min Typ Max Units IS ISM Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) ➀ — — — — -2.5 -10 A VSD t rr QRR Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge — — — — — — -5.5 200 380 V nS µc ton Forward Turn-On Time Test Conditions Tj = 25°C, IS = -2.5A, VGS = 0V ➃ Tj = 25°C, IF = -2.5A, di/dt ≤-100A/µs VDD ≤ -50V ➃ Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD. Thermal Resistance Parameter RthJC RthJ-PCB Junction to Case Junction to PC Board Min Typ Max Units — — — — 8.3 27 °C/W Test Conditions Soldered to a copper clad PC board For footnotes refer to the last page 2 www.irf.com IRFE9110 10 100 VGS TOP -15V -10V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V 1 -4.5V 20µs PULSE WIDTH T = 25 C 1 10 1 -4.5V 10 100 ° J 0.1 0.1 -VDS , Drain-to-Source Voltage (V) 1 10 100 -VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 10 2.5 TJ = 25 ° C TJ = 150 ° C 1 V DS = -50V 20µs PULSE WIDTH 0.1 4 5 6 7 8 9 -VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 10 R DS(on) , Drain-to-Source On Resistance (Normalized) -I D , Drain-to-Source Current (A) 20µs PULSE WIDTH T = 150 C ° J 0.1 0.1 VGS -15V -10V -8.0V -7.0V -6.0V -5.5V -5.0V BOTTOM -4.5V TOP -I D , Drain-to-Source Current (A) -I D , Drain-to-Source Current (A) 100 ID = -2.6A 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 V GS = -10V 0 20 40 60 80 100 120 140 160 TJ , Junction Temperature ( °C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRFE9110 C, Capacitance (pF) VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd 300 C iss 200 C oss 100 C rss 20 -VGS , Gate-to-Source Voltage (V) 400 ID = -2.5 A V DS = 80V V DS = 50V V DS = 20V 16 12 8 4 FOR TEST CIRCUIT SEE FIGURE 13 0 0 1 10 0 100 4 8 12 Q G , Total Gate Charge (nC) VDS , Drain-to-Source Voltage (V) Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 100 10 OPERATION IN THIS AREA LIMITED BY R TJ = 150 ° C 1 TJ = 25 ° C 0.1 0.0 V GS = 0 V 0.5 1.0 1.5 2.0 2.5 3.0 -VSD ,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 3.5 -II D , Drain Current (A) -ISD , Reverse Drain Current (A) DS(on) 10 100us 1ms 1 10ms 0.1 TC = 25 °C TJ = 150 °C Single Pulse 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRFE9110 3.0 RD V DS -ID , Drain Current (A) VGS D.U.T. RG - 2.0 + V DD VGS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % Fig 10a. Switching Time Test Circuit 1.0 td(on) tr t d(off) tf VGS 10% 0.0 25 50 75 100 125 150 TC , Case Temperature( ° C) 90% Fig 9. Maximum Drain Current Vs. Case Temperature VDS Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thJC ) Thermal Response (Z thJC ) 10 D = 0.50 D = 0.50 0.20 0.20 0.10 1 0.10 1 0.05 0.05 0.02 0.01 0.02 0.01 0.1 0.1 0.01 0.00001 0.01 0.00001 SINGLE PULSE (THERMAL RESPONSE) SINGLE PULSE (THERMAL RESPONSE) 0.0001 0.0001 P DM P DM t1 t1 0.001 t2 t2 Notes: 1. Notes: Duty factor D = t 1 / t 2 DutyTfactor D =xt 1Z/ thJC t 2 + TC 2.1.Peak J = P DM 2. Peak TJ = P DM x Z thJC + TC 0.01 0.1 0.01 (sec) 0.1 Duration 0.001 t1 , Rectangular Pulse t1 , Rectangular Pulse Duration (sec) 1 1 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFE9110 D .U .T RG VD D IA S -20V VGS tp -12V A D R IV E R 0.01 Ω 15V Fig 12a. Unclamped Inductive Test Circuit IAS EAS , Single Pulse Avalanche Energy (mJ) L VDS 300 TOP BOTTOM ID 1.1A 1.6A 2.5A 200 100 0 25 50 75 100 125 150 Starting TJ , Junction Temperature ( °C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current tp V (BR)DSS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG -12V 12V .2µF .3µF -10V -12V QGS QGD D.U.T. +VDS VGS VG -3mA Charge Fig 13a. Basic Gate Charge Waveform 6 IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRFE9110 Foot Notes: ➀ Repetitive Rating; Pulse width limited by maximum junction temperature. ➁ VDD =-25V, starting TJ = 25°C, Peak IL = -2.5A, VGS =- 10V ➂ ISD ≤ -2.5A, di/dt ≤− 285A/µs, VDD≤ -100V, TJ ≤ 150°C Suggested RG =7.5 Ω ➃ Pulse width ≤ 300 µs; Duty Cycle ≤ 2% Case Outline and Dimensions — LCC-18 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 10/01 www.irf.com 7