INTEGRATED CIRCUITS DATA SHEET TDA8002C IC card interface Product specification Supersedes data of 1999 Feb 24 File under Integrated Circuits, IC02 1999 Oct 12 Philips Semiconductors Product specification IC card interface TDA8002C FEATURES APPLICATIONS • Single supply voltage interface (3.3 or 5 V environment) IC card readers for: • Low-power sleep mode • GSM applications • Three specific protected half-duplex bidirectional buffered I/O lines • Banking • VCC regulation 5 V ±5% or 3 V ±5%, ICC < 55 mA for VDD = 3.0 to 6.5 V, with controlled rise and fall times • Identification • Electronic payment • Pay TV • Thermal and short-circuit protections with current limitations • Road tolling. • Automatic ISO 7816 activation and deactivation sequences GENERAL DESCRIPTION • Enhanced ESD protections on card side (>6 kV) The TDA8002C is a complete low-power analog interface for asynchronous and synchronous cards. It can be placed between the card and the microcontroller. It performs all supply, protection and control functions. It is directly compatible with ISO 7816, GSM11.11 and EMV specifications. • Clock generation for the card up to 12 MHz with synchronous frequency changes • Clock generation up to 20 MHz (external clock) • Synchronous and asynchronous cards (memory and smart cards) • ISO 7816, GSM11.11 compatibility and EMV (Europay, MasterCard and Visa) compliant • Step-up converter for VCC generation • Supply supervisor for spikes elimination and emergency deactivation • Chip select input for easy use of several TDA8002Cs in parallel. ORDERING INFORMATION PACKAGE TYPE NUMBER MARKING NAME DESCRIPTION VERSION TDA8002CT/A/C1 TDA8002CT/A SO28 TDA8002CT/B plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 TDA8002CT/B/C1 TDA8002CT/C/C1 TDA8002CT/C TDA8002CG/C1 TDA8002C plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1 1999 Oct 12 LQFP32 2 Philips Semiconductors Product specification IC card interface TDA8002C QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies 3.0 − 6.5 V low-power − − 150 µA Idle mode; fCLKOUT = 10 MHz − − 5 mA VDD supply voltage IDD(lp) supply current IDD(idle) supply current IDD(active) supply current active mode; VCC(O) = 5 V; fCLKOUT = 10 MHz fCLK = LOW; ICC = 100 µA − − 8 mA fCLK = 5 MHz; ICC = 10 mA − − 50 mA fCLK = 5 MHz; ICC = 55 mA − − 140 mA fCLK = LOW; ICC = 100 µA − − 8 mA fCLK = 5 MHz; ICC = 10 mA − − 50 mA fCLK = 5 MHz; ICC = 55 mA − − 140 mA ICC < 55 mA; DC load 4.6 − 5.4 V ICC = 40 nAs; AC load 4.6 − 5.4 V ICC < 55 mA; DC load 2.76 − 3.24 V ICC = 40 nAs; AC load 2.76 − 3.24 V active mode; VCC(O) = 3 V; fCLKOUT = 10 MHz Card supply VCC(O) output voltage active mode for VCC = 5 V active mode for VCC = 3 V General fCLK card clock frequency 0 − 12 MHz tde deactivation sequence duration 60 80 100 µs Ptot continuous total power dissipation Tamb 1999 Oct 12 TDA8002CT/x Tamb = −25 to +85 °C − − 0.56 W TDA8002CG Tamb = −25 to +85 °C − − 0.46 W −25 − +85 °C ambient temperature 3 Philips Semiconductors Product specification IC card interface TDA8002C BLOCK DIAGRAM VDDA VDDD handbook, full pagewidth 100 nF 100 nF 28 13 470 nF S1 S2 14 12 SUPPLY STEP-UP CONVERTER ALARM INTERNAL REFERENCE 4 Vref INTERNAL OSCILLATOR 2.5 MHz VOLTAGE SENSE 11 AGND 15 VUP 470 nF CS OFF EN1 3 26 EN2 ALARM RSTIN CMDVCC MODE CV/TV CLKDIV1 CLKDIV2 CLKSEL STROBE CLKOUT XTAL1 XTAL2 AUX1UC CLKUP PVCC 25 VCC VCC 23 GENERATOR 100 nF 24 EN5 27 19 6 RST BUFFER 22 CLOCK BUFFER 21 RST SEQUENCER LATCH EN4 7 5 8 CLOCK CIRCUITRY 18 CLK PRES 9 CLK EN3 30 31 THERMAL PROTECTION OSCILLATOR I/O TRANSCEIVER 20 2 I/O TRANSCEIVER 17 32 I/O TRANSCEIVER 16 1 AUX1 TDA8002CG AUX2UC I/OUC 10 29 DGND1 DGND2 FCE246 Fig.1 Block diagram. 1999 Oct 12 100 nF 4 AUX2 I/O Philips Semiconductors Product specification IC card interface TDA8002C PINNING PIN SYMBOL XTAL1 TYPE CT/A TYPE CT/B TYPE CT/C TYPE CG I/O DESCRIPTION 1 1 1 30 I crystal connection or input for external clock XTAL2 2 2 2 31 O crystal connection I/OUC 3 3 3 32 I/O data I/O line to and from microcontroller AUX1UC 4 4 4 1 I/O auxiliary line 1 to and from microcontroller for synchronous applications AUX2UC 5 − − 2 I/O auxiliary line 2 to and from microcontroller for synchronous applications CS − 5 5 3 I chip select control input for enabling pins I/OUC, AUX1UC, AUX2UC, CLKSEL, CLKDIV1, CLKDIV2, STROBE, CV/TV, CMDVCC, RSTIN, OFF and MODE; note 1 ALARM 6 6 6 4 O open drain PMOS reset output for microcontroller (active HIGH) CLKSEL 7 7 7 5 I control input signal for CLK (LOW = XTAL oscillator; HIGH = STROBE input) CLKDIV1 8 8 8 6 I control input with CLKDIV2 for choosing CLK frequency CLKDIV2 9 9 9 7 I control input with CLKDIV1 for choosing CLK frequency STROBE 10 10 10 8 I external clock input for synchronous applications CLKOUT 11 11 11 9 O clock output (see Table 1) DGND1 12 12 12 10 supply digital ground 1 AGND 13 13 13 11 supply analog ground S2 14 14 14 12 VDDA 15 15 15 13 S1 16 16 16 14 I/O capacitance connection for voltage doubler VUP 17 17 17 15 I/O output of voltage doubler I/O 18 18 18 16 I/O data I/O line to and from card AUX2 19 − − 17 I/O PRES 20 19 19 18 I card input presence contact (active LOW) PRES − 20 − − I active HIGH card input presence contact CV/TV − − 20 19 I card voltage selection input line (high = 5 V, low = 3 V); note 1 AUX1 21 21 21 20 I/O auxiliary I/O line to and from card CLK 22 22 22 21 O clock to card output (C3I) (see Table 1) RST 23 23 23 22 O card reset output (C2I) I/O capacitance connection for voltage doubler supply analog supply voltage auxiliary I/O line to and from card VCC 24 24 24 23 O supply for card (C1I) CMDVCC 25 25 25 24 I start activation sequence input from microcontroller (active LOW) RSTIN 26 26 26 25 I card reset input from microcontroller OFF 27 27 27 26 O open-drain NMOS interrupt output to microcontroller (active LOW) 1999 Oct 12 5 Philips Semiconductors Product specification IC card interface TDA8002C PIN SYMBOL TYPE CT/A TYPE CT/B TYPE CT/C TYPE CG I/O DESCRIPTION MODE 28 28 28 27 I operating mode selection input (HIGH = normal; LOW = sleep) VDDD − − − 28 supply digital supply voltage DGND2 − − − 29 supply digital ground 2 Note 1. A pull-up resistor of 100 kΩ connected to VDD is integrated. handbook, halfpage handbook, halfpage XTAL1 1 28 MODE XTAL1 1 28 MODE XTAL2 2 27 OFF XTAL2 2 27 OFF I/OUC 3 26 RSTIN I/OUC 3 26 RSTIN AUX1UC 4 25 CMDVCC AUX2UC 5 24 VCC CS 5 24 VCC ALARM 6 23 RST ALARM 6 23 RST 22 CLK CLKSEL 7 CLKSEL 7 25 CMDVCC AUX1UC 4 TDA8002CT/A 22 CLK TDA8002CT/B CLKDIV1 8 21 AUX1 CLKDIV1 8 21 AUX1 CLKDIV2 9 20 PRES CLKDIV2 9 20 PRES STROBE 10 19 AUX2 STROBE 10 19 PRES CLKOUT 11 18 I/O CLKOUT 11 18 I/O DGND1 12 17 VUP AGND 13 DGND1 12 16 S1 AGND 13 15 VDDA S2 14 16 S1 15 VDDA S2 14 FCE247 FCE248 Fig.2 Pin configuration (TDA8002CT/A). 1999 Oct 12 17 VUP Fig.3 Pin configuration (TDA8002CT/B). 6 Philips Semiconductors Product specification IC card interface TDA8002C handbook, halfpage XTAL1 1 28 MODE XTAL2 2 27 OFF I/OUC 3 26 RSTIN 25 CMDVCC AUX1UC 4 CS 5 24 VCC ALARM 6 23 RST CLKSEL 7 22 CLK TDA8002CT/C CLKDIV1 8 21 AUX1 CLKDIV2 9 20 CV/TV STROBE 10 19 PRES CLKOUT 11 18 I/O DGND1 12 17 VUP AGND 13 16 S1 15 VDDA S2 14 FCE249 25 RSTIN 26 OFF 27 MODE 28 VDDD 29 DGND2 30 XTAL1 32 I/OUC handbook, full pagewidth 31 XTAL2 Fig.4 Pin configuration (TDA8002CT/C). AUX1UC 1 24 CMDVCC AUX2UC 2 23 VCC CS 3 22 RST ALARM 4 21 CLK TDA8002CG 18 PRES STROBE 8 17 AUX2 CLKOUT I/O 16 7 VUP 15 CLKDIV2 S1 14 19 CV/TV VDDA 13 6 S2 12 CLKDIV1 AGND 11 20 AUX1 DGND1 10 5 9 CLKSEL Fig.5 Pin configuration (TDA8002CG). 1999 Oct 12 7 FCE250 Philips Semiconductors Product specification IC card interface TDA8002C FUNCTIONAL DESCRIPTION Clock circuitry Power supply The TDA8002C supports both synchronous and asynchronous cards. There are three methods to clock the circuitry: The supply pins for the chip are VDDA, VDDD, AGND, DGND1 and DGND2. VDDA and VDDD (i.e. VDD) should be in the range of 3.0 to 6.5 V. All card contacts remain inactive during power-up or power-down. • Apply a clock signal to pin STROBE • Use of an internal RC oscillator • Use of a quartz oscillator which should be connected between pins XTAL1 and XTAL2 or an external clock applied on XTAL1. On power-up, the logic is reset by an internal signal. The sequencer is not activated until VDD reaches Vth2 + Vhys2 (see Fig.6). When VDD falls below Vth2, an automatic deactivation sequence of the contacts is performed. When CLKSEL is HIGH, the clock should be applied to the STROBE pin. When CLKSEL is LOW, the internal oscillators is used. Chip selection When an internal clock is used, the clock output is available on pin CLKOUT. The RC oscillator is selected by making CLKDIV1 HIGH and CLKDIV2 LOW. The clock output to the card is available on pin CLK. The frequency of the card clock can be the input frequency divided by 2 or 4, STOP low or 1.25 MHz, depending on the states of CLKDIV1 or CLKDIV2 (see Table 1). The chip select pin (CS) allows the use of several TDA8002Cs in parallel. When CS is HIGH, the pins RSTN, CMDVCC, MODE, CV/TV, CLKDIV1, CLKDIV2, CLKSEL and STROBE control the chip, pins I/OUC, AUX1UC and AUX2UC are the copy of I/O, AUX1 and AUX2 when enabled (with integrated 20 kΩ pull-up resistors connected to VDD) and OFF is enabled. When STROBE is used for entering the clock to a synchronous card, STROBE should remain stable during activation sequence otherwise the first pulse may be omitted. When CS goes LOW, the levels on pins RSTIN, CMDVCC, MODE, CV/TV, CLKDIV1, CLKDIV2 and STROBE are internally latched, I/OUC, AUX1UC and AUX2UC go to high-impedance with respect to I/O, AUX1 and AUX2 (with integrated 100 kΩ pull-up resistors connected to VDD) and OFF is high-impedance. Do not change CLKSEL during activation. When in low-power (sleep) mode, the internal oscillator frequency which is available on pin CLKOUT is lowered to approximately 16 kHz for power economy purposes. Supply voltage supervisor (VDD) This block surveys the VDD supply. A defined retriggerable pulse of 10 ms minimum (tW) is delivered on the ALARM output during power-up or power-down of VDD (see Fig.6). This signal is also used for eliminating the spikes on card contacts during power-up or power-down. When VDD reaches Vth2 + Vhys2, an internal delay (tW) is started. The ALARM output is active until this delay has expired. When VDD falls below Vth2, ALARM is activated and a deactivation sequence of the contacts is performed. 1999 Oct 12 8 Philips Semiconductors Product specification IC card interface TDA8002C handbook, full pagewidth Vth2 + Vhys2 VDD Vth2 tW tW ALARM FCE272 Fig.6 ALARM as a function of VDD (tW pulse width minimum of 10 ms). handbook, full pagewidth CS OFF, I/OUC AUX1UC, AUX2UC t DZ t SL CS INPUTS FCE245 t IS t SI t ID Fig.7 Chip select. 1999 Oct 12 9 t DI Philips Semiconductors Product specification IC card interface Table 1 TDA8002C Clock circuitry definition MODE CLKSEL CLKDIV1 CLKDIV2 HIGH LOW HIGH LOW HIGH LOW LOW LOW HIGH LOW LOW HIGH LOW HIGH HIGH LOW(2) FREQUENCY OF FREQUENCY OF CLK CLKOUT 1⁄ f 2 int HIGH 1⁄ f 2 int 1⁄ f 4 xtal 1⁄ f 2 xtal HIGH STOP low fxtal HIGH X(1) X(1) STROBE X(1) X(1) X(1) fxtal fxtal fxtal 1⁄ STOP low 2fint (3) Notes 1. X = don’t care. 2. In low-power mode. 3. fint = 32 kHz in low-power mode. I/O circuitry In the event of a conflict, both lines may remain LOW until the software enables the lines to be HIGH. The anti-latch circuitry ensures that the lines do not remain LOW if both sides return HIGH, regardless of the prior conditions. The maximum frequency on the lines is approximately 200 kHz. The three I/O transceivers are identical. The state is HIGH for all I/O pins (i.e. I/O, I/OUC, AUX1, AUX1UC, AUX2 and AUX2UC). Pin I/O is referenced to VCC and pin I/OUC to VDD, thus ensuring proper operation in the event that VCC ≠ VDD. When CS is HIGH, I/OUC, AUX1UC and AUX2UC are internally pulled-up to VDD with 20 kΩ resistors. When CS is LOW, I/OUC, AUX1UC and AUX2UC are permanently HIGH (with integrated 100 kΩ pull-up resistors connected to VDD). The first side on which a falling edge is detected becomes a master (input). An anti-latch circuitry first disables the detection of the falling edge on the other side, which becomes slave (output), see Fig.8. After a delay time td (between 50 and 400 ns), the logic 0 present on the master side is transferred on the slave side. When the input is back to HIGH level, a current booster is turned on during the delay td on the output side and then both sides are back to their idle state, ready to detect the next logic 0 on any side. handbook, full pagewidth I/O I/OUC td td td conflict idle MGD703 Fig.8 Master and slave signals. 1999 Oct 12 10 Philips Semiconductors Product specification IC card interface TDA8002C If pin MODE goes LOW in the active mode, a normal deactivation sequence is performed before entering the low-power mode. When pin MODE goes HIGH, the circuit enters the normal operating mode after a delay of at least 6 ms (96 cycles of CLKOUT). During this time the CLKOUT remains at 16 kHz. Logic circuitry After power-up, the circuit has six possible states of operation. Figure 9 shows the state diagram. IDLE MODE After reset, the circuit enters the idle mode. A minimum number of functions in the circuit are active while waiting for the microcontroller to start a session: • All card contacts are inactive • Oscillator (XTAL) does not operate • The VDD supervisor, ALARM output, card presence detection and OFF output remain functional • All card contacts are inactive • I/OUC, AUX1UC and AUX2UC are high-impedance • Internal oscillator is slowed to 32 kHz, providing 16 kHz on CLKOUT. • Oscillator (XTAL) runs, delivering CLKOUT • Voltage supervisor is active. ACTIVE MODE LOW-POWER MODE When the activation sequence is completed, the TDA8002C will be in the active mode. Data is exchanged between the card and the microcontroller via the I/O lines. When pin MODE goes LOW, the circuit enters the low-power (sleep) mode. As long as pin MODE is LOW no activation is possible. handbook, full pagewidth ACTIVATION POWER OFF IDLE MODE FAULT ACTIVE MODE LOW-POWER MODE DEACTIVATION MGE735 Fig.9 State diagram. 1999 Oct 12 11 Philips Semiconductors Product specification IC card interface TDA8002C 2. VCC rises from 0 to 3 or 5 V (t2 = t1 + 11⁄2T) (according to the state on pin CV/TV) ACTIVATION SEQUENCE From Idle mode, the circuit enters the activation mode when the microcontroller sets the CMDVCC line LOW or sets the MODE line HIGH when the CMDVCC line is already LOW. The internal circuitry is then activated, the internal clock is activated and an activation sequence is executed. When RST is enabled it becomes the inverse of RSTIN. 3. I/O, AUX1 and AUX2 are enabled and CLK is enabled (t3 = t1 + 4T); I/O, AUX1 and AUX2 were forced LOW until this time 4. CLK is set by setting RSTIN to HIGH (t4) 5. RST is enabled (t5 = t1 + 7T); after t5, RSTIN has no further action on CLK, but is only controlling RST. Figures 10 to 12 illustrate the activation sequence as follows: The value of VCC (5 or 3 V) must be selected by the level on pin CV/TV before the activation sequence. 1. Step-up converter is started (t1 ≈ t0) handbook, full pagewidth OSC_INT/64 tact CMDVCC t0 VUP t1 VCC T = 25 µs t2 t3 I/O CLK t5 LOW t4 RSTIN RST FCE273 Fig.10 Activation sequence using RSTIN and CMDVCC. 1999 Oct 12 12 Philips Semiconductors Product specification IC card interface TDA8002C handbook, full pagewidth OSC_INT/64 tact CLKDIV1 CLKDIV2 CMDVCC t0 VUP t1 t2 VCC t3 I/O LOW CLK RSTIN RST FCE274 Fig.11 Activation sequence using CMDVCC, CLKDIV1 and CLKDIV2 signals to enable CLK. handbook, full pagewidth CMDVCC VCC I/O AUX1UC AUX1 RSTIN tact RST STROBE CLK FCE251 Fig.12 Activation sequence for synchronous application. 1999 Oct 12 13 Philips Semiconductors Product specification IC card interface TDA8002C 1. RST goes LOW (t11 ≈ t10) DEACTIVATION SEQUENCE 2. CLK is stopped (t12 = t11 + 1⁄2T) When a session is completed, the microcontroller sets the CMDVCC line to HIGH state or MODE line to LOW state. The circuit then executes an automatic deactivation sequence by counting the sequencer down and thus end in the Idle mode. 3. I/O, AUX1 and AUX2 fall to zero (t13 = t11 + T) 4. VCC falls to zero (t14 = t11 + 11⁄2T); a special circuit ensures that I/O remains below VCC during the falling slope of VCC Figures 13 and 14 illustrate the deactivation sequence as follows: 5. VUP falls (t15 = t11 + 5T). tde handbook, full pagewidth OSC_INT/64 CMDVCC t10 t15 VUP t14 VCC t13 I/O LOW t12 CLK RSTIN RST t11 FCE479 Fig.13 Deactivation sequence 1999 Oct 12 14 Philips Semiconductors Product specification IC card interface TDA8002C When one or more of these faults are detected, the circuit pulls the interrupt line OFF to its active LOW state and a deactivation sequence is initiated. In the event that the card is present the interrupt line OFF is set to HIGH state when the microcontroller has reset the CMDVCC line HIGH (after completion of the deactivation sequence). In the event that the card is not present OFF remains LOW. Fault detection The following fault conditions are monitored by the circuit: • Short-circuit or high current on VCC • Removing card during transaction • VDD dropping • Overheating. tde handbook, full pagewidth OSC_INT/64 OFF t10 PRES t14 VCC t13 I/O LOW t12 CLK RST t11 FCE480 Fig.14 Emergency deactivation sequence. 1999 Oct 12 15 Philips Semiconductors Product specification IC card interface TDA8002C LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); note 1. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage −0.3 +6.5 V VDDA analog supply voltage −0.3 +6.5 V VCC card supply voltage pins; XTAL1, XTAL2, ALARM, CS, MODE, RSTIN, CLKSEL, AUX2UC, AUX1UC, CLKDIV1, CLKDIV2, CLKOUT, STROBE, CMDVCC, CV/TV and OFF −0.3 +6.5 V Vi(card) input voltage on card contact pins; I/O, AUX2, PRES, PRES, AUX1, CLK, RST and VCC −0.3 +6.5 V Ves electrostatic handling voltage on pins I/O, AUX2, PRES, PRES, AUX1, CLK, RST and VCC −6 +6 kV on all other pins −2 +2 kV Tstg storage temperature −55 +125 °C Ptot continuous total power dissipation TDA8002CT/x Tamb = −25 to +85 °C − 0.56 W TDA8002CG Tamb = −25 to +85 °C − 0.46 W Tamb ambient temperature −25 +85 °C Tj junction temperature − 150 °C Note 1. Stress beyond these levels may cause permanent damage to the device. This is a stress rating only and functional operation of the device under this condition is not implied. HANDLING Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining. Method 3015 (HBM 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin with respect to ground. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1999 Oct 12 PARAMETER CONDITIONS VALUE UNIT SOT136-1 70 K/W SOT401-1 91 K/W thermal resistance from junction to ambient 16 in free air Philips Semiconductors Product specification IC card interface TDA8002C CHARACTERISTICS VDD = 3.3 V; Tamb = 25 °C; fxtal = 10 MHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies 3 − VDD supply voltage 6.5 V IDD(lp) supply current low-power mode − − 150 µA IDD(idle) supply current Idle mode; fCLKOUT = 10 MHz − − 5 mA IDD(active) supply current active mode; VCC(O) = 5 V; fCLKOUT = 10 MHz fCLK = LOW; ICC = 100 µA − − 8 mA fCLK = 5 MHz; ICC = 10 mA − − 50 mA fCLK = 5 MHz; ICC = 55 mA − − 140 mA active mode; VCC(O) = 3 V; fCLKOUT = 10 MHz fCLK = LOW; ICC = 100 µA − − 8 mA fCLK = 5 MHz; ICC = 10 mA − − 50 mA fCLK = 5 MHz; ICC = 55 mA − − 140 mA Vth2 threshold voltage on VDD for falling voltage supervisor 2.2 − 2.4 V Vhys2 hysteresis on Vth2 50 100 150 mV − − 0.3 V VCC = 5 V; ICC < 55 mA; DC load 4.6 − 5.4 V ICC = 40 nAs; AC load 4.6 − 5.4 V VCC = 3 V; ICC < 55 mA; DC load 2.76 − 3.24 V ICC = 24 nAs; AC load Card supply VCC(O) output voltage Idle mode active mode ICC(O) SR output current slew rate 2.76 − 3.24 V VCC(O) = from 0 to 5 or 3 V − − 55 mA VCC short-circuited to ground − 200 − mA rising or falling slope 0.10 0.15 0.20 V/µs Crystal connections (XTAL1 and XTAL2) Cext external capacitors note 1 − 15 − pF fxtal resonance frequency note 2 2 − 24 MHz 1999 Oct 12 17 Philips Semiconductors Product specification IC card interface SYMBOL PARAMETER TDA8002C CONDITIONS MIN. TYP. MAX. UNIT Data lines GENERAL td(edge) delay between falling edge of I/O, AUX1, AUX2, I/OUC, AUX1UC and AUX2UC tr, tf rise and fall times fI/O(max) maximum frequency on data lines − Ci = Co = 30 pF − 1 µs − − 0.5 µs − − 200 kHz DATA LINES I/O, AUX1 AND AUX2 (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VCC) Vo output voltage Idle and low-power modes 0 − 0.3 V VOH HIGH-level output voltage on data lines IOH = −20 µA 0.8VCC − VCC V VOL LOW-level output voltage on II/O = 1 mA data lines − − 0.4 V VIH HIGH-level input voltage on data lines 0.6VCC − VCC V VIL LOW-level input voltage on data lines 0 − 0.5 V Vidle voltage on data lines outside a session − − 0.4 V Rpu internal pull-up resistance between data lines and VCC 8 10 12 kΩ Iedge current from data lines when active pull-up is active − 1 − mA IIL LOW-level input current on data lines VIL = 0.4 V − − −600 µA IIH HIGH-level input current on data lines VIH = VCC − − 10 µA DATA LINES I/OUC, AUX1UC AND AUX2UC (WITH 20 KΩ PULL-UP RESISTOR CONNECTED TO VDD WHEN CS IS HIGH AND 100 KΩ WHEN CS IS LOW) VDD − 1 − VDD + 0.2 V LOW-level output voltage on II/OUC = 1 mA data lines − − 0.4 V VIH HIGH-level input voltage on data lines 0.7VDD − VDD V VIL LOW-level input voltage on data lines 0 − 0.3VDD V Zidle impedance on data lines outside a session 10 − − MΩ − − 5 µA VOH HIGH-level output voltage on data lines VOL IOH = −20 µA ALARM and OFF when connected (open-drain outputs) IOH(OFF) 1999 Oct 12 HIGH-level output current on pin OFF VOH(OFF) = 5 V 18 Philips Semiconductors Product specification IC card interface SYMBOL TDA8002C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VOL(OFF) LOW-level output voltage on IOL(OFF) = 2 mA pin OFF − − 0.4 V IOL(ALARM) LOW-level output current on VOL(ALARM) = 0 V pin ALARM − − −5 µA VOH(ALARM) HIGH-level output voltage on pin ALARM VDD − 1 − − V tW ALARM pulse width 6 − 20 ms 0 − 20 MHz − 16 − kHz − IOH(ALARM) = −2 mA Clock output (CLKOUT; powered from VDD) fCLKOUT frequency on CLKOUT low power VOL LOW-level output voltage IOL = 1 mA 0 0.5 V VOH HIGH-level output voltage IOH = −1 mA VDD − 0.5 − − V tr, tf rise and fall times CL = 15 pF; notes 3 and 4 − − 8 ns δ duty factor CL = 15 pF; notes 3 and 4 40 − 60 % active mode 2 2.5 3 MHz sleep mode − 32 − kHz Internal oscillator fint frequency of internal oscillator Card reset output (RST) VO(inact) output voltage inactive modes 0 − 0.3 V td(RST) delay between RSTIN and RST RST enabled − − 100 ns VOL LOW-level output voltage IOL = 200 µA 0 − 0.3 V VOH HIGH-level output voltage IOH = −200 µA VCC − 0.5 − VCC V tr, tf rise and fall times CL = 30 pF − 0.5 ns − Card clock output (CLK) VO(inact) output voltage inactive modes 0 − 0.3 V VOL LOW-level output voltage IOL = 200 µA 0 − 0.3 V VOH HIGH-level output voltage IOH = −50 µA VCC − 0.5 − VCC V tr, tf rise and fall times CL = 30 pF; note 3 − − 8 ns δ duty factor CL = 30 pF; note 3 45 − 55 % SR slew rate (rise and fall) 0.2 − − V/ns Strobe input (STROBE) fSTROBE frequency on STROBE 0 − 10 MHz VIL LOW-level input voltage 0 − 0.3VDD V VIH HIGH-level input voltage 0.7VDD − VDD V Logic inputs (CLKSEL, CLKDIV1, CLKDIV2, MODE, CMDVCC and RSTIN); note 5 VIL LOW-level input voltage 0 − 0.3VDD V VIH HIGH-level input voltage 0.7VDD − VDD V 1999 Oct 12 19 Philips Semiconductors Product specification IC card interface SYMBOL PARAMETER TDA8002C CONDITIONS MIN. TYP. MAX. UNIT LOGIC INPUTS (CV/TV AND CS) (INTEGRATED 10 KΩ PULL-UP RESISTOR CONNECTED TO VDD); note 5 VIL LOW-level input voltage 0 − 0.3VDD V VIH HIGH-level input voltage 0.7VDD − VDD V Logic inputs PRES and PRES; note 5 VIL LOW-level input voltage 0 − 0.3VDD V VIH HIGH-level input voltage 0.7VDD − VDD V IIL(PRES) LOW-level input current on pin PRES − − −10 µA IIH(PRES) HIGH-level input current on pin PRES − − 10 µA Tsd shut-down local temperature − 135 − °C ICC(sd) shut-down current at VCC − − 90 mA VOL = 0 V Protections Timing tact activation sequence duration guaranteed by design; see Fig.12 − 180 220 µs tde deactivation sequence duration guaranteed by design; see Fig.14 50 70 100 µs t3 start of the window for sending CLK to the card see Figs 10 and 11 − − 130 µs t5 end of the window for sending CLK to the card see Fig.11 150 − − µs tIS time from input to select 100 − − ns tSI time from select to input 1000 − − ns tID time from input to deselect 1000 − − ns tDI time from deselect to input 100 − − ns tSL time from select to low impedance − − 40 ns tDZ time from deselect to high impedance pull-up resistor at pin OFF = 10 kΩ; 1 device − − 6 ns 2 devices in parallel − − 3 ns tr(max) maximum rise time on pin CS − − 100 ns tf(max) maximum fall time on pin CS − − 100 ns 1999 Oct 12 20 Philips Semiconductors Product specification IC card interface TDA8002C Notes 1. It may be necessary to connect capacitors from XTAL1 and XTAL2 to ground depending on the choice of crystal or resonator. 2. When the oscillator is stopped in mode 1, XTAL1 is set to HIGH. t1 3. The transition time and duty cycle definitions are shown in Fig.15; δ = -------------t1 + t2 4. CLKOUT transition time and duty cycle do not need to be tested. 5. PRES and CMDVCC are active LOW; RSTIN, PRES and CS are active HIGH. handbook, full pagewidth tr tf 90% 90% VOH 1/2 VCC 10% 10% VOL t1 t2 Fig.15 Definition of transition times. 1999 Oct 12 21 MGE741 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ground VDD C2 10 µF P1-0 J1 2 33 pF P1-1 33 pF P1-2 22 C4 C8 C3 C7 C2 C6 C1 C5 C5I C1I C6I C2I C7I C3I C8I C4I MODE OFF RSTIN C3(2) 100 nF CMDVCC VCC RST CLK AUX1 CV/TV PRES CARD READ I/O (1) K1 VUP K2 S1 C6(5) 470 nF C4(3) 100 nF VDDA C5(4) 470 nF 28 1 27 2 26 3 25 4 24 5 23 6 22 21 20 IC1 TDA8002CT/C 7 8 9 19 10 18 11 17 12 16 13 15 14 XTAL1 XTAL2 P1-3 14.745 MHz P1-4 P1-5 I/OUC P1-6 AUX1UC P1-7 CS RST ALARM P3-0 CLKSEL P3-1 CLKDIV1 P3-2 CLKDIV2 P3-3 STROBE P3-4 CLKOUT 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 11 IC2 80C51 C8 10 µF 29 13 28 26 16 25 17 24 18 XTAL1 19 VSS 20 23 VDD Fig.16 Application diagram. 21 P0-0 P0-1 P0-2 P0-3 P0-4 P0-5 P0-6 P0-7 EA ALE PSEN P2-7 P2-6 P2-5 P2-4 P2-3 P2-2 P2-1 P2-0 FCE195 Product specification CLK line may be shielded with respect to other lines. Decoupling capacitors C7 and C8 may be placed as close as possible to pin VDDA. A good ground plane is recommended. 22 VCC TDA8002C TDA8002C should be placed as close as possible to the card reader. (1) Contact normally open. (2) C3 close to pin VCC of TDA8002C. (3) C4 close to C1 contact of card reader. (4) C5 close to VUP pin of TDA8002C. (5) C6 as close as possible to pins S1 and S2. 30 12 XTAL2 C7 100 nF 31 27 P3-7 S2 2 15 P3-6 AGND 40 14 P3-5 DGND1 1 Philips Semiconductors C1 100 nF IC card interface 3.3 V or 5 V J1 1 APPLICATION INFORMATION ull pagewidth 1999 Oct 12 VDD This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... C1 100 nF P1-0 J1 2 33 pF C9 C7I C3I C8I C4I CLK AUX1 CV/TV CARD READ PRES AUX2 (1) K1 I/OUC XTAL2 P1-5 25 26 27 28 29 30 31 32 1 23 2 3 22 21 IC1 4 20 TDA8002CG 5 19 6 18 7 17 8 P1-6 AUX1UC P1-7 AUX2UC RST CS P3-0 ALARM P3-1 CLKSEL P3-2 CLKDIV1 P3-3 CLKDIV2 P3-4 STROBE P3-5 16 15 14 13 12 11 10 9 K2 C6(5) 470 nF C4(3) 100 nF P3-7 XTAL2 XTAL1 VSS C7 100 nF C8 10 µF 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 IC2 31 11 80C51 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 VCC P0-0 P0-1 P0-2 P0-3 P0-4 P0-5 P0-6 P0-7 EA ALE PSEN P2-7 P2-6 P2-5 P2-4 P2-3 P2-2 P2-1 P2-0 FCE196 VDD Fig.17 Application diagram (for more details, see “Application note AN98054” ). Product specification CLK line may be shielded with respect to other lines. Decoupling capacitors C7, C8 and C9 may be placed as close as possible to pin VDDA and VDDD. A good ground plane is recommended. TDA8002C TDA8002C should be placed as close as possible to the card reader. (1) Contact normally open. (2) C3 close to pin VCC of TDA8002C. (3) C4 close to C1 contact of card reader. (4) C5 close to VUP pin of TDA8002C. (5) C6 as close as possible to pins S1 and S2. C5(4) 470 nF P3-6 CLKOUT C2I P1-3 P1-4 24 I/O 23 C6I RST XTAL1 C1I CMDVCC VCC DGND1 C5I C3(2) 100 nF DGND2 C5 S2 C1 P1-2 AGND C6 MODE VDDD C2 OFF C7 S1 C3 100 nF RSTIN C8 P1-1 14.745 MHz VUP C4 33 pF VDD VDDA ground VDD C2 10 µF Philips Semiconductors 3.3 V or 5 V J1 1 IC card interface book, full pagewidth 1999 Oct 12 VDD Philips Semiconductors Product specification IC card interface TDA8002C PACKAGE OUTLINES SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e w M bp 0 detail X 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013AE 1999 Oct 12 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 24 Philips Semiconductors Product specification IC card interface TDA8002C SOT401-1 LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm c y X A 17 24 ZE 16 25 e A A2 E HE (A 3) A1 w M pin 1 index θ bp 32 Lp 9 L 1 8 detail X ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 5.1 4.9 0.5 7.15 6.85 7.15 6.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 97-08-04 SOT401-1 1999 Oct 12 EUROPEAN PROJECTION 25 Philips Semiconductors Product specification IC card interface TDA8002C • For packages with leads on two sides and a pitch (e): SOLDERING – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 1999 Oct 12 26 Philips Semiconductors Product specification IC card interface TDA8002C Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Oct 12 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/25/03/pp28 Date of release: 1999 Oct 12 Document order number: 9397 750 06149