INTEGRATED CIRCUITS DATA SHEET TDA8586 Power amplifier with load detection and auto BTL/SE selection Preliminary specification Supersedes data of 1998 May 25 File under Integrated Circuits, IC01 1999 Apr 08 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 FEATURES GENERAL DESCRIPTION General The IC incorporates the following functions: 1. 4 × 6 W SE amplifies without SE capacitor, because of the availability of 2 half supply voltage power buffers • Operating voltage from 8 to 18 V • Low distortion 2. 2 × 20 W BTL amplifiers • Few external components, fixed gain 3. Automatic switching between 2 and 4 speaker operation. The mode of operation is determined during start-up. • Automatic mode selection (SE or BTL) depending on connected ‘rear’ loads • Can be used as a stereo amplifier in Bridge-Tied Load (BTL) or quad Single-Ended (SE) amplifiers This amplifier is protected for all general short-circuit conditions to battery or ground, overvoltage, 45 V load dump and short-circuits on the speaker outputs. • Single-ended mode without loudspeaker capacitor • Soft clipping, to guarantee good clip behaviour with inductive loads The IC is contained in a 20-pin power HSOP package, but is also available in a 17-pin SIL power package. When packaged in the 20-pin HSOP package additional functions are available: 1. DDD level selection between 2 and 10% • Mute and standby mode with one-pin operation • Diagnostic information for Dynamic Distortion Detector (DDD), high temperature (140 °C) mode of operation and short-circuit 2. Overrule pin for changing mode of operation (from SE to BTL or from BTL to SE). • No switch-on/off plops when switching between standby and mute and from mute to on • Load detection on ‘rear’ channels when switching from standby to mute • Fast mute on supply voltage drops (low VP mute). Protection • Short-circuit proof to ground, positive supply voltage on all pins and across load • ESD protected on all pins • Thermal protection against temperatures exceeding 150 °C • Load dump protection • Overvoltage protection. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA8586Q DBS17P plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) SOT243-1 TDA8586TH HSOP20 heatsink small outline package; 20 leads; low stand-off SOT418-2 1999 Apr 08 2 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP operating supply voltage 8.0 − 18 V Iq(tot) total quiescent current VP = 14.4 V, SE mode − 140 170 mA Istb standby supply current VP = 14.4 V − 1 100 µA Gv voltage gain SE mode 25 26 27 dB BTL mode 31 32 33 dB THD = 0.5% 14 15 − W THD = 10% 17 21 − W Bridge-tied load application Po output power VP = 14.4 V; RL = 4 Ω THD total harmonic distortion fi = 1 kHz; Po = 1 W; VP = 14.4 V; RL = 4 Ω − 0.05 0.15 % VOO DC output offset voltage VP = 14.4 V; RL = 4 Ω; mute condition − 10 20 mV VP = 14.4 V; on condition − 0 100 mV Rs = 1 kΩ; VP = 14.4 V − 100 200 µV THD = 0.5% 4 4.5 − W THD = 10% Vn(o) noise output voltage Single-ended application Po output power VP = 14.4 V; RL = 4 Ω 5 6 − W THD total harmonic distortion fi = 1 kHz; Po = 1 W; VP = 14.4 V; RL = 4 Ω − 0.08 0.15 % VOO DC output offset voltage VP = 14.4 V; RL = 4 Ω; mute condition − 10 20 mV VP = 14.4 V; on condition − 0 100 mV Rs = 1 kΩ; VP = 14.4 V − 80 150 µV Vn(o) 1999 Apr 08 noise output voltage 3 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 BLOCK DIAGRAM VP1 handbook, full pagewidth VP2 16 2 IN1 5 − 60 kΩ − V/I + OA 1 OUT1 + + 60 kΩ TDA8586Q − V/I − VPn OA 3 HVP1 + IN2 + 6 + 60 kΩ IN3 7 V/I − V/I − 4 OUT2 − − 60 kΩ ACREF OA + OA 17 OUT3 + 11 + VPn 60 kΩ 30 kΩ − V/I − VPn OA 15 HVP2 + BUFFER IN4 + 8 + 60 kΩ MSO 13 OA 14 − INTERFACE DIAGNOSTIC 10 12 9 MGR023 PGND2 PGND1 Fig.1 Block diagram SOT243-1. 1999 Apr 08 OUT4 − V/I 4 DIAG Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection handbook, full pagewidth IN1 TDA8586 VP1 VP2 18 13 2 − 60 kΩ − V/I + 17 OA OUT1 + + 60 kΩ TDA8586TH n.c. 1 − V/I − VPn 19 OA HVP1 + IN2 + 3 + 60 kΩ IN3 4 V/I − V/I − OUT2 − − 60 kΩ ACREF 20 OA + 14 OA OUT3 + 6 + VPn 60 kΩ 30 kΩ − V/I − VPn 12 OA HVP2 + BUFFER IN4 + 5 + 60 kΩ MSO 8 V/I − 7 DIAGNOSTIC 9 15 16 PGND2 PGND1 MGR024 DDDSEL OVERRULE Fig.2 Block diagram SOT418-2 (HSOP20 heatsink up). 1999 Apr 08 OUT4 − INTERFACE 10 11 OA 5 DIAG Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 PINNING PIN SOT243 PIN SOT418 n.c. − 1 not connected IN1 5 2 non-inverting input 1 IN2 6 3 inverting input 2 IN3 7 4 non inverting input 3 IN4 8 5 inverting input 4 ACREF 11 6 common signal input DIAG 12 7 diagnostic output/mode fix MSO 13 8 mode select mute, standby or on OVERRULE − 9 mode selection overrule DDDSEL − 10 2 or 10% dynamic distortion detection SYMBOL DESCRIPTION OUT4 14 11 SE output 4 (negative) HVP2 15 12 buffer output/BTL output 2 (negative) VP2 16 13 supply voltage 2 OUT3 17 14 SE output 3/BTL output 2 (positive) PGND2 10 15 power ground 2 PGND1 9 16 power ground 1 OUT1 1 17 SE output 1/BTL output 1 (positive) VP1 2 18 supply voltage 1 HVP1 3 19 buffer output/BTL output 1 (negative) OUT2 4 20 SE output 2 (negative) 1999 Apr 08 6 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 handbook, halfpage OUT1 1 VP1 2 HVP1 3 OUT2 4 n.c. 1 20 OUT2 IN1 5 IN1 2 19 HVP1 IN2 6 IN2 3 18 VP1 IN3 7 IN3 4 17 OUT1 IN4 8 IN4 5 PGND1 9 handbook, halfpage 16 PGND1 TDA8586TH TDA8586Q 15 PGND2 ACREF 6 PGND2 10 DIAG 7 14 OUT3 ACREF 11 MSO 8 13 VP2 DIAG 12 OVERRULE 9 12 HVP2 MSO 13 DDDSEL 10 11 OUT4 OUT4 14 MGR026 HVP2 15 VP2 16 OUT3 17 MGR025 Fig.3 Pin configuration (SOT243-1). 1999 Apr 08 Fig.4 Pin configuration (SOT418-2). 7 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection The presence of the load is measured after the transition between standby and mute. The IC will determine if there is an acceptable load on both outputs (OUT2 and OUT4). If both outputs are unloaded, the IC will switch to a 2 speaker mode of operation (BTL mode), unless it is overruled. FUNCTIONAL DESCRIPTION The TDA8586 is a multi-purpose power amplifier with four amplifiers and 2 buffer stages, which can be connected in the following configurations with high output power and low distortion: • Dual Bridge-Tied Load (BTL) amplifiers There are two options to overrule: 1. Before transition from mute to on, after a load detection, pulling the diagnostic output above 9.5 V will force the IC into 4 speaker mode • Quad Single-Ended (SE) amplifiers. In the BTL mode of operation, the 2 buffer amplifiers act as inverting amplifiers to complete the bridge across the ‘front’ amplifiers (OUT1 and OUT3) and the ‘rear’ outputs (OUT2 and OUT4) enter a high-impedance state. 2. TDA8586TH: pulling the OVERRULE pin according pinning table. In the SE mode of operation, the buffers act as an AC ground path thereby eliminating the need for series capacitors on the speaker outputs. Care should be taken with the OVERRULE function as it works during the on mode. If there is a 2 or 4 speaker mode change during the on mode a large ‘plop’ can be heard on the speakers. Diagnostics: • While the IC is in the mute mode, the diagnostic output will signal the mode of operation when the IC is not overruled The ACREF input (common signal input) acts with the four signal inputs (IN1 to IN4) to provide quasi differential inputs. A capacitor must be connected to this pin of which the ground pin should be connected to the ground at the signal source (usually the ground at the audio signal processor). This capacitor has a dual function. During the speaker detection, the signal ground capacitor is used to set the time constant of the measurement (and thus determines the minimum required switch-on time). The capacitor on the MSO pin allows the integrate function to provide immunity to outside noises during load detection. • In the on mode the diagnostic output will signal any fault in the IC or if the output of any amplifier is clipping with a distortion of 10% (or 2% depending on selected clip-mode). Special attention is given to the dynamic behaviour as follows: • Noise suppression during engine start • No plops when switching from standby to on • Slow offset change between mute and on (controlled by MSO pin) • Low noise levels, which are independent of the supply voltage. Protections are included to avoid the IC being damaged at: • Over temperature: Tj > 150 °C • Short-circuit of the output pin(s) to ground or supply rail. When short-circuited, the power dissipation is limited • ESD protection (Human Body Model 3000 V and Machine Model 300 V). 1999 Apr 08 TDA8586 8 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection handbook, full pagewidth state condition standby mute load detect mute no load detect TDA8586 on no clipping/shorts on clipping on short-circuit VP VP 0 minimum 1 s 9V MSO 3V SE detection BTL detection 0 5V diagnostic information BTL detected SE detected 0 10 V diagnostic overrule The mode is overruled only from BTL to SE when the diagnostic pin is excited with a pulse of 10 V. 0 5V mode select This voltage must remain present. Whatever the load detection has found the mode of operation will be inverted. Toggling between the 2 modes is possible. 0 short-circuit to supply amplifier output short-circuit over load 0.5VP short-circuit to ground 0 short-circuit to supply short-circuit over load 0.5VP buffer/amplifier output 0 short-circuit to ground MGR027 Fig.5 Timing diagram including diagnostics. 1999 Apr 08 9 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP PARAMETER CONDITIONS supply voltage MIN. MAX. UNIT operating 8 18 V load dump protected; see Fig.6 − 45 V VDIAG voltage on diagnostic pin − 18 V IOSM non-repetitive peak output current − 6 A IORM repetitive peak output current − 4 A Vrp reverse polarity voltage − 6 V Vsc AC and DC short-circuit voltage of output pins across loads and to ground or supply pins − 18 V Ptot total power dissipation − 75 W Tj junction temperature − 150 °C Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −40 +150 °C note 1 Note 1. A large reverse current will flow, therefore external protection is needed (fuse and reverse diode). MGL404 handbook, halfpage 45 V VP 14.4 V t (ms) tf tr Fig.6 Load dump voltage waveform. THERMAL CHARACTERISTICS SYMBOL PARAMETER Rth(j-a) thermal resistance from junction to ambient Rth(j-c) thermal resistance from junction to case 1999 Apr 08 CONDITIONS in free air 10 VALUE UNIT 40 K/W 2 K/W Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 CHARACTERISTICS VP = 14.4 V; Tamb = 25 °C; fi = 1 kHz; RL = ∞; measured in test circuit of Fig.8; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VP operating supply voltage Iq(tot) total quiescent current Istb standby current VO DC output voltage VP(mute) low supply voltage mute Vo single-ended and bridge-tied load output voltage VI 8.0 14.4 18 V − 140 170 mA − 1 100 µA − 7.0 − V 6.0 7.0 8.0 V mute condition − − 20 mV on condition − − 100 mV SE mode VP = 14.4 V VP = 14.4 V; RL = 4 Ω DC input voltage VP = 14.4 V − 4.0 − V voltage at pin MSO standby condition 0 − 0.8 V mute condition; note 1 2.0 3.0 4 V on condition 8.0 − 10.5 V mute pin at standby condition; VMSO < 0.8 V − 5 40 µA PIN MSO VMSO IMSO input current Diagnostic; output buffer (open-collector); see Figs 7 to 8 VDIAG(L) diagnostic output voltage LOW Isink = 1 mA − 0.3 0.8 V ILI leakage current VDIAG = 14.4 V − − 1 µA VDIAG(or) diagnostic override voltage in mute mode after load detection 10.5 − 18 V VDIAG(4ch) diagnostic 4 channel indication mute, after load detection with voltage 4 speakers connected − 0.3 0.8 V CD2 clip detector LOW THD mode; VDIAG > 3 V; R = 10 kΩ 0.5 2 3.5 % CD10 clip detector HIGH THD mode (default); VDIAG > 3 V; R = 10 kΩ 7 10 13 % CLIP DETECT CONTROL PIN VDDDSEL voltage at DDD select pin to obtain: 10% DDD 0 − 1 V 2% DDD 3 − 6 V IDDDSEL Input current DDD select pin VDDDSEL = 5 V 15 − 140 µA 1999 Apr 08 11 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection SYMBOL PARAMETER TDA8586 CONDITIONS MIN. TYP. MAX. UNIT Stereo BTL application (see Fig.7) THD Po total harmonic distortion output power fi = 1 kHz; Po = 1 W; RL = 4 Ω − 0.05 0.15 % 45 Hz < fi < 10 kHz; Po = 1 W; RL = 4 Ω; filter: f < 30 kHz − 0.3 − % THD = 0.5% 14 15 − W THD = 10% 17 21 − W 31 32 33 dB VP = 14.4 V; RL = 4 Ω; note 2 Gv voltage gain Vi(rms) = 15 mV ∆Gv channel unbalance Vi(rms) = 15 mV −0.7 0 +0.7 dB αcs channel separation Po = 2 W; fi = 1 kHz; RL = 4 Ω 45 55 − dB VOO DC output offset voltage VP = 14.4 V; on condition − 0 100 mV VP = 14.4 V; RL = 4 Ω; mute condition − 10 20 mV Vn(o) noise output voltage on Rs = 1 kΩ; VP = 14.4 V; note 3 − 100 150 µV Vn(o)(mute) noise output voltage mute note 3 − 0 20 µV Vo(mute) output voltage mute Vi(rms) = 1 V − 3 500 µV SVRR supply voltage ripple rejection: Rs = 0 Ω; fi = 1 kHz; Vripple = 2 V (p-p) on condition 45 55 − dB mute condition 55 70 − dB 40 60 90 kΩ Zi 1999 Apr 08 input impedance input referenced to ground 12 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection SYMBOL PARAMETER TDA8586 CONDITIONS MIN. TYP. MAX. UNIT Quad SE application (see Fig.8) THD Po total harmonic distortion output power fi = 1 kHz; Po = 1 W; RL = 4 Ω − 0.05 0.15 % 45 Hz < fi < 10 kHz; Po = 1 W; RL = 4 Ω; filter: f < 30 kHz − 0.5 − % THD = 0.5% 4 4.5 − W THD = 10% 5 6 − W 25 26 27 dB VP = 14.4 V; RL = 4 Ω; note 2 Gv voltage gain Vi(rms) = 15 mV ∆Gv channel unbalance Vi(rms) = 15 mV −0.7 0 +0.7 dB αcs channel separation Po = 2 W; fi = 1 kHz; RL = 4 Ω 40 50 − dB VOO DC output offset voltage VP = 14.4 V; on condition − 0 100 mV VP = 14.4 V; RL = 4 Ω; mute condition − 10 20 mV Vn(o) noise output voltage on Rs = 1 kΩ; VP = 14.4 V; note 3 − 80 150 µV Vn(o)(mute) noise output voltage mute note 3 − 0 20 µV Vo(mute) output voltage mute Vi(rms) = 1 V − 3 500 µV SVRR supply voltage ripple rejection Rs = 0 Ω; fi = 1 kHz; Vripple = 2 V (p-p) on condition 43 47 − dB mute condition 55 70 − dB Notes 1. Tolerances on the mute level is tight because of the usage of this pin for integration during load detection. 2. The output power is measured directly on the pins of the IC. 3. The noise output is measured in a bandwidth of 20 Hz to 20 kHz. 1999 Apr 08 13 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 APPLICATION INFORMATION handbook, full pagewidth 1000 µF (16/40 V) 220 nF VP1 VP2 2 16 IN1 5 100 nF VP − 60 kΩ VINL front − V/I + OA 1 OUT1 + + + 60 kΩ TDA8586Q − − V/I − VPn OA 4 or 8 Ω 3 HVP1 + 220 nF + IN2 6 + 60 kΩ 220 nF IN3 7 OA V/I − V/I − 4 OUT2 − − 60 kΩ VINR front + OA 17 OUT3 + ACREF 11 47 µF (10 V) + − + VPn 60 kΩ 30 kΩ − V/I − VPn OA 4 or 8 Ω 15 HVP2 + BUFFER 220 nF + IN4 8 + 60 kΩ switched +9 V OA 14 OUT4 − V/I − +5 V 10 kΩ 30 kΩ MSO 13 INTERFACE DIAGNOSTIC 12 DIAG 15 kΩ switch 4.7 µF (10 V) 10 9 PGND2 PGND1 Fig.7 Stereo bridge-tied load application (SOT243-1). 1999 Apr 08 14 MGR028 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 handbook, full pagewidth 1000 µF (16/40 V) 220 nF VP1 VP2 2 16 IN1 5 100 nF VP − 60 kΩ VINL front − V/I + OA 1 OUT1 + + + 60 kΩ TDA8586Q − − V/I − VPn OA 3 HVP1 + 220 nF + 60 kΩ VINL rear 220 nF + − + IN2 6 IN3 7 OA V/I − V/I − VINR front 4 OUT2 − + OA 17 OUT3 + ACREF 11 47 µF (10 V) + − + VPn 60 kΩ 30 kΩ − V/I − VPn OA + + + 60 kΩ VINR rear switched +9 V OA 14 OUT4 − V/I − +5 V 4.7 µF (10 V) INTERFACE DIAGNOSTIC 10 9 PGND2 PGND1 Fig.8 Quad single-ended application (SOT243-1). 1999 Apr 08 4 or 8 Ω 10 kΩ MSO 13 15 kΩ switch − + IN4 8 4 or 8 Ω 15 HVP2 BUFFER 30 kΩ 4 or 8 Ω − 60 kΩ 220 nF 4 or 8 Ω 15 12 DIAG MGR029 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 handbook, full pagewidth 1000 µF (16/40 V) 220 nF VP1 VP2 18 13 IN1 2 100 nF VP − 60 kΩ VINL front − V/I + OA 17 OUT1 + + + 60 kΩ TDA8586TH n.c. 1 − − V/I − VPn OA 4 or 8 Ω 19 HVP1 + 220 nF + IN2 3 + 60 kΩ 220 nF IN3 4 OA V/I − V/I − 20 OUT2 − − 60 kΩ VINR front + OA 14 OUT3 + ACREF 6 47 µF (10 V) + − + VPn 60 kΩ 30 kΩ − V/I − VPn OA 4 or 8 Ω 12 HVP2 + BUFFER 220 nF + IN4 5 + 60 kΩ switched +9 V OA 11 OUT4 − V/I − +5 V 10 kΩ 30 kΩ MSO 8 INTERFACE DIAGNOSTIC 7 DIAG 15 kΩ switch 4.7 µF (10 V) 10 9 15 16 DDDSEL OVERRULE PGND2 PGND1 Fig.9 Stereo bridge-tied load application (SOT418-2). 1999 Apr 08 16 MGR030 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 handbook, full pagewidth 1000 µF (16/40 V) 220 nF VP1 VP2 18 13 IN1 2 100 nF VP − 60 kΩ VINL front − V/I + OA 17 OUT1 + + + 60 kΩ TDA8586TH n.c. 1 − − V/I − VPn OA 19 HVP1 + 220 nF + 60 kΩ VINL rear 220 nF + − + IN2 3 IN3 4 OA V/I − V/I − VINR front 20 OUT2 − + OA 14 OUT3 + ACREF 6 47 µF (10 V) + − + VPn 60 kΩ 30 kΩ − V/I − VPn OA + + + 60 kΩ VINR rear switched +9 V OA 11 OUT4 − V/I − +5 V 4.7 µF (10 V) INTERFACE DIAGNOSTIC 10 9 15 16 DDDSEL OVERRULE PGND2 PGND1 Fig.10 Quad single-ended application (SOT418-2). 1999 Apr 08 4 or 8 Ω 10 kΩ MSO 8 15 kΩ switch − + IN4 5 4 or 8 Ω 12 HVP2 BUFFER 30 kΩ 4 or 8 Ω − 60 kΩ 220 nF 4 or 8 Ω 17 7 DIAG MGR031 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 INTERNAL PIN CONFIGURATION PIN TDA8586TH NAME 2, 3, 4, 5 and 6 inputs EQUIVALENT CIRCUIT VP handbook, halfpage IN MGE014 11, 12, 14, 17, 19 and 20 outputs handbook, halfpage VP OUT 0.5 VP 8 mode select handbook, halfpage MGE015 VP MGE016 1999 Apr 08 18 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 PACKAGE OUTLINES DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) SOT243-1 non-concave Dh x D Eh view B: mounting base side d A2 B j E A L3 L Q c 1 v M 17 e1 Z bp e e2 m w M 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A2 bp c D (1) d Dh E (1) e mm 17.0 15.5 4.6 4.2 0.75 0.60 0.48 0.38 24.0 23.6 20.0 19.6 10 12.2 11.8 2.54 e1 e2 1.27 5.08 Eh j L L3 m Q v w x Z (1) 6 3.4 3.1 12.4 11.0 2.4 1.6 4.3 2.1 1.8 0.8 0.4 0.03 2.00 1.45 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-03-11 97-12-16 SOT243-1 1999 Apr 08 EUROPEAN PROJECTION 19 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 HSOP20: heatsink small outline package; 20 leads; low stand-off SOT418-2 E D A x X c E2 y HE v M A D1 D2 10 1 pin 1 index Q A A2 E1 (A3) A4 θ Lp detail X 20 11 Z w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) D1 D2 E(2) E1 E2 e HE Lp Q +0.12 0.53 0.32 16.0 13.0 −0.02 0.40 0.23 15.8 12.6 1.1 0.9 11.1 10.9 6.2 5.8 2.9 2.5 1.27 14.5 13.9 1.1 0.8 1.7 1.5 bp c D(2) v w x y 0.25 0.25 0.03 0.07 Z θ 2.5 2.0 8° 0° Note 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 97-10-29 98-02-25 SOT418-2 1999 Apr 08 EUROPEAN PROJECTION 20 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. SOLDERING Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). WAVE SOLDERING Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE • For packages with leads on two sides and a pitch (e): The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. MANUAL SOLDERING Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Surface mount packages REFLOW SOLDERING MANUAL SOLDERING Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. 1999 Apr 08 When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 21 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection TDA8586 Suitability of IC packages for wave, reflow and dipping soldering methods SOLDERING METHOD MOUNTING PACKAGE WAVE REFLOW(1) DIPPING Through-hole mount DBS, DIP, HDIP, SDIP, SIL suitable(2) − suitable Surface mount not suitable suitable − suitable − suitable − not recommended(4)(5) suitable − not recommended(6) suitable − BGA, SQFP suitable(3) HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Apr 08 22 Philips Semiconductors Preliminary specification Power amplifier with load detection and auto BTL/SE selection NOTES 1999 Apr 08 23 TDA8586 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545002/750/02/pp24 Date of release: 1999 Apr 08 Document order number: 9397 750 05483