PHILIPS PCF8548U/2

INTEGRATED CIRCUITS
DATA SHEET
PCF8548
65 × 102 pixels matrix LCD driver
Product specification
Supersedes data of 1999 Mar 22
File under Integrated Circuits, IC12
1999 Aug 16
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
3.1
Packages
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
7
PIN FUNCTIONS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
R0 to R64: row driver outputs
C0 to C101: column driver outputs
VSS1 and VSS2: negative power supply rails
VDD1 to VDD3: positive power supply rails
VLCDIN: LCD power supply
VLCDOUT: LCD power supply
VLCDSENSE: voltage multiplier regulation input
(VLCD)
T1 to T12: test pads
SDAIN and SDAOUT: I2C-bus data lines
SCL: I2C-bus clock signal
SA0: slave address
OSC: oscillator
RES: reset
8
BLOCK DIAGRAM FUNCTIONS
8.1
8.2
8.3
8.4
8.5
8.6
Oscillator
I2C-bus interface
Display control logic
Display Data RAM (DDRAM)
Timing generator
LCD row and column drivers
9
INITIALIZATION
10
ADDRESSING
10.1
10.2
Display data RAM structure
RAM access
11
I2C-BUS INTERFACE
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.2
Characteristics of the I2C-bus
Bit transfer
START and STOP conditions
System configuration
Acknowledge
I2C-bus protocol
1999 Aug 16
2
12
INSTRUCTIONS
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.3
12.3.1
12.4
12.4.1
12.4.2
12.5
12.6
12.7
12.7.1
12.8
12.9
12.10
External reset (RES)
Function set
Power-Down (PD)
V
H
MX
MY
Display control
D and E
Display configuration
TRS
BRS
Set Y address of RAM
Set X address of RAM
Set HV generator stages
S[1:0]
Temperature control
Bias system
Set VOP value
13
LIMITING VALUES
14
HANDLING
15
DC CHARACTERISTICS
16
AC CHARACTERISTICS
17
RESET
18
APPLICATION INFORMATION
19
CHIP INFORMATION
20
PAD INFORMATION
21
DEVICE PROTECTION DIAGRAM
22
TRAY INFORMATION
23
DEFINITIONS
24
LIFE SUPPORT APPLICATIONS
25
PURCHASE OF PHILIPS I2C COMPONENTS
26
BARE DIE DISCLAIMER
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
1
PCF8548
FEATURES
• Single-chip LCD controller/driver
• 65 row and 102 column outputs
• Display data RAM 65 × 102 bits
• On-chip:
– Configurable 5 (4, 3 and 2) × voltage multiplier
generating VLCD (external VLCD also possible)
2
– Generation of intermediate LCD bias voltages
• Portable instruments
– Oscillator requires no external components
(external clock also possible).
• Point of sale terminals.
APPLICATIONS
• Telecom equipment
• 400 kbits/s fast I2C-bus interface
3
• CMOS compatible inputs
GENERAL DESCRIPTION
The PCF8548 is a low power CMOS LCD controller driver,
designed to drive a graphic display of 65 rows and
102 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD supply and bias voltages, resulting in a minimum of
external components and low power consumption.
The PCF8548 interfaces to most microcontrollers via an
I2C-bus interface.
• Mux rate: 1 : 65
• Logic supply voltage range VDD1 to VSS:
– 1.9 to 5.5 V.
• High voltage generator supply voltage range VDD2 to
VSS and VDD3 to VSS:
– 2.4 to 4.5 V with LCD voltage internally generated
(voltage generator enabled).
• Display supply voltage range VLCD to VSS:
3.1
– 4.5 to 9.0 V
Packages
The PCF8548 is available as chip with bumps in tray; tape
carrier package is available on request.
• Low power consumption, suitable for battery operated
systems
• Temperature compensation of VLCD
• Slim chip layout, suitable for Chip-On-Glass (COG)
applications
• Programmable bottom row pads mirroring and top row
pads mirroring, for compatibility with both Tape Carrier
Package (TCP) and COG applications.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCF8548U/2
Tray
chip with bumps in tray
−
PCF8548U/9
Bumped wafer
quarter wafer
−
1999 Aug 16
3
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
5
PCF8548
BLOCK DIAGRAM
VDD1
handbook, full pagewidth
VDD2
VDD3
C0 to C101
R0 to R64
65
102
VSS1
PCF8548
COLUMN DRIVERS
ROW DRIVERS
DATA LATCHES
SHIFT REGISTER
VSS2
RES
VLCDIN
BIAS
VOLTAGE
GENERATOR
OSCILLATOR
VLCDSENSE
VLCDOUT
HIGH
VOLTAGE
GENERATOR
4 STAGES
DISPLAY DATA RAM
65 × 102 BITS
TIMING
GENERATOR
I2C-BUS
INTERFACE
SDAOUT SDAIN SCL
OSC
SA0
DISPLAY CONTROL LOGIC
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12
MGS393
Fig.1 Block diagram.
6
PINNING
SYMBOL
PAD
DESCRIPTION
SYMBOL
PAD
DESCRIPTION
RES
1
external reset input (active
LOW)
VLCDIN
35 to 40
LCD supply voltage
R32 to R19
41 to 54
LCD row driver outputs
SDAOUT
2
I2C-bus data output
R0 to R18
57 to 75
LCD row driver outputs
SDAIN
3 and 4
I2C-bus data input
C0 to C101
76 to 177
LCD column driver outputs
SCL
5 and 6
I2C-bus clock input
R50 to R33
178 to 195
LCD row driver outputs
T2
7
test 2 output
R51 to R64
198 to 211
LCD row driver outputs
SA0
8
least significant bit of slave
address
T12 to T9
212 to 215
test outputs
T7 to T5
T4 and T3
T1
9 to 11
12 and 13
14
test inputs
test input/output
test input
VSS1
15 to 20
negative power supply 1
VSS2
21 to 26
negative power supply 2
VLCDOUT
28 to 33
voltage multiplier output
34
voltage multiplier
regulation input (VLCD)
VLCDSENSE
1999 Aug 16
OSC
216
oscillator
T8
217
test input
VDD1
218 to 223
supply voltage 1
VDD3
224 to 226
supply voltage 3
VDD2
227 to 233
supply voltage 2
27, 55, 56, dummy pads
196 and 197
4
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
7
7.1
PCF8548
7.8
PIN FUNCTIONS
T1 and T3 to T7 must be connected to VSS1. T8 must be
connected to VDD1. T2 and T9 to T12 must be left
open-circuit; not accessible to user.
R0 to R64: row driver outputs
These pads output the row signals.
7.2
C0 to C101: column driver outputs
7.9
These pads output the column signals.
7.3
VSS1 and VSS2: negative power supply rails
VDD1 to VDD3: positive power supply rails
VDD2 and VDD3 are the supply voltages for the internal
voltage generator. Both have to be at the same voltage
and must be connected together outside of the chip. If the
internal voltage generator is not used, they should both be
connected to power or to the VDD1 pad.
VDD1 is used as the power supply for the rest of the chip.
This voltage can be a different voltage than VDD2 and
VDD3.
7.5
VLCDIN: LCD power supply
7.10
Internally generated positive power supply for the liquid
crystal display. An external LCD supply voltage can be
supplied using the VLCDIN pad. In this case, VLCDOUT has
to be connected to ground, and the internal voltage
generator has to be programmed to zero. If the PCF8548
is in power-down mode, the external LCD supply voltage
must be switched off.
7.6
7.11
SA0: slave address
Two different slave addresses can be selected using the
SA0 pad. This allows two PCF8548 LCD drivers to be
connected to the same I2C-bus.
VLCDOUT: LCD power supply
7.12
OSC: oscillator
When the on-chip oscillator is used this input must be
connected to VDD1. An external clock signal, if used, is
connected to this input.
7.13
VLCDSENSE: voltage multiplier regulation input
(VLCD)
RES: reset
This signal is used to reset the device. The signal is active
LOW.
VLCDSENSE is the input voltage for the internal voltage
multiplier regulation.
If the internal voltage generator is used then VLCDSENSE
must be connected to VLCDOUT. If an external supply
voltage is used then VLCDSENSE must be connected to
ground.
1999 Aug 16
SCL: I2C-bus clock signal
I2C-bus serial clock signal input.
Positive power supply for the liquid crystal display. If the
internal voltage generator is used, the two supply rails
VLCDIN and VLCDOUT must be connected together and an
external capacitor must be connected (see Fig.19).
7.7
SDAIN and SDAOUT: I2C-bus data lines
Serial data and acknowledge lines for the I2C-bus.
By connecting SDAIN to SDAOUT, the SDA line becomes
fully I2C-bus compatible. Having the acknowledge output
(SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAOUT pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8548
will not be able to create a valid logic 0 level. By splitting
the SDA input from the output the device could be used in
a mode that ignores the acknowledge bit. In COG
applications where the acknowledge cycle is required, it is
necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid
LOW level.
VSS2 is related to VDD2 and VDD3 and VSS1 is related to
VDD1.
7.4
T1 to T12: test pads
5
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
8
8.1
PCF8548
8.5
BLOCK DIAGRAM FUNCTIONS
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the I2C-bus.
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to VDD1. An external
clock signal (if used), is connected to this input.
8.2
8.6
9
Display control logic
Reset is accomplished by applying an external RES pulse
(active LOW). When reset occurs within the specified time
all internal registers are initialized, however the RAM is still
undefined. The state after reset is described in
Section 12.1.
Display Data RAM (DDRAM)
The PCF8548 contains a 65 × 102 bit static RAM which
stores the display data. The RAM is divided into 8 banks of
102 bytes and 1 bank of 102 bits [(8 × 8 + 1) × 102 bits].
During RAM access, data is transferred to the RAM via the
I2C-bus interface. There is a direct correspondence
between the X address and column output number.
1999 Aug 16
INITIALIZATION
Immediately following Power-on, all internal registers and
the RAM content are undefined. A reset pulse must first be
applied.
The display control logic generates the control signals to
read from the RAM via the 102 bits parallel port. It also
generates the control signals for the row and column
drivers.
8.4
LCD row and column drivers
The PCF8548 contains 65 row and 102 column drivers,
which connect the appropriate LCD bias voltages to the
display in accordance with the data to be displayed.
Figure 2 shows typical waveforms. Unused outputs should
be left unconnected.
I2C-bus interface
The I2C-bus interface receives and executes the
commands sent via the I2C-bus. It also receives RAM data
and sends it to the RAM.
8.3
Timing generator
The RES input must be ≤0.3 VDD when VDD reaches
VDD(min) (or higher) within a maximum time tVHRL after VDD
goes HIGH (see Fig.17).
6
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
frame n + 1
frame n
ROW 0
R0 (t)
ROW 1
R1 (t)
COL 0
C0 (t)
COL 1
C1 (t)
Vstate1(t)
Vstate2 (t)
VLCD
V2
V3
V4
V5
VSS
VLCD
V2
V3
V4
V5
VSS
VLCD
V2
V3
V4
V5
VSS
VLCD
V2
V3
V4
V5
VSS
VLCD − VSS
V3 − VSS
Vstate1(t)
VLCD − V2
0V
V3 − VSS
V4 − V5
0V
VSS − V5
V4 − VLCD
VSS − VLCD
VLCD − VSS
V3 − VSS
Vstate2 (t)
VLCD − V2
0V
V3 − VSS
V4 − V5
0V
VSS − V5
V4 − VLCD
VSS − VLCD
0 1 2 3 4 5 6 7 8...
... 64 0 1 2 3 4 5 6 7 8...
Vstate1(t) = C1(t) − R0(t).
Vstate2(t) = C1(t) − R1(t).
Fig.2 Typical LCD driver waveforms.
1999 Aug 16
7
... 64
MGS671
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
DDRAM
bank 0
top of LCD
bank 1
bank 2
LCD
bank 3
bank 7
bank 8
MGS395
Fig.3 DDRAM to display mapping.
1999 Aug 16
8
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
10 ADDRESSING
The Display Data RAM (DDRAM) of the PCF8548 is accessed as indicated in Figs 3, 6, 7, 8 and 9. The DDRAM has a
matrix of 65 × 102 bits. The RAM cells are addressed by the X and Y address pointers. The address ranges are X0 to
X101 (1100101b) and Y0 to Y8 (1000b). Addresses outside of these ranges are not allowed. In vertical addressing mode
(V = 1) the Y address increments after each byte (see Fig.5). After the last Y address (Y = 8), Y wraps around to 0 and
X increments to address the next column. In the horizontal addressing mode (V = 0) the X address increments after each
byte (see Fig.4). After the last X address (X = 101), X wraps around to 0 and Y increments to address the next row. After
the very last address (X = 101 and Y = 8) the address pointers wrap around to address X = 0 and Y = 0.
10.1
Display data RAM structure
handbook, full pagewidth
0
1
2
102
103
104
204
205
206
306
307
308
408
409
410
510
511
512
612
613
614
714
715
716
816
817
818
0
0
Y address
917
X address
101
8
MGS396
Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
1999 Aug 16
9
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
0
9
1
10
0
2
3
4
Y address
5
6
7
8
0
917
X address
101
8
MGS397
Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
The DO bit defines the bit order (MSB on top or MSB on bottom) for writing to the RAM (see Figs 6 and 7).
handbook, full pagewidth
MSB
LSB
MSB
MGS398
LSB
Fig.6 RAM byte organization, if DO = 0.
1999 Aug 16
10
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
LSB
MSB
LSB
MGS399
MSB
Fig.7 RAM byte organization, if DO = 1.
The MX bit allows a horizontal mirroring; when MX = 1, the X address space is mirrored. The address X = 0 is then
located at the right side (column 101) of the display (see Fig.9). When MX = 0 the mirroring is disabled and the address
X = 0 is located at the left side (column 0) of the display (see Fig.8).
handbook, full pagewidth
0
8
0
X address
101
Y address
MGS400
Fig.8 RAM format addressing (MX = 0).
1999 Aug 16
11
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
0
8
101
X address
0
Y address
MBL044
Fig.9 RAM format addressing (MX = 1).
10.2
RAM access
If the D/C bit is logic 1 the RAM can be written to. The data is written to the RAM during the acknowledge cycle.
1999 Aug 16
12
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
• Slave: the device addressed by a master
11 I2C-BUS INTERFACE
11.1
• Multi-Master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
Serial Data line (SDA) and a Serial Clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
11.1.1
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock
signals of two or more devices.
BIT TRANSFER
11.1.4
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse because changes in the
data line at this time will be interpreted as a control signal.
Bit transfer is illustrated in Fig.10.
11.1.2
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. A master receiver must also
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end-of-data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a STOP
condition. Acknowledgement on the I2C-bus is illustrated
in Fig.13.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P). The START
and STOP conditions are illustrated in Fig.11.
11.1.3
ACKNOWLEDGE
SYSTEM CONFIGURATION
The system configuration is illustrated in Fig.12.
• Transmitter: the device which sends the data to the bus
• Receiver: the device which receives the data from the
bus
• Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Fig.10 Bit transfer.
1999 Aug 16
13
MBC621
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.11 Definition of START and STOP conditions.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.12 System configuration.
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.13 Acknowledgement on the I2C-bus.
1999 Aug 16
14
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
11.2
PCF8548
The control and data bytes are also acknowledged by all
addressed slaves on the bus.
I2C-bus protocol
The PCF8548 supports command, data write and status
read access.
After the last control byte, depending on the D/C bit setting,
either a series of display data bytes or command data
bytes may follow. If the D/C bit is set to logic 1, these
display bytes are stored in the display RAM at the address
specified by the data pointer. The data pointer is
automatically updated and the data is directed to the
intended PCF8548 device. If the D/C bit of the last control
byte is set to logic 0, these command bytes will be
decoded and the setting of the device will be changed
according to the received commands. The
acknowledgement after each byte is made only by the
addressed slave. At the end of the transmission the
I2C-bus master issues a STOP condition (P).
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. Two 7-bit slave
addresses (0111100 and 0111101) are reserved for the
PCF8548. The least significant bit of the slave address is
set by connecting the input SA0 to either logic 0 (VSS1) or
logic 1 (VDD1).
The I2C-bus protocol is illustrated in Fig.14.
The sequence is initiated with a START condition (S) from
the I2C-bus master which is followed by the slave address.
All slaves with the corresponding address acknowledge in
parallel, all the others will ignore the I2C-bus transfer. After
acknowledgement, one or more command words follow
which define the status of the addressed slaves.
A command word consists of a control byte, which defines
Co and D/C, plus a data byte (see Fig.14 and Table 1).
If the R/W bit is set to logic 1 the chip will output data
immediately after the slave address if the D/C bit, which
was sent during the last write access, is set to logic 0. If no
acknowledge is generated by the master after a byte, the
driver stops transferring data to the master.
The last control byte is tagged with a cleared most
significant bit (i.e. the continuation bit Co). After a control
byte with a cleared Co bit, only data bytes will follow. The
state of the D/C bit defines whether the data byte is
interpreted as a command or as RAM data.
mode
handbook, Write
full pagewidth
acknowledgement
from PCF8548
S
S 0 1 1 1 1 0 A 0 A 1 DC
0
slave address
acknowledgement
from PCF8548
control byte
A
acknowledgement
from PCF8548
data byte
2n ≥ 0 bytes
command word
Co
A 0 DC
Co
acknowledgement
from PCF8548
control byte
1 byte
acknowledgement
from PCF8548
data byte
A
A P
n ≥ 0 bytes
MSB . . . . . . . . . . . LSB
S R/
0 1 1 1 1 0 A W
0
Read mode
acknowledgement
from PCF8548
S
S 0 1 1 1 1 0 A 1 A
0
PCF8548
slave address
acknowledgement
from master
status bytes
A P
Co DC 0 0 0 0 0 0 A
control byte
slave address
Fig.14 I2C-bus protocol.
1999 Aug 16
15
MGS401
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
12 INSTRUCTIONS
The instruction format is divided into two modes:
1. If D/C is set LOW, commands can be sent to the chip.
2. If D/C is set HIGH, the DDRAM will be accessed.
Every instruction can be sent in any order to the PCF8548.
Table 1
Instruction set
COMMAND BYTE
INSTRUCTION
D/C
R/W
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
H = 0 or 1
NOP
0
0
0
0
0
0
0
0
0
0
no operation
Reserved
0
0
0
0
0
0
0
0
0
1
do not use
Function set
0
0
0
0
1
MX
MY
PD
V
H
Power-down control; entry
mode; extended instruction
set control (H)
Read status byte
0
1
PD
D
E
MX
MY
DO
read status byte
Write data
1
0
D7
TRS BRS
D6
D5
D4
D3
D2
D1
D0
writes data to RAM
X
do not use
H=0
Reserved
0
0
0
0
0
0
0
0
1
Set VLCD range
0
0
0
0
0
0
0
1
0
Display control
0
0
0
0
0
0
1
D
0
E
sets display configuration
Set HV-gen
stages
0
0
0
0
0
1
0
0
S1
S0
# of HV-gen voltage
multiplication
Set Y address of
RAM
0
0
0
1
0
0
Y3
Y2
Y1
Y0
sets Y address of RAM:
0≤Y≤8
Set X address of
RAM
0
0
1
X6
X5
X4
X3
X2
X1
X0
sets X address of RAM:
0 ≤ X ≤ 101
Reserved
0
0
0
0
0
0
0
0
1
X
do not use
Temperature
control
0
0
0
0
0
0
0
1
TC1
Display
configuration
0
0
0
0
0
0
1
DO
TRS BRS top/bottom row mode set data
order
Bias system
0
0
0
0
0
1
0
BS2
BS1
Reserved
0
0
0
1
X
X
X
X
X
Set VOP
0
0
1
PRS VLCD programming range
select
H=1
1999 Aug 16
TC0 set temperature coefficient
(TCx)
BS0 set bias system (BSx)
X
do not use (reserved for test)
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 write VOP to register
16
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
Table 2
PCF8548
Explanations of symbols in Table 1
BIT
0
1
RESET STATE
PD
chip is active
chip is in Power-down mode
1
V
horizontal addressing
vertical addressing
0
H
use basic instruction set
use extended instruction set
0
MX
normal X addressing
X address is mirrored
0
MY
display is not vertically mirrored
display is vertically mirrored
0
TRS
top rows are not mirrored
top rows are mirrored
0
BRS
bottom rows are not mirrored
bottom rows are mirrored
0
DO
MSB is on top
LSB is on top
0
VLCD programming range LOW
VLCD programming range HIGH
PRS
D and E
TC[1:0]
S[1:0]
0
00
display blank
D=0
10
normal mode
E=0
01
all display segments on
11
inverse video mode
00
VLCD temperature coefficient 0
01
VLCD temperature coefficient 1
10
VLCD temperature coefficient 2
11
VLCD temperature coefficient 3
00
2 × voltage multiplier
01
3 × voltage multiplier
10
4 × voltage multiplier
11
5 × voltage multiplier
TC[1:0] = 00
S[1:0] = 00
BS[2:0]
bias system
BS[2:0] = 000
Vop[6:0]
VLCD programming
Vop[6:0] = 0000000
12.1
External reset (RES)
After power-on a reset pulse must be applied immediately to the chip, as it is in an undefined state. A reset of the chip
can be achieved using the external reset pad. After the reset the LCD driver is set to the following states:
• Power-down mode (PD = 1)
• All LCD outputs at VSS (display off)
• Horizontal addressing (V = 0)
• Normal instruction set (H = 0)
• Normal display (MX = MY = TRS = BRS = 0)
• Display blank (E = D = 0)
• Address counter X[6:0] = 0 and Y[3:0] = 0
• Temperature coefficient (TC[1:0] = 0)
• Bias system (BS[2:0] = 0)
• VLCD is equal to 0, the HV generator is switched off (Vop[6:0] = 0 and PRS = 0)
• After power-on (RAM data is undefined), the reset signal does not change the content of the RAM.
1999 Aug 16
17
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
12.2
PCF8548
12.2.5
Function set
POWER-DOWN (PD)
12.2.1
MY
When MY = 1, the display is mirrored vertically.
• All LCD outputs at VSS (display off)
A change of this bit has an immediate effect on the display.
• Bias generator and VLCD generator off
• Oscillator off (external clock possible)
12.3
• VLCD can be disconnected
12.3.1
• RAM contents not cleared (RAM data can be written)
The bits D and E select the display mode (see Table 2).
• VLCD output is discharged to VSS.
12.4
12.2.2
12.4.1
V
When V = 0, the horizontal addressing is selected.
The data is written to the RAM as shown in Fig.4. When
V = 1, the vertical addressing is selected. The data is
written to the RAM as shown in Fig.5.
12.2.3
When H = 0 the commands ‘display control’, ‘set HV-gen
stages’, ‘set Y address’ and ‘set X address’ can be
performed. When H = 1 the other commands can be
executed. The commands ‘write data’ and ‘function set’
can be executed in both cases.
12.4.2
Display configuration
TRS
BRS
Bit BRS enables the bottom row pad blocks to be mirrored.
This is used to enable flexibility in the wiring of the row
lines from the PCF8548 to the LCD cell (e.g. COG or TCP
wiring). When BRS = 0 rows 0 to 18 and rows 33 to 50 are
organized as illustrated in Fig.22. When BRS = 1 rows
0 to 18 and rows 33 to 50 are mirrored and organized as
illustrated in Fig.23.
MX
When MX = 0, the display RAM is written from left to right
(X = 0 is on the left side of the display, X = 100 is on the
right side of the display). When MX = 1 the display RAM is
written from right to left (X = 0 is on the right side of the
display, X = 100 is on the left side of the display).
12.5
Set Y address of RAM
Y[3 : 0] defines the Y address vector address of the RAM.
Thus, if a horizontally mirroring of the display is desired the
RAM must first be rewritten.
Table 3
D AND E
Bit TRS enables the top row pad blocks to be mirrored.
This is used to enable flexibility in the wiring of the row
lines from the PCF8548 to the LCD cell (e.g. COG or TCP
wiring). When TRS = 0 rows 19 to 32 and rows 51 to 64
are organized as illustrated in Fig.22. When TRS = 1 rows
19 to 32 and rows 51 to 64 are mirrored and organized as
illustrated in Fig.23.
H
12.2.4
Display control
X and Y address ranges
Y3
Y2
Y1
Y0
CONTENT
ALLOWED X RANGE
0
0
0
0
bank 0 (display RAM)
0 to 101
0
0
0
1
bank 1 (display RAM)
0 to 101
0
0
1
0
bank 2 (display RAM)
0 to 101
0
0
1
1
bank 3 (display RAM)
0 to 101
0
1
0
0
bank 4 (display RAM)
0 to 101
0
1
0
1
bank 5 (display RAM)
0 to 101
0
1
1
0
bank 6 (display RAM)
0 to 101
0
1
1
1
bank 7 (display RAM)
0 to 101
1
0
0
0
bank 8 (display RAM); note 1
0 to 101
Note
1. In bank 8 only the MSB is accessed.
1999 Aug 16
18
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
12.6
PCF8548
Set X address of RAM
There are 4 different temperature coefficients available in
the PCF8548 (see Fig.15). The coefficients are selected
by the two bits TC[1:0]. Table 6 shows the typical values of
the different temperature coefficients. The coefficients are
proportional to the programmed VLCD.
The X address points to the columns. The range of X is
0 to 101 (65H).
12.7
12.7.1
Set HV generator stages
S[1:0]
12.9
Bias system
The PCF8548 incorporates a software configurable
voltage multiplier. After reset the voltage multiplier is set to
2 × VDD2. Other voltage multiplier factors are set via the
command ‘set HV-gen stages’ (see Tables 1 and 2).
The Bias voltage levels are set in the ratio
1
of R − R − nR − R − R giving a ------------- bias system.
n+4
The resulting bias levels are shown in Table 5.
12.8
Different multiplex rates require different factors n (see
Table 4); this is programmed by BS[2 : 0]. For Mux 1 : 65
the optimum bias value n is given by:
Temperature control
Due to the temperature dependency of the liquid crystals
viscosity, the LCD controlling voltage VLCD must be
increased with lower temperature to maintain optimum
contrast.
n =
65 – 3 = 5.06 = 5 resulting in 1⁄9bias.
m–3 =
MGS402
handbook, halfpage
VLCD
Tcut
Fig.15 Temperature coefficients.
1999 Aug 16
19
T
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
Table 4
PCF8548
Programming the required bias system
BS[2]
BS[1]
BS[0]
n
RECOMMENDED MUX RATE
0
0
0
7
1 : 100
0
0
1
6
1 : 81
0
1
0
5
1 : 64
0
1
1
4
1 : 49
1
0
0
3
1 : 36
1
0
1
2
1 : 24
1
1
0
1
1 : 16
1
1
1
0
1:9
Table 5
The parameters are explained in Fig.16 and Table 6.
The maximum voltage that can be generated is dependent
on the VDD2 voltage and the display load current.
Two overlapping VLCD ranges are selectable via the
command ‘HV-gen control’. For the LOW (PRS = 0) range
a = a1 and for the HIGH (PRS = 1) range a = a2 with steps
equal to b in both ranges. It should be noted that the
charge pump is turned off if VOP[6;0] and bit PRS are all set
to zero. For Mux 1 : 65 the optimum operation voltage of
the liquid can be calculated as follows:
LCD bias voltage
SYMBOL
BIAS VOLTAGES
BIAS VOLTAGES
FOR 1⁄9 BIAS
V1
VLCD
V2
(n + 3)/(n + 4)
8⁄
9 × VLCD
V3
(n + 2)/(n + 4)
7⁄
9
× VLCD
V4
2/(n + 4)
2⁄
9
× VLCD
V5
1/(n + 4)
1⁄
9
× VLCD
V6
VSS
VLCD
VSS
1 + 65
V LCD = --------------------------------------- × V th = 6.85 × V th
1
2 ×  1 – ----------

65
12.10 Set VOP value
The voltage at reference temperature can be calculated
as: [VLCD (T = Tcut)]
V LCD
( Tcut )
= ( a + V OP × b )
where Vth is the threshold voltage of the liquid crystal
material used.
(1)
The operating voltage VLCD can be set by software.
The generated voltage is dependent on the temperature,
programmed Temperature Coefficient (TC) and the
programmed voltage at reference temperature (Tcut).
V LCD = ( a + V OP × b ) × [ 1 + ( T – T cut ) × TC ]
(2)
Table 6
Typical values for parameters for the HV-generator programming
SYMBOL
BITS
VALUE
UNIT
a1
2.94 (PRS = 0)
a2
6.75 (PRS = 1)
V
b
0.03
V
Tcut
27
°C
1999 Aug 16
20
V
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
VLCD
a1
charge pump off
b
a2
a1+b
0H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH 00H 01H 02H 03H 04H 05H 06H . . . 5FH 6FH 7FH
LOW (PRS = 0)
HIGH (PRS = 1)
MGS658
VOP[6:0] (programmed); 00H to 7FH, programme range LOW and HIGH.
Fig.16 VOP programming of PCF8548.
As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD (9.0 V) the
customer must ensure while setting the VOP register and selecting the temperature coefficient, under all conditions and
including all tolerances VLCD remains below 9.0 V.
1999 Aug 16
21
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
13 LIMITING VALUES
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134); parameters are valid
over operating temperature range unless otherwise specified; all voltages referenced to VSS = 0 V. Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or at any other conditions above those given in the characteristics sections of the specification is not
implied. Exposure to limiting values for extended periods may affect device reliability.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD1
supply voltage
−0.5
+6.5
V
VDD2,VDD3
supply voltage for internal voltage generator
−0.5
+4.5
V
VLCD
supply voltage for the LCD
−0.5
+9.0
V
ISS
supply current
−50
+50
mA
Vi(n)
all input voltages
−0.5
VDD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
Ppack
power dissipation per package
−
300
mW
P/out
power dissipation per output
−
30
mW
14 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
15 DC CHARACTERISTICS
VDD1 = 1.9 to 5.5 V; VDD2 and VDD3 = 2.4 to 4.5 V; VSS1 and VSS2 = 0 V; VLCD = 4.5 to 9.0 V; Tamb = −40 to +85 °C;
unless otherwise specified.
SYMBOL
VDD1
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1.9
−
5.5
V
Tamb = −25 to +85 °C
1.8
−
5.5
V
supply voltage
VDD2,VDD3
supply voltage for
internal voltage
generator
LCD voltage internally
generated (voltage generator
enabled)
2.4
−
4.5
V
VLCDIN
LCD input supply
voltage
LCD voltage externally
supplied (voltage generator
disabled)
4.5
−
9.0
V
VLCDOUT
LCD output supply
voltage
LCD voltage internally
generated (voltage generator
enabled); note 1
4.5
−
9.0
V
IDD1
supply current
VDD1 = 2.8 V; VLCD = 7.6 V;
fsclk = 0; Tamb = 25 °C;
notes 2 and 3
−
20
−
µA
IDD2,IDD3
supply current for
internal voltage
generator
with external VLCD
−
0.5
−
µA
with internal VLCD generation; −
VDD1 = 2.8 V; VLCD = 7.6 V;
fsclk = 0; Tamb = 25 °C; no
display load; 4 × charge pump;
notes 2 and 3
180
−
µA
1999 Aug 16
22
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
SYMBOL
IDD(tot)
ILCDIN
PARAMETER
total supply current
supply current from
external VLCD
PCF8548
CONDITIONS
MIN.
TYP.
MAX.
UNIT
with internal VLCD generation; −
VDD1 = 2.8 V; VLCD = 7.6 V;
fsclk = 0; Tamb = 25 °C; no
display load; 4 × charge pump;
notes 2 and 3
200
350
µA
(Power-down mode) with
internal or external VLCD
generation; note 4
−
1.5
10
µA
VDD1 = 2.8 V; VLCD = 7.6 V;
fsclk = 0; Tamb = 25 °C; no
display load; notes 2, 3 and 5
−
30
−
µA
Logic
VIL
LOW-level input voltage
VSS1
−
0.3VDD1
V
VIH
HIGH-level input voltage
0.7VDD1
−
VDD1
V
IL
leakage current
Vi = VDD1 or VSS1
−1
−
+1
µA
Column and row outputs
Rrow
row output resistance
R0 to R64
VDD1 to VDD3 = 5.0 V;
VLCD = 7.6 V; IL = 10 µA;
outputs tested one at a time
−
12
20
kΩ
Rcol
column output
resistance C0 to C101
VLCD = 7.6 V
−
12
20
kΩ
Vbias(col)
column bias tolerance
C0 to C101
−100
0
+100
mV
Vbias(row)
row bias tolerance
R0 to R64
−100
0
+100
mV
+300
mV
LCD supply voltage generator
VLCD
VLCD tolerance
internally generated
VDD1 = 2.8 V; VLCD = 7.6 V;
fsclk = 0; Tamb = 25 °C;
no display load;
notes 2, 3 6 and 7
−300
0
TC
temperature coefficient
00
−
−0.0 × 10−3
−
01
−
1/°C
−0.76 ×
10−3
−
1/°C
10−3
10
−
−1.05 ×
−
1/°C
11
−
−2.10 × 10−3 −
1/°C
Notes
1. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load.
2. Internal clock.
3. When fsclk = 0 there is no I2C-bus clock.
4. Power-down mode. During power-down all static currents are switched off.
5. If external VLCD, the display load current is not transmitted to IDD.
6. Tolerance depends on the temperature; (typically zero at Tamb = 27 °C), maximum tolerance values are measured
at the temperature range limit.
7. For TC0 to TC3.
1999 Aug 16
23
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
16 AC CHARACTERISTICS
VDD1 = 1.9 to 5.5 V; VDD2 and VDD3 = 2.4 to 4.5 V; VSS1 and VSS2 = 0 V; VLCD = 4.5 to 9 V; Tamb = −40 to +85 °C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
20
38
70
kHz
20
38
100
kHz
−
73
−
Hz
fOSC
oscillator frequency
fclk(ext)
external clock frequency
fframe
frame frequency
tVHRL
VDD1 to RES LOW
see Fig.17 and note 2
0
−
1
µs
tW(RES)
RES LOW pulse width
see Fig.17 and note 3
100
−
−
ns
VDD1 = 2.8 V;
Tamb = −20 to +70 °C
fOSC or fclk(ext) = 38 kHz;
note 1
I2C-bus timing characteristics; see note 4
fSCLK
SCL clock frequency
0
−
400
kHz
tSCLL
SCL clock LOW period
1.3
−
−
µs
tSCLH
SCL clock HIGH period
0.6
−
−
µs
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
0.9
µs
tr
SCL and SDA rise time
note 5
20 + 0.1Cb
−
300
ns
tf
SCL and SDA fall time
note 5
20 + 0.1Cb
−
300
ns
tf(SDA)(ro)
SDA fall time for read out
VDD1 = <3.6 V
20 + 0.1Cb
−
1000
ns
Cb
capacitive load represented by each
bus line
−
−
400
pF
tSU;STA
set-up time for a repeated START
condition
0.6
−
−
µs
tHD;STA
START condition hold time
0.6
−
−
µs
tSU;STO
set-up time for STOP condition
0.6
−
−
µs
tSW
tolerable spike width on bus
−
−
50
ns
tBUF
bus free time between a STOP and
START condition
1.3
−
−
µs
note 6
Notes
1.
f clk ( ext )
f frame = ----------------520
2. RES may be LOW before VDD1 goes HIGH.
3. If tW(RES) is longer than 3 ns (typical) a reset may be generated.
4. All timing values are valid within the operating supply voltage and ambient temperature ranges and are referenced
to VIL and VIH with an input voltage swing of VSS to VDD.
5. The rise and fall times specified here refer to the driver device (i.e. not PCF8548) and are part of the general fast
I2C-bus specification. When PCF8548 asserts an acknowledge on SDA, the minimum fall time is 10 ns.
Cb = capacitive load per bus line.
6. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width <tSW(max).
1999 Aug 16
24
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
17 RESET
handbook, full pagewidth
VDD
t W(RES)
RES
t W(RES)
VDD
t VHRL
RES
t W(RES)
Fig.17 Reset timing.
1999 Aug 16
25
t W(RES)
MGS404
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
18 APPLICATION INFORMATION
Table 7
Programming example for PCF8548
BITS
STEP
DISPLAY
B7
B6
B5
B4
B3
B2
B1
B0
OPERATION
I2C-bus start
1
2
0
1
1
1
1
0
0
0
slave address for write
3
0
0
0
0
0
0
0
0
control byte with cleared Co
bit and D/C set to logic 0
4
0
0
1
0
0
0
0
1
function set; PD = 0; V = 0;
select extended instruction
set (H = 1 mode)
5
0
0
0
1
0
0
1
0
set bias system 2; this is the
recommended bias system
for a multiplex rate 1 : 65
6
1
1
1
0
1
0
1
0
set VOP; VOP is set to a
+106 × b [V]; it should be
noted that the required
voltage is dependent on the
liquid
7
0
0
1
0
0
0
0
0
function set; PD = 0; V = 0;
select normal instruction set
(H = 0 mode)
8
0
0
0
0
1
1
0
0
display control; set normal
mode (D = 1; E = 0)
I2C-bus start
9
restart; to write into the
display RAM the D/C must
be set to logic 1; therefore a
control byte is needed
10
0
1
1
1
1
0
0
0
slave address for write
11
0
1
0
0
0
0
0
0
control byte with cleared Co
bit and D/C set to logic 1
12
1
1
1
1
1
0
0
0
data write; Y and X are
initialized to 0 by default, so
they are not set here
MGS405
13
1
0
1
0
0
0
0
0
data write
MGS406
1999 Aug 16
26
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
BITS
STEP
14
DISPLAY
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
0
0
0
0
0
OPERATION
data write
MGS407
15
0
0
0
0
0
0
0
0
data write
MGS408
16
1
1
1
1
1
0
0
0
data write
MGS409
17
0
0
1
0
0
0
0
0
data write
MGS410
18
1
1
1
1
1
0
0
0
data write
MGS411
I2C-bus start
19
restart
20
0
1
1
1
1
0
0
0
slave address for write
21
1
0
0
0
0
0
0
0
control byte with set Co bit
and D/C set to logic 0
22
0
0
0
0
1
1
0
1
display control; set inverse
video mode (D = 1; E = 1)
MGS412
23
1
0
0
0
0
0
0
0
control byte with set Co bit
and D/C set to logic 0
24
1
0
0
0
0
0
0
0
set X address of RAM; set
address to ‘0000000’
MGS413
1999 Aug 16
27
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
BITS
STEP
DISPLAY
OPERATION
B7
B6
B5
B4
B3
B2
B1
B0
25
1
1
0
0
0
0
0
0
control byte with set Co bit
and D/C set to logic 1
26
0
0
0
0
0
0
0
0
data write
MGS414
27
0
0
0
0
0
0
0
0
control byte with cleared Co
bit and D/C set to logic 0
28
1
0
0
0
0
0
0
0
set X address of RAM; set
address to ‘0000000’
MGS415
I2C-bus start
29
restart
30
0
1
1
1
1
0
0
0
slave address for write
31
1
1
0
0
0
0
0
0
control byte with set Co bit
and D/C set to logic 1
32
1
1
1
1
1
0
0
0
write data
MGS416
33
1
0
0
0
0
0
0
0
control byte with set Co bit
and D/C set to logic 0
VDD1
handbook, halfpage
SCL
PCF8548
SCL
VDD1
MICROCONTROLLER
SDA
SDAIN
SDAOUT
MGS417
Fig.18 Connecting the I2C-bus interface.
1999 Aug 16
28
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
DISPLAY 102 × 65
102
33
VSS1
VSS2
VDD2,3
VDD1
PCF8548
VLCDSENSE
VLCDOUT
VLCDIN
32
≥3
CVLCD
CVDD
VDD
I/O
VSS
MGS418
The number of I/Os depends on the application.
Fig.19 Internal charge pump is used and a single supply voltage.
handbook, full pagewidth
DISPLAY 102 × 65
≥3
VDD1
33
VSS1
VSS2
PCF8548
VLCDSENSE
VLCDOUT
VLCDIN
102
VDD2,3
VDD1
32
CVDD1
CVLCD
I/O
CVDD2
VDD2
VSS
MGS419
The number of I/Os depends on the application.
Fig.20 Internal charge pump is used and two separate supply voltages.
1999 Aug 16
29
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
DISPLAY 102 × 65
33
VSS1
VSS2
PCF8548
VLCDSENSE
VLCDOUT
VLCDIN
102
VDD2,3
VDD1
32
≥3
CVDD
I/O
VDD
VSS
VLCD
MGS420
The number of I/Os depends on the application.
Fig.21 External high voltage generation is used.
The pinning of the PCF8548 is optimized for single plane wiring e.g. for chip-on-glass display modules, or for TCP.
Display size: 65 × 102 pixels. The required minimum value for the external capacitors in an application with the PCF8548
are: CVDD, CVDD1, CVDD2 and CVLCD = 1.0 µF (min.). Higher capacitor values are recommended for ripple reduction.
To reduce the sensitivity of the reset to ESD/EMC disturbances for a COG application, it is strongly recommended to
implement on the glass (ITO) a series input resistance in the reset line (The recommended minimum value is 8 kΩ).
19 CHIP INFORMATION
The PCF8548 is manufactured in n-well CMOS technology. The substrate is at VSS potential.
20 PAD INFORMATION
PAD
VALUE
UNIT
Minimum bump pitch
70
µm
Pad size, alumin
62 × 100
µm
Bumps
50 (±6) × 90 (±6) × 17.5 (±5)
µm
Wafer thickness without bumps
U/2 = 381; U/9 = 525
µm
1999 Aug 16
30
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
Table 8 Bonding pad location
All x and y coordinates are referenced to the centre of the
chip (dimension in µm; see Fig.22).
SYMBOL
PAD
x
y
SYMBOL
PAD
x
y
RES
SDAOUT
1
2
+1160
+840
+899.4
+899.4
R32
R31
41
42
−4235
−4305
+899.4
+899.4
SDAIN
SDAIN
SCL
SCL
3
4
5
6
+600
+520
+200
+120
+899.4
+899.4
+899.4
+899.4
R30
R29
R28
R27
43
44
45
46
−4375
−4445
−4515
−4585
+899.4
+899.4
+899.4
+899.4
T2
SA0
T7
7
8
9
−200
−410
−620
+899.4
+899.4
+899.4
T6
T5
T4
T3
T1
VSS1
10
11
12
13
14
−830
−1040
−1250
−1460
−1670
+899.4
+899.4
+899.4
+899.4
+899.4
VSS2
VSS2
15
16
17
18
19
20
21
22
23
24
−1750
−1830
−1910
−1990
−2070
−2150
−2310
−2390
−2470
−2550
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
R26
R25
R24
R23
R22
R21
R20
R19
dummy pad
dummy pad
R0
R1
R2
R3
R4
R5
R6
R7
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
−4655
−4725
−4795
−4865
−4935
−5005
−5075
−5145
−5355
−5320
−5040
−4970
−4900
−4830
−4760
−4690
−4620
−4550
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
VSS2
VSS2
dummy pad
25
26
27
−2630
−2710
−2790
+899.4
+899.4
+899.4
R8
R9
R10
65
66
67
−4480
−4410
−4340
−899.4
−899.4
−899.4
VLCDOUT
VLCDOUT
VLCDOUT
VLCDOUT
VLCDOUT
VLCDOUT
28
29
−2950
−3030
+899.4
+899.4
R11
R12
68
69
−4270
−4200
−899.4
−899.4
30
31
32
−3110
−3190
−3270
+899.4
+899.4
+899.4
R13
R14
R15
70
71
72
−4130
−4060
−3990
−899.4
−899.4
−899.4
VLCDSENSE
VLCDIN
VLCDIN
VLCDIN
33
34
35
36
37
−3350
−3430
−3510
−3590
−3670
+899.4
+899.4
+899.4
+899.4
+899.4
R16
R17
R18
73
74
75
−3920
−3850
−3780
−899.4
−899.4
−899.4
VLCDIN
VLCDIN
VLCDIN
38
39
40
−3750
−3830
−3910
+899.4
+899.4
+899.4
C0
C1
C2
C3
76
77
78
79
−3570
−3500
−3430
−3360
−899.4
−899.4
−899.4
−899.4
C4
80
−3290
−899.4
VSS1
VSS1
VSS1
VSS1
VSS1
VSS2
VSS2
1999 Aug 16
31
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
SYMBOL
PAD
x
y
SYMBOL
PAD
x
y
C5
C6
81
82
−3220
−3150
−899.4
−899.4
C47
C48
123
124
−210
−140
−899.4
−899.4
C7
C8
C9
C10
83
84
85
86
−3080
−3010
−2940
−2870
−899.4
−899.4
−899.4
−899.4
C49
C50
C51
C52
125
126
127
128
−70
+0
+140
+210
−899.4
−899.4
−899.4
−899.4
C11
C12
C13
87
88
89
−2800
−2730
−2660
−899.4
−899.4
−899.4
C53
C54
C55
129
130
131
+280
+350
+420
−899.4
−899.4
−899.4
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
−2590
−2520
−2450
−2380
−2310
−2240
−2170
−2100
−2030
−1960
−1890
−1750
−1680
−1610
−1540
−1470
−1400
−1330
−1260
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
+490
+560
+630
+700
+770
+840
+910
+980
+1050
+1120
+1190
+1260
+1330
+1400
+1470
+1540
+1610
+1680
+1750
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
C33
C34
C35
109
110
111
−1190
−1120
−1050
−899.4
−899.4
−899.4
C75
C76
C77
151
152
153
+1820
+1890
+2030
−899.4
−899.4
−899.4
C36
C37
C38
112
113
114
−980
−910
−840
−899.4
−899.4
−899.4
C78
C79
C80
154
155
156
+2100
+2170
+2240
−899.4
−899.4
−899.4
C39
C40
115
116
−770
−700
−899.4
−899.4
C81
C82
157
158
+2310
+2380
−899.4
−899.4
C41
C42
C43
117
118
119
−630
−560
−490
−899.4
−899.4
−899.4
C83
C84
C85
159
160
161
+2450
+2520
+2590
−899.4
−899.4
−899.4
C44
C45
C46
120
121
122
−420
−350
−280
−899.4
−899.4
−899.4
C86
C87
C88
162
163
164
+2660
+2730
+2800
−899.4
−899.4
−899.4
1999 Aug 16
32
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
SYMBOL
PAD
x
y
SYMBOL
PAD
x
y
C89
C90
C91
165
166
167
+2870
+2940
+3010
−899.4
−899.4
−899.4
R60
R61
207
208
+4515
+4445
+899.4
+899.4
C92
C93
168
169
+3080
+3150
−899.4
−899.4
C94
C95
C96
170
171
172
+3220
+3290
+3360
−899.4
−899.4
−899.4
R62
R63
R64
T12
209
210
211
212
+4375
+4305
+4235
+3880
+899.4
+899.4
+899.4
+899.4
C97
C98
C99
173
174
175
+3430
+3500
+3570
−899.4
−899.4
−899.4
T11
T10
T9
213
214
215
+3720
+3560
+3400
+899.4
+899.4
+899.4
C100
C101
R50
R49
176
177
178
179
+3640
+3710
+3850
+3920
−899.4
−899.4
−899.4
−899.4
R48
R47
R46
R45
R44
R43
R42
R41
R40
R39
180
181
182
183
184
185
186
187
188
189
+3990
+4060
+4130
+4200
+4270
+4340
+4410
+4480
+4550
+4620
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
−899.4
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
+3160
+2680
+2600
+2520
+2440
+2360
+2280
+2200
+2120
+2040
+1960
+1880
+1800
+1720
+1640
+1560
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
+899.4
R38
R37
190
191
+4690
+4760
−899.4
−899.4
OSC
T8
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD3
VDD3
VDD3
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
232
233
+1480
+1400
+899.4
+899.4
R36
R35
R34
192
193
194
+4830
+4900
+4970
−899.4
−899.4
−899.4
R33
dummy pad
dummy pad
195
196
197
+5040
+5320
+5355
R51
R52
R53
198
199
200
R54
R55
R56
R57
R58
R59
1999 Aug 16
Table 9
Alignment marks
x
y
MARKS
−899.4
−899.4
+899.4
+5214
−899.4
mark 1
−5214
−899.4
mark 2
+4099
+899.4
mark 3
+5145
+5075
+5005
+899.4
+899.4
+899.4
−4099
+899.4
mark 4
201
202
203
204
205
+4935
+4865
+4795
+4725
+4655
+899.4
+899.4
+899.4
+899.4
+899.4
206
+4585
+899.4
The alignment marks are circular with a diameter of
100 µm.
33
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row 51
dummy
row 33
dummy
alignment mark
alignment mark
col 101
row 50
row 18
col 0
row 64
OSC
T9
T10
T11
T12
T8
VDD1
VDD3
VDD2
RES
pad No.1
SDAOUT
SDAIN
SCL
T1
T3
T4
T5
T6
T7
SA0
T2
VSS1
VSS2
dummy
VLCDOUT
VLCDIN
alignment mark
VLCDSENSE
row 32
dummy
row 19
alignment mark
row 0
.
..
.
..
...
.
..
.
..
.
..
dummy
x
Philips Semiconductors
.
..
34
0, 0
...
.
..
.
..
y
65 × 102 pixels matrix LCD driver
handbook, full pagewidth
1999 Aug 16
PC8548-1
MGS421
Product specification
Fig.22 Bonding pad location.
PCF8548
Maximum chip size: 2.12 mm × 10.99 mm.
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
handbook, full pagewidth
R50
R49
.
..
.
.
R34
R33
R64
R63
.
..
.
.
R52
R51
PC8548-1
R19
R20
..
..
.
R31
R32
R0
R1
..
..
.
R17
R18
C0
C1
.
..
PC8548-1
MX = 1
..
.
C100
C101
MGS657
Fig.23 Pad layout for BRS, TRS and MX.
1999 Aug 16
COLUMNS
BRS = 1
COLUMNS
PC8548-1
TRS = 1
35
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
21 DEVICE PROTECTION DIAGRAM
handbook, full pagewidth
VSS1
VDD1
VDD1
VSS1
T2
VDD2
VSS1
VSS1
VDD1
VSS2
T3, T4
VDD3
VSS1
VSS1
VSS1
VLCDIN
VSS2
VSS1
T9
T10
T11
T12
VSS1
VLCDIN
VLCDOUT
VLCDSENSE
VSS1
VSS1
VSS1
VSS1
COL 0-101/ ROW 0-64
VDD1
VLCDIN
SA0
OSC
RES
T1
T5 to T7
VSS1
1 per block
VSS1
VSS1
MGS422
T8
VSS1
VSS1
Fig.24 Device protection diagram.
1999 Aug 16
36
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
22 TRAY INFORMATION
x
handbook, full pagewidth
A
C
y
D
B
F
E
MGS423
The dimensions are given in Table 10.
Fig.25 Tray details.
Table 10 Dimensions
DIM.
handbook, halfpage
PC8548-1
MGS424
The orientation of the IC in a pocket is indicated by the position of
the IC type name on the die surface with respect to the chamfer on
the upper left corner of the tray. Refer to the bonding pad location
diagram for the orientating and position of the type name on the die
surface.
Fig.26 Tray alignment.
1999 Aug 16
37
DESCRIPTION
VALUE
A
pocket pitch, x direction
13.77 mm
B
pocket pitch, y direction
4.45 mm
C
pocket width, x direction
11.09 mm
D
pocket width, y direction
2.3 mm
E
tray width, x direction
50.8 mm
F
tray width, x direction
50.8 mm
x
number of pockets in
x direction
3
y
number of pockets in
y direction
10
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
23 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Application information
Where application information is given, it is advisory and does not form part of the specification.
24 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
25 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
26 BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern
processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no
control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors
assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of
the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
1999 Aug 16
38
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8548
NOTES
1999 Aug 16
39
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Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA 67
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465006/02/pp40
Date of release: 1999
Aug 16
Document order number:
9397 750 05023