INTEGRATED CIRCUITS DATA SHEET TDA8083 Satellite Demodulator and Decoder (SDD3) Product specification File under Integrated Circuits, IC02 1999 Jul 28 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 FEATURES • One chip Digital Video Broadcasting (DVB) (ETS300421) compliant demodulator and concatenated Viterbi and Reed-Solomon decoder with de-interleaver and de-randomizer • 3.3 V supply voltage • Reed-Solomon (RS) decoder: • Relevant outputs are 5 V tolerant to ease interface to 5 V environment – (204, 188, T = 8) Reed-Solomon code • Few external components for full application – Automatic synchronization of bytes, transport packets and frames • On-chip crystal oscillator (4 MHz) and Phase-Locked Loop (PLL) for internal clock generation – Internal convolutional de-interleaving (I = 12; using internal memory) • Power-on reset module – De-randomizer based on Pseudo Random Binary Sequence (PRBS) • QPSK/BPSK demodulator: – Different modulation schemes: Quadrature Phase Shift Keying (QPSK) and Binary Phase Shift Keying (BPSK) – External indication of uncorrectable error (transport error indicator is set) – Indication of the number of lost blocks – Interpolator and internal anti-aliasing filter to handle variable symbol rates – Indication of the number of corrected blocks. • Interface: – Tuner Automatic Gain Control (AGC) control – I2C-bus interface initializes and monitors the demodulator and Forward Error Correction (FEC) decoder; a default mode is defined – Two on-chip matched 7-bit Analog-to-Digital Converters (ADCs) – Square-root raised-cosine Nyquist – Maximum symbol frequency of 30 Msymbols/s – 6-bit I/O expander for flexible access to and from the I2C-bus – Can be used at low channel Signal-to-Noise Ratio (S/R) – I2C-bus configurable interrupt input – Switchable I2C-bus loop-through to suppress I2C-bus crosstalk in the tuner – Internal full digital carrier recovery, clock recovery and AGC loops with programmable loop filters – Digital Satellite Equipment Control (DiSEqC) 1.X, tone burst generation and tone mode with a 22 or 44 kHz carrier – Two carrier recovery loops enabling optimum phase noise suppression – S/R estimation. – Parallel or serial output mode for MPEG transport stream (3-state mode also possible) • Viterbi decoder: – Rate 1⁄2 convolutional code based – Standby mode for reduced power consumption. • Package: QFP100 – Constraint length K = 7 with G1 = 171oct and G2 = 133oct • Boundary scan test. – Supported puncturing code rates: 1⁄2, 2⁄3, 3⁄4, 4⁄5, 5⁄6, 6⁄ , 7⁄ and 8⁄ 7 8 9 APPLICATIONS – 4-bit ‘soft decision’ inputs for both I and Q • Digital satellite TV: demodulation and FEC. – Truncation length of 144 – Automatic synchronization to detect puncturing rate and spectral inversion – Channel Bit Error Rate (BER) estimation from 10−2 to 10−8 – Differential decoding optional. 1999 Jul 28 2 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 GENERAL DESCRIPTION The TDA8083 has a double carrier loop configuration which has excellent capabilities of tracking phase noise. Synchronization of the FEC unit is done completely internally, thereby minimizing I2C-bus communication. The output of the TDA8083 allows different output modes (parallel or serial) to interface to a demultiplexer, descrambler or MPEG-2 decoder including a 3-state mode. For evaluation of the TDA8083, demodulator and Viterbi decoder outputs can be made available externally. This document specifies a DVB compliant demodulator and forward error correction decoder IC for reception of QPSK or BPSK modulated signals for satellite applications. The Satellite Demodulator and Decoder (SSD) can handle variable symbol rates without adapting the analog filters within the tuner. Typical applications for this device are: • MCPC (Multi-Channel Per Carrier): one QPSK or BPSK modulated signal in a single satellite channel (transponder) The SDD can be controlled and monitored by the I2C-bus. A 5-bit bidirectional I/O expander and an interrupt line are available. By sending an interrupt signal, the SDD can inform the microcontroller of its internal status. Separate resets are available for logic only, logic plus the I2C-bus and carrier loops. A switchable I2C-bus loop-through to the tuner is implemented to switch off the I2C-bus connection to the tuner. This reduces phase noise in the tuner in case of I2C-bus crosstalk. • Simul-cast: QPSK or BPSK modulated signal together with a Frequency Modulated (FM) signal in a single satellite channel (transponder). The TDA8083 can handle variable symbol rates in the range of 12 to 30 Msymbols/s with a minimum number of low cost and non-critical external components. Furthermore, for dish control applications hardware supports DiSEqC 1.X and tone burst generation via I2C-bus control. A 22 or a 44 kHz carrier can be generated (tone mode). The TDA8083 has minimal interfaces with the tuner. It only requires the demodulated analog I and Q baseband input signals and provides a tuner AGC control signal. Analog-to-digital conversion is done internally by two matched 7-bit ADCs. The TDA8083 runs on a low frequency crystal which is upconverted to a clock frequency by means of an internal PLL. Furthermore, the TDA8083 has an internal anti-alias filter, which can cover the range of symbol frequencies without the need to switch external (SAW) filters. 1999 Jul 28 3 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDA analog supply voltage 3.0 3.3 3.6 V VDDD digital supply voltage 3.0 3.3 3.6 V IDD(tot) total supply current − 270 340 mA fclk(int) internal clock frequency − − 64 MHz rs symbol rate 12 − 30 Msymbols/s αro Nyquist roll-off − 35 − % IL implementation loss note 2 − 0.3 − dB S/R signal-to-noise ratio locking the SDD in QPSK mode; note 2 2 − − dB Ptot total power dissipation Tamb = 70 °C; note 1 − 890 1220 mW note 1 Tstg storage temperature −55 − +150 °C Tamb ambient temperature 0 − 70 °C Tj junction temperature − − 125 °C Tamb = 70 °C Notes 1. Typical value is specified for a symbol rate of 27.5 Msymbols/s, a puncture rate of 3⁄4 and a supply voltage of 3.3 V. Maximum value is specified for a symbol rate of 30 Msymbols/s, a puncture rate of 7⁄8, a supply voltage of 3.6 V and using a 4 MHz crystal. 2. Implementation loss at the demodulator output and minimum SNR to lock the TDA8083 are measured including tuner in a laboratory environment at a symbol rate of 27.5 MS/s. ORDERING INFORMATION TYPE NUMBER TDA8083H 1999 Jul 28 PACKAGE NAME QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm 4 VERSION SOT317-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 55 I2C-BUS CONTROL 65 64 TDI P0 to P5 24, 23, 22, 21, 27, 26 I2C-BUS TUNER SWITCH TDO TCK TMS TRST 71 DATA I/O EXPANDER 70 63 69 XTALI XTALO 85 86 62 BOUNDARY SCAN TEST FINE AGC CONTROL TDA8083 LOCK DETECTORS OSCILLATOR AND PLL 58 57 56 DLOCK VLOCK RSLOCK SYNCHRONIZATION COARSE AGC 5 QA 78 DIGITAL PHASE ROTATOR DIGITAL PHASE ROTATOR ANTI-ALIASING FILTERING INTERPOLATION SQUARE-ROOT RAISED-COSINE ADC MUX Q0 to Q6 FINE AGC CLOCK RECOVERY 9, 11, 12, 13, 14, 16, 17 ENERGY DISPERSAL REMOVAL 94 ANTI-ALIASING FILTERING INTERPOLATION SQUARE-ROOT RAISED-COSINE MUX ADC REED-SOLOMON DECODER AGC 80 28 50 29, 30, 31, 33, 34, 35, 38, 45 48 49 61 DTO CONTROL 4 CARRIER RECOVERY (AFC LOOP) 20 INTERRUPT CONTROL 54 INT GENERAL PURPOSE Σ∆ CONVERTER 98 OUTSD POWER-ON RESET DISEQC AND TONE BURST 39 POR 91 DTO CONTROL PDOCLK PDOSYNC PDO0 to PDO7 PDOERR PDOVAL TEST TPLL PRESET CARRIER RECOVERY (PHASE LOOP) FCE353 DISCTRL Product specification Fig.1 Block diagram. TDA8083 handbook, full pagewidth IA DE-INTERLEAVER I0 to I6 VITERBI DECODER 99, 100, 1, 2, 6, 7, 8 Philips Semiconductors 52 SCLT Satellite Demodulator and Decoder (SDD3) 53 SDAT BLOCK DIAGRAM 1999 Jul 28 SDA SCL A0 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 PINNING SYMBOL PIN I/O DESCRIPTION I2 1 I digital I-input bit 2 (ADC bypass); note 1 I3 2 I digital I-input bit 3 (ADC bypass); note 1 VSSD1 3 − digital ground 1 (core and input periphery) TPLL 4 I test pin (normally connected to ground) VSSD2 5 − digital ground 2 (core and input periphery) I4 6 I digital I-input bit 4 (ADC bypass); note 1 I5 7 I digital I-input bit 5 (ADC bypass); note 1 I6 8 I digital I-input bit 6 (ADC bypass; MSB); note 1 Q0 9 I digital Q-input bit 0 (ADC bypass; LSB); note 1 VDDD1 10 − digital supply voltage 1 (core and input periphery) Q1 11 I digital Q-input bit 1 (ADC bypass); note 1 Q2 12 I digital Q-input bit 2 (ADC bypass); note 1 Q3 13 I digital Q-input bit 3 (ADC bypass); note 1 Q4 14 I digital Q-input bit 4 (ADC bypass); note 1 VSSD3 15 − digital ground 3 (core and input periphery) Q5 16 I digital Q-input bit 5 (ADC bypass); note 1 Q6 17 I digital Q-input bit 6 (ADC bypass; MSB); note 1 VSSD4 18 − digital ground 4 (output periphery) VDDD2 19 − digital supply voltage 2 (core and input periphery) PRESET 20 I P3 21 I/O quasi-bidirectional I/O port (bit 3) P2 22 I/O quasi-bidirectional I/O port (bit 2) P1 23 I/O quasi-bidirectional I/O port (bit 1) P0 24 I/O quasi-bidirectional I/O port (bit 0) VDDD3 25 − P5 26 I/O quasi-bidirectional I/O port (bit 5) P4 27 I/O quasi-bidirectional I/O port (bit 4) PDOCLK 28 O clock output for transport stream bytes PDO0 29 O parallel data output (bit 0) or serial data output PDO1 30 O parallel data output (bit 1) PDO2 31 O parallel data output (bit 2) VSSD5 32 − digital ground 5 (output periphery) PDO3 33 O parallel data output (bit 3) PDO4 34 O parallel data output (bit 4) PDO5 35 O parallel data output (bit 5) VSSD6 36 − digital ground 6 (core and input periphery) VSSD7 37 − digital ground 7 (core and input periphery) PDO6 38 O parallel data output (bit 6) POR 39 O Power-on reset output VDDD4 40 − digital supply voltage 4 (output periphery) 1999 Jul 28 input for default mode setting digital supply voltage 3 (output periphery) 6 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) SYMBOL TDA8083 PIN I/O DESCRIPTION VDDD5 41 − digital supply voltage 5 (core and input periphery) VSSD8 42 − digital ground 8 (core and input periphery) VDDD6 43 − digital supply voltage 6 (core and input periphery) VDDD7 44 − digital supply voltage 7 (output periphery) PDO7 45 O parallel data output (bit 7) n.c. 46 − not connected VSSD9 47 − digital ground 9 (core and input periphery) PDOERR 48 O transport error indicator output PDOVAL 49 O data valid indicator output PDOSYNC 50 O transport packet synchronization pulse output VSSD10 51 − digital ground 10 (output periphery) SCL 52 I serial clock of I2C-bus input; note 1 SDA 53 I/O serial data of I2C-bus input or output; note 1 INT 54 O interrupt output (active LOW); note 1 A0 55 I I2C-bus hardware address input RSLOCK 56 O Reed-Solomon lock indicator output VLOCK 57 O Viterbi lock indicator output DLOCK 58 O demodulator lock indicator output VDDD8 59 − digital supply voltage 8 (core and input periphery) VDDD9 60 − digital supply voltage 9 (core and input periphery) TEST 61 I test pin (normally connected to ground) TRST 62 I BST optional asynchronous reset input (normally connected to ground) TCK 63 I BST dedicated test clock input (normally connected to ground) SCLT 64 O serial clock of I2C-bus loop-through output; note 1 SDAT 65 I/O serial data of I2C-bus loop-through input or output; note 1 VDDD10 66 − digital supply voltage 10 (core and input periphery) VSSD11 67 − digital ground 11 (output periphery) VSSD12 68 − digital ground 12 (core and input periphery) TMS 69 I BST control signal input (normally connected to ground) TDO 70 O BST serial test data output TDI 71 I BST serial test data input (normally connected to ground) VDDD11 72 − digital supply voltage 11 (core and input periphery) VSSD13 73 − digital ground 13 (core and input periphery) VSSD(AD) 74 − digital ground ADC VDDD(AD) 75 − digital supply ADC Vref(B) 76 O bottom reference voltage output for ADC VSSA1 77 − analog ground 1 QA 78 I analog input Q Vref(Q) 79 O AGC decoupling output (Q path) IA 80 I analog input I VSSA2 81 − analog ground 2 1999 Jul 28 7 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) SYMBOL TDA8083 PIN I/O DESCRIPTION Vref(I) 82 O AGC decoupling output (I path) VDDA 83 − analog supply voltage VDD(XTAL) 84 − supply voltage for crystal oscillator XTALI 85 I crystal oscillator input XTALO 86 O crystal oscillator output VSS(XTAL) 87 − ground for crystal oscillator VDDD12 88 − digital supply voltage 12 (core and input periphery) VDDD13 89 − digital supply voltage 13 (core and input periphery) VSSD14 90 − digital ground 14 (core and input periphery) DISCTRL 91 O 22 or 44 kHz output for dish control applications VSSD15 92 − digital ground 15 (output periphery) VSSD16 93 − digital ground 16 (core and input periphery) AGC 94 O tuner AGC output; note 1 n.c. 95 − not connected VDDD14 96 − digital supply voltage 14 (output periphery) VDDD15 97 − digital supply voltage 15 (core and input periphery) OUTSD 98 O sigma delta output; note 1 I0 99 I digital I-input bit 0 (ADC bypass; LSB); note 1 I1 100 I digital I-input bit 1 (ADC bypass); note 1 Note 1. This pin is 5 V tolerant. 1999 Jul 28 8 Philips Semiconductors Product specification 81 VSSA2 82 Vref(I) 84 VDD(XTAL) 83 VDDA 85 XTALI 86 XTALO 87 VSS(XTAL) 88 VDDD12 90 VSSD14 89 VDDD13 TDA8083 91 DISCTRL 93 VSSD16 92 VSSD15 94 AGC 95 n.c 96 VDDD14 97 VDDD15 99 I0 100 I1 handbook, full pagewidth 98 OUTSD Satellite Demodulator and Decoder (SDD3) I2 1 80 IA I3 2 79 Vref(Q) VSSD1 3 78 QA TPLL 4 77 VSSA1 VSSD2 5 I4 6 76 Vref(B) 75 VDDD(AD) I5 7 I6 8 74 VSSD(AD) 73 VSSD13 Q0 9 72 VDDD11 VDDD1 10 71 TDI Q1 11 70 TDO Q2 12 69 TMS Q3 13 68 VSSD12 67 VSSD11 Q4 14 VSSD3 15 66 VDDD10 TDA8083H Q5 16 65 SDAT Q6 17 64 SCLT VSSD4 18 63 TCK VDDD2 19 62 TRST PRESET 20 61 TEST P3 21 60 VDDD9 P2 22 59 VDDD8 P1 23 58 DLOCK P0 24 57 VLOCK VDDD3 25 56 RSLOCK P5 26 55 A0 P4 27 54 INT Fig.2 Pin configuration. 1999 Jul 28 9 PDOVAL 49 PDOSYNC 50 PDOERR 48 VSSD9 47 n.c. 46 PDO7 45 VDDD7 44 VSSD8 42 VDDD6 43 VDDD5 41 POR 39 VDDD4 40 PDO6 38 PDO5 35 VSSD6 36 VSSD7 37 51 VSSD10 PDO4 34 52 SCL PDO1 30 PDO3 33 53 SDA PDO0 29 PDO2 31 VSSD5 32 PDOCLK 28 FCE352 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 APPLICATION INFORMATION handbook, full pagewidth FLASH FRONT PANEL CONTROL DRAM OPTIONAL 4 MHz clock I TUNER ZERO IF Q TDA8083 (SDD3) SAA7214 (T-MIPS) I2C-bus 1394 L + PHY IEEE 1394 BUFFERS IEEE 1284 RS232 SCART1 RGB CVBS/YC telco i/f smart card(s) VXX MODEM AV PES SAA7215 (DIVA3) ADAC SWITCHING SCART3 TDA8004 16-Mbit 16-Mbit SDRAM SDRAM Fig.3 Satellite set-top box concept. 1999 Jul 28 SCART2 LR 10 FCE354 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT317-2 c y X 80 A 51 81 50 ZE e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp L 31 100 detail X 30 1 wM bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 20.1 19.9 14.1 13.9 0.65 24.2 23.6 18.2 17.6 1.95 1.0 0.6 0.2 0.15 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT317-2 1999 Jul 28 EUROPEAN PROJECTION 11 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Jul 28 12 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable(2) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 Jul 28 13 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Jul 28 14 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) TDA8083 NOTES 1999 Jul 28 15 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1999 SCA 67 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/01/pp16 Date of release: 1999 Jul 28 Document order number: 9397 750 05355