PHILIPS TDA10085

INTEGRATED CIRCUITS
DATA SHEET
TDA10085HT
Single chip DVB-S/DSS channel
receiver
Product specification
Supersedes data of 2000 March 16
File under Integrated Circuits, IC02
2001 Aug 31
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
CONTENTS
11
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
7
LIMITING VALUES
8
THERMAL CHARACTERISTICS
9
CHARACTERISTICS
10
APPLICATION INFORMATION
11
PACKAGE OUTLINE
12
SOLDERING
12.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
12.2
12.3
12.4
12.5
13
DATA SHEET STATUS
14
DEFINITIONS
15
DISCLAIMERS
16
PURCHASE OF PHILIPS I2C COMPONENTS
2001 Aug 31
2
TDA10085HT
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
1
TDA10085HT
FEATURES
• DSS and DVB-S compliant single chip demodulator and
forward error correction
• Dual 6-bit Analog-to-Digital Converter (ADC) on-chip
• PLL that allows using a low-cost crystal
(typically 4 MHz)
• DiSEqC 1.X from 1 to 8 byte-long sequences with
modulated or unmodulated output
2
• DVB-S receivers (ETS 300-421)
• DSS dish control
• DSS receivers.
• Digital cancellation of ADC offset
• Simultaneous parallel and serial output interfaces
3
• Variable rate BPSK/QPSK coherent demodulator
GENERAL DESCRIPTION
The TDA10085 is a single-chip channel receiver for
satellite television reception matching both DSS and
DVB-S standards. The device contains a dual 6-bit flash
ADC, variable rate BPSK/QPSK coherent demodulator
and forward error correction functions. The ADC interfaces
directly with I and Q analog baseband signals.
After analog-to-digital conversion, the TDA10085
implements a bank of cascadable filters as well as
anti-alias and half-Nyquist filters. An analog AGC signal is
generated using an amplitude estimation function. The
TDA10085 performs clock recovery at twice the baud rate
and achieves coherent demodulation without any
feedback to the local oscillator. Forward error correction is
built around two error-correcting codes: a Reed-Solomon
(outer code) and a Viterbi decoder (inner code). The
Reed-Solomon decoder corrects up to 8 erroneous bytes
among the N (204) bytes of one data packet.
A convolutional de-interleaver is located between the
Viterbi output and the Reed-Solomon decoder input. The
de-interleaver and Reed-Solomon decoder are
automatically synchronized according to a frame
synchronization algorithm that uses the sync pattern
present in each packet. The TDA10085 is controlled via an
I2C-bus interface. The circuit operates at sampling
frequencies up to 100 MHz, can process variable
modulation rates and achieves transmission rates up to
45 Mbaud. Furthermore, for dish control applications,
hardware supports DiSEqc 1.x with control access via the
I2C-bus.
• Modulation rate variable from 1 to 49 Mbauds
• Automatic gain control output
• Digital symbol timing recovery:
– Acquisition range up to 960 ppm
• Carrier offset cancellation up to one half of the sampling
frequency
• Digital carrier recovery:
– Acquisition range up to 12% of the symbol rate
• Half-Nyquist filters: roll-off = 0.35 for DVB and
0.2 for DSS
• Interpolating and anti-aliasing filters to handle variable
symbol rates
• Channel quality estimation
• Spectral inversion ambiguity resolution
• Viterbi decoder:
– Supported rates from 1/2 to 8/9
– Constraint length K = 7 with G1 = 1718 and
G2 = 1338
– Viterbi output BER measurement
– Automatic code rate search within 1/2, 2/3 and 6/7 in
DSS mode
– Automatic code rate search within 1/2, 2/3, 3/4, 5/6
and 7/8 in DVB-S mode
• Convolutional de-interleaver and Reed Solomon
decoder according to DVB and DSS specifications
An interrupt line that can be programmed to activate on
events or on timing information is provided.
• Automatic frame synchronization
Designed in 20 micron CMOS technology and housed in a
TQFP64 package, the TDA10085 operates over the
commercial temperature range.
• Selectable DVB-S descrambling
• I2C-bus interface
• 64-pin TQFP package
• CMOS technology (0.2 µm, 1.8 V to 3.3 V).
2001 Aug 31
APPLICATIONS
3
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
4
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
VERSION
TDA10085HT
5
TDA10085HT
NAME
DESCRIPTION
TQFP64
plastic thin quad flat package; 64 leads; body 10 × 10 × 1.0 mm
SOT357-1
BLOCK DIAGRAM
handbook, full pagewidth
VDDE5
DVCC
24
VAGC
7
VDDI
PLLVCC
3, 8, 26,
38, 55
30
VDD3
4
AVD
10
ADVD
16
VDDE
42
PWM
ENCODER
CARRIER
SYNC
AGC
DETECTION
AGC
DETECTION
27, 44,
57
62
61
VIN2
12
ADC OFFSET
CANCELLATION
VIN1
15
DUAL 6-BIT
ADC
60
59
COMPLEX
MULTIPLIER
FILTER
BANK
XIN
CLOCK
SYNC
1
2
VREFN
VREFP
51
REED SOLOMON
DECODER
DE-INTERLEAVER
SADDR0
DO5
DO4
DO3
DO2
DO1
DO0
OUTPUT
INTERFACE
DE-SCRAMBLER
19
37
13
34
14
BOUNDARY SCAN
TDA10085HT
35
18
36
TMD
CLB#
DO6
PLL
VITERBI
DECODER
ENSERI
53
52
NCO
XOUT
54
HALF-NYQUIST
FILTERS
DO7
40
46
41
17
FEL
TMS
TCK
TRST
TDI
TDO
20
IICDIV
SCL
SDA
SCL-0
33
32
47
48
49
29
28
SDA-0
CONTROL
LOGIC
I2C-BUS
INTERFACE
50
I2C-BUS
TUNER SWITCH
DISECQ
63
22K
21
22
31
5
CTRL1 CTRL2 CTRL3
PLLGND DGDND
Fig.1 Block diagram.
2001 Aug 31
6
4
9, 25, 39,
56, 64
VSSI
11
AVS
43
ADVS
23, 45,
58
VSSE
PSYNC
UNCOR
DEN
OCLK
MGU427
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
6
TDA10085HT
PINNING
SYMBOL
PIN
TYPE
XIN
1
I
XOUT
2
I
VDDI
3
supply
digital core supply voltage (typically 1.8 V)
PLLVCC
4
supply
analog supply voltage for the PLL (typically 3.3 V)
PLLGND
5
ground
analog ground for the PLL
DGND
6
ground
digital PLL core ground voltage; see note 2
DVCC
7
supply
digital PLL core supply voltage (typically 1.8 V)
VDDI
8
supply
digital ADC supply voltage (typically 1.8 V)
VSSI
9
ground
digital ADC ground voltage; see note 2
VDD3
10
supply
analog ADC supply voltage (typically 3.3 V)
AVS
11
ground
analog ground voltage
VIN2
12
I
analog signal input for channel Q; see note 1
VREFN
13
O
negative analog voltage reference output (typically 1.25 V); a
decoupling capacitor (typically 0.1 µF) must be placed as close as
possible between VREFN and GND
VREFP
14
O
positive analog voltage reference output (typically 2 V); a decoupling
capacitor (typically 0.1 µF) must be placed as closed as possible
between VREFP and GND
VIN1
15
I
analog signal input for channel I; see note 1
AVD
16
supply
SADDR0
17
I
SADDR0 input signal is the LSB of the I2C-bus address of the
TDA10085; other bits of the address are set internally to 000111,
therefore the complete I2C-bus address is (MSB to LSB):
0, 0, 0, 1, 1, 1 plus the SADDR0 bit; see note 1
TMD
18
I
test input; must be connected to ground for normal operation; see
note 1
ENSERI
19
I
enable serial interface input; when HIGH, the serial transport stream
is present on the boundary scan pins (TRST, TDO, TCK, TDI
and TMS); when LOW, the boundary scan pins are available; note 1
IICDIV
20
I
input to select the I2C-bus internal system clock frequency (depends
on the crystal frequency); internal I2C-bus clock is XIN when
IICDIV = 0 and XIN/4 if IICDIV = 1; see note 1
CTRL1
21
OD
control line output 1; this pin function is directly programmable
through the I2C-bus interface; default value is logic 1; open-drain
output requiring an external pull-up resistor to 3.3 V or to 5 V
CTRL2
22
OD
control line output 2; this pin function is directly programmable
through the I2C-bus interface; default value is logic 1; open-drain
output requiring an external pull-up resistor to 3.3 V or to 5 V
VSSE
23
ground
VDDE5
24
supply
digital 5 V supply voltage; required for the 5 V tolerance of inputs
VSSI
25
ground
digital core ground voltage; see note 2
2001 Aug 31
DESCRIPTION
crystal oscillator input and output pins; in a typical application, a
fundamental oscillator crystal is connected between pins XIN and
XOUT; see note 1
analog supply voltage (typically 3.3 V); a 0.1 µF decoupling capacitor
must be placed between AVD and AVS
digital ground voltage; see note 2
5
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
SYMBOL
TDA10085HT
PIN
TYPE
DESCRIPTION
VDDI
26
supply
digital core supply voltage (typically 1.8 V)
VDDE
27
supply
digital supply voltage (typically 3.3 V)
SDA_0
28
I/OD
I2C-bus bidirectional serial input/ open drain output; equivalent to
SDA but with a high-impedance state programmable via the I2C-bus;
a pull-up resistor must be connected between this pin and DVCC
SCL_0
29
OD
I2C-bus clock output; equivalent to SCL but with a high-impedance
state programmable via the I2C-bus; open drain output requiring an
external pull-up resistor to 5 V
VAGC
30
O or OD
PWM encoded output signal for AGC; the refresh frequency of AGC
information is the sampling frequency divided by 2048, the maximum
signal frequency on the VAGC output is 1/4 × AGC sampling clock;
the VAGC output can be selected by I2C-bus to be open-drain or
have 3.3 V capability (typically, output VAGC is fed to the AGC
amplifier through a single RC network)
CTRL3
31
I/OD
control line 3 input/open drain output; this pin function is directly
programmable through the I2C-bus interface and is an input by
default; it requires a pull-up resistor to 3.3 or 5 V, or a pull-down
resistor to GND
SDA
32
I/OD
I2C-bus bidirectional serial data input/output; the open-drain output
requires a pull-up resistor (typically 2.2 kΩ) to be connected between
SDA and 5 V for proper operation
SCL
33
I
I2C-bus clock input; nominally a square wave with a maximum
frequency of 400 kHz generated by the system I2C-bus master; see
note 1
TMS
34
I/O
boundary scan mode: test mode select input/output; provides the
logic levels needed to change the TAP controller from state to state
serial mode enabled (ENSERI = 1): serial TS uncorrectable output;
when not in serial mode, TMS must be set to VSS
TCK
35
I/O
boundary scan mode: test clock input/output; TCK is an independant
clock used to drive the TAP controller
serial mode enabled (ENSERI = 1): TCK is the serial TS clock
output; when not in serial mode, TCK must be set to VSS
TRST
36
I/O
boundary scan mode: test reset input/output; TRST is an active-LOW
reset input to the TAP controller
serial mode enabled (ENSERI = 1): test reset input/output; TRST is
the serial TS PSYNC output; when not in serial mode, TRST must be
set to VSS
FEL
37
OD
front-end locked output signal that goes HIGH when demodulator,
Viterbi decoder and de-interleaver are all synchronized; open-drain
output requiring an external pull-up resistor to 3.3 or 5 V; can be set
via the I2C-bus to be an interrupt pin
VDDI
38
supply
digital core supply voltage (typically 1.8 V)
VSSI
39
ground
digital core ground voltage; see note 2
TDI
40
I/O
boundary scan mode: test data and instruction serial input
serial mode enabled (ENSERI = 1): serial TS data output; must be
set to VSS when not in serial mode
2001 Aug 31
6
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
SYMBOL
TDO
TDA10085HT
PIN
TYPE
DESCRIPTION
41
I/O
boundary scan mode: test data serial output; output provided on the
falling edge of TCK
serial mode enabled (ENSERI = 1): serial TS enable input; must be
set to VSS when not in serial mode
ADVD
42
supply
analog supply voltage for the 2nd PLL (typically 1.8 V)
ADVS
43
ground
analog ground voltage for the 2nd PLL
VDDE
44
supply
digital supply voltage (typically 3.3 V)
VSSE
45
ground
digital ground voltage; see note 2
CLB#
46
I
asynchronous, active LOW input that clears the TDA10085; when
CLB# goes LOW the circuit immediately enters its RESET mode and
normal operation resumes three XIN rising edges later after CLB#
returns HIGH; at RESET, the I2C-bus register contents are all
initialized to their default values; the minimum width of CLB# LOW
level is three XIN clock periods; pin CLB# is not TTL, 5 V tolerant
PSYNC
47
O
packet sync output signal goes HIGH on a rising edge of OCLK each
time the first byte of a packet is provided
UNCOR
48
O
uncorrectable packet output signal goes HIGH on a rising edge of
OCLK when the packet provided is uncorrectable
DEN
49
O
data enable; this output signal is HIGH when there is valid data on
bus DO[7:0]
OCLK
50
O
output clock for the parallel DO[7:0] outputs; OCLK is generated
internally and depends on which interface type is selected
DO0
51
O
DO1
52
O
DO2
53
O
transport stream data output bits; part of the 8-bit parallel data output
after demodulation, Viterbi decoding, de-interleaving, RS decoding
and de-scrambling; possible output interfaces are three parallel and
two serial
DO3
54
O
VDDI
55
supply
digital core supply voltage (typically 1.8 V)
VSSI
56
ground
digital core ground voltage; see note 2
VDDE
57
supply
digital supply voltage (typically 3.3 V)
VSSE
58
ground
digital ground voltage; see note 2
DO4
59
O
DO5
60
O
DO6
61
O
DO7
62
O
22K
63
O
VSSI
64
ground
transport stream data output bits; part of the 8-bit parallel data output
after demodulation, Viterbi decoding, de-interleaving, RS decoding
and de-scrambling; possible output interfaces are three parallel and
two serial
22 kHz output used to control the antenna LNB (output is controlled
via the I2C-bus interface)
digital core ground voltage; see note 2
Notes
1. TTL, 5 V tolerant input (if VDDE5 is connected to 5 V).
2. DGND, VSSI and VSSE can be connected to the same ground plane.
2001 Aug 31
7
Philips Semiconductors
Product specification
49 DEN
50 OCLK
51 DO0
52 DO1
53 DO2
54 DO3
TDA10085HT
55 VDDI
56 VSSI
57 VDDE
58 VSSE
59 DO4
60 DO5
61 DO6
62 DO7
handbook, full pagewidth
63 22K
64 VSSI
Single chip DVB-S/DSS channel receiver
XIN 1
48 UNCOR
XOUT 2
47 PSYNC
VDDI 3
46 CLB#
PLLVCC 4
45 VSSE
PLLGND 5
44 VDDE
DGND 6
43 ADVS
DVCC 7
42 ADVD
41 TDO
VDDI 8
TDA10085HT
40 TDI
VSSI 9
VDD3 10
39 VSSI
AVS 11
38 VDDI
VIN2 12
37 FEL
Fig.2 Pin configuration.
2001 Aug 31
8
SDA 32
CTRL3 31
VAGC 30
SCL_0 29
SDA_0 28
VDDE 27
VDDI 26
VSSI 25
VDDE5 24
33 SCL
VSSE 23
AVD 16
CTRL2 22
34 TMS
CTRL1 21
VIN1 15
IICDIV 20
35 TCK
ENSERI 19
VREFP 14
TMD 18
36 TRST
SADDR0 17
VREFN 13
MGU426
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
7 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VVDDE
DC supply voltage
−0.5
+4.1
V
VVDDI
DC core supply voltage
−0.5
+2.2
V
VI
DC input voltage
−0.5
VVDDE + 0.5
V
Tamb
ambient temperature
0
70
°C
Tj
junction temperature
−
150
°C
Tsp
solder point temperature
−
300
°C
Note
1. Stresses above the Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute
Maximum Ratings conditions for extended periods may affect device reliability.
8
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
9
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
45
K/W
in free air
CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VVDDE
digital supply voltage
3.0
3.3
3.6
V
VVDDI
digital core supply voltage
1.6
1.8
2.0
V
VVDDE5
digital 5 V supply voltage
for 5 V tolerance of inputs 4.5
5.0
5.5
V
VIH
HIGH-level input voltage
TTL input; note 1
2.0
−
VVDDE + 0.3 V
VIL
LOW-level input voltage
TTL input
−0.5
−
+0.8
V
VOH
HIGH-level output voltage
IOH = −0.8 mA
VVDDE − 0.1 −
−
V
IOH = −IO(max); note 4
2.4
−
−
V
VOL
LOW-level output voltage
IOL = 0.8 mA
−
−
0.1
V
IOL = IO(max); note 4
−
−
0.4
V
68
−
78
mA
1 Mbaud
−
38
−
mA
27.5 Mbauds
−
93
−
mA
45 Mbauds
−
−
139
mA
input capacitance
−
10
−
pF
fXIN
crystal frequency
−
4
−
MHz
VIH
HIGH-level input voltage
0.7VVDDE
−
VVDDE
V
VIL
LOW-level input voltage
0
−
0.3VVDDE
V
digital PLL supply voltage
1.6
1.8
2.0
V
IVDDE
supply current for VVDDE
fs = 96 MHz
IVDDI
supply current for VVDDI
symbol rate
Ci
XIN
PLL
VDVCC
2001 Aug 31
9
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
SYMBOL
PARAMETER
TDA10085HT
CONDITIONS
MIN.
TYP.
MAX.
UNIT
analog PLL supply voltage
3.0
3.3
3.6
V
VVDD3
3 V ADC digital supply
voltage
3.0
3.3
3.6
V
VAVD
analog supply voltage
3.0
3.3
3.6
V
VVIN1,
VVIN2
analog input voltage
DC component
VVREFN
−
VVREFP
V
AC component
−
750
−
mV
VPLLVCC
ADC
Ci
analog input capacitance
−
−
16
pF
VVREFP
top voltage reference
−
2.475
−
V
VVREFN
bottom voltage reference
−
1.725
−
V
SINAD
ADC signal to noise and
distortion ratio
note 2
−
34
−
dB
THD
total harmonic distortion
note 3
−
35
−
dB
Notes
1. All inputs except pin CLB# are 5 V tolerant.
2. Signal-to-noise plus distortion ratio (SINAD): ratio between the RMS magnitude of the fundamental input frequency
to the RMS magnitude of all other ADC output signals.
3. Total Harmonic Distortion (THD): ratio of the RMS sum of all harmonics of the input signal (below one half of the
sampling frequency) to the RMS value at the fundamental frequency.
4. IO(max) = 8 mA for pins OCLK and TCK
IO(max) = 4 mA for pins DO[7:0], DEN, PSYNC, UNCOR, TDI, TDO, TRST, TMS, SDA, SCL_O and SDA_O
IO(max) = 2 mA for pins CTRL1, CTRL2, CTRL3, VAGC and FEL, 22K.
2001 Aug 31
10
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
10 APPLICATION INFORMATION
handbook, full pagewidth
VAGC XIN
30
1
MIXER
×
VIN1
LO
VREFP
from
LNB
PLL
VREFN
90° PHASE
SHIFT
XOUT
2
51-54
59-62
15
14
TDA10085HT
13
8
DO[7-0]
50
OCLK
49
DEN
48
UNCOR
47
PSYNC
GND
×
VIN2
12
28
29
32
33
SDA-0 SCL-0
SDA SCL
MIXER
MGU428
The TDA10085 can receive a 4 MHz clock signal delivered by the PLL synthesizer, or can generate the sampling clock from a crystal connected
between XIN and XOUT.
Bypass capacitors (0.1 µF) should be placed close to ADC voltage references VREFP and VREFN.
Fig.3 Front-end receiver schematic.
handbook, full pagewidth
LNB SUPPLY
GENERATION
channel I
LNB
TUNER
channel Q
VIN1
VIN2
VAGC
CTRL1
30
21
22K
63
15
TDA10085
51-54 MPEG2
59-62
8
12
28
29
SDA-0 SCL-0
32
33
SDA SCL
Fig.4 Typical use of CTRL1 and 22K outputs.
2001 Aug 31
11
transport
stream
DO[7-0]
MGU429
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
11 PACKAGE OUTLINE
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm
SOT357-1
c
y
X
A
48
33
49
32
ZE
e
E HE
A
(A 3)
A2 A
1
wM
pin 1 index
θ
bp
64
Lp
L
17
1
detail X
16
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.2
0.15
0.05
1.05
0.95
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1.0
0.75
0.45
0.2
0.08
0.1
Z D(1) Z E(1)
θ
1.45
1.05
7
0o
1.45
1.05
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT357-1
137E10
MS-026
2001 Aug 31
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
12
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
If wave soldering is used the following conditions must be
observed for optimal results:
12 SOLDERING
12.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
12.2
TDA10085HT
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
12.3
12.4
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2001 Aug 31
Manual soldering
13
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
12.5
TDA10085HT
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
13 DATA SHEET STATUS
DATA SHEET STATUS(1)
PRODUCT
STATUS(2)
DEFINITIONS
Objective specification
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary specification
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product specification
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2001 Aug 31
14
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
TDA10085HT
14 DEFINITIONS
15 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
16 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2001 Aug 31
15
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
© Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/04/pp16
Date of release: 2001
Aug 31
Document order number:
9397 750 08489