Philips Semiconductors Objective specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic full-pack envelope. The device is intended for use in Automotive applications, Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in general purpose switching applications. PINNING - SOT186A PIN BUK574-60H QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V PIN CONFIGURATION MAX. UNIT 60 20 30 150 42 V A W ˚C mΩ SYMBOL DESCRIPTION d case 1 gate 2 drain 3 source g case isolated s 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDS VDGR ±VGS ±VGSM Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature ID ID IDM Ptot Tstg Tj MIN. MAX. UNIT RGS = 20 kΩ tp ≤ 50 µs - 60 60 15 20 V V V V Ths = 25 ˚C Ths = 100 ˚C Ths = 25 ˚C Ths = 25 ˚C - - 55 - 20 13.5 80 30 150 150 A A A W ˚C ˚C TYP. MAX. UNIT - 4.17 K/W 55 - K/W THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-hs Thermal resistance junction to heatsink Thermal resistance junction to ambient With heatsink compound Rth j-a July 1996 1 Rev 1.001 Philips Semiconductors Objective specification PowerMOS transistor Logic level FET BUK574-60H STATIC CHARACTERISTICS Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance VGS(TO) IDSS IDSS IGSS RDS(ON) MIN. TYP. MAX. UNIT VGS = 0 V; ID = 0.25 mA 60 - - V VDS = VGS; ID = 1 mA VDS = 60 V; VGS = 0 V; Tj = 25 ˚C VDS = 60 V; VGS = 0 V; Tj =125 ˚C VGS = ±15 V; VDS = 0 V VGS = 5 V; ID = 20 A 1.0 - 1.5 1 0.1 10 34 2.0 10 1.0 100 42 V µA mA nA mΩ MIN. TYP. MAX. UNIT 10 18 - S DYNAMIC CHARACTERISTICS Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 20 A Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1100 420 160 1750 600 275 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 Ω; Rgen = 50 Ω - 25 110 150 100 40 150 220 145 ns ns ns ns Ld Internal drain inductance - 4.5 - nH Ls Internal source inductance Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT 2500 V ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Visol R.M.S. isolation voltage from all three terminals to external heatsink f = 50-60 Hz; sinusoidal waveform; R.H. ≤ 65% ; clean and dustfree Cisol Capacitance from T2 to external f = 1 MHz heatsink - - 10 - pF MIN. TYP. MAX. UNIT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR - - - 20 A IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage IF = 20 A ; VGS = 0 V - 0.9 80 2.0 A V trr Qrr Reverse recovery time Reverse recovery charge IF = 20 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 60 0.25 - ns µC July 1996 2 Rev 1.001 Philips Semiconductors Objective specification PowerMOS transistor Logic level FET BUK574-60H AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 41 A ; VDD ≤ 25 V ; Ths = 25 ˚C VGS = 5 V ; RGS = 50 Ω July 1996 3 MIN. TYP. MAX. UNIT - - 90 mJ Rev 1.001 Philips Semiconductors Objective specification PowerMOS transistor Logic level FET BUK574-60H MECHANICAL DATA Dimensions in mm Net Mass: 2 g 10.3 max 4.6 max 3.2 3.0 2.9 max 2.8 Recesses (2x) 2.5 0.8 max. depth 6.4 15.8 19 max. max. 15.8 max seating plane 3 max. not tinned 3 2.5 13.5 min. 1 0.4 2 3 M 1.0 (2x) 0.6 2.54 0.9 0.7 0.5 2.5 5.08 1.3 Fig.1. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". July 1996 4 Rev 1.001 Philips Semiconductors Objective specification PowerMOS transistor Logic level FET BUK574-60H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. July 1996 5 Rev 1.001