PI6C49016 Low Power Networking Clock Generator Features Description ÎÎ25 MHz crystal or clock input The PI6C49016 is a clock generator device intended for PCIExpress/networking applications. The device includes three 100 MHz differential outputs for PCI-Express using reduced power, one single-ended 125 MHz output, one single-ended 66.66 MHz, and one single-ended 80 MHz output with spread spectrum. ÎÎThree differential 100 MHz PCI-Express clock outputs – push-pull termination ÎÎSpread spectrum capability on all 100 MHz PCI-e clock outputs with -0.5% down spread ÎÎOne single-ended 66.66 MHz output ÎÎOne single-ended 125 MHz output for Gigabit Ethernet at 2.5V ÎÎOne single-ended 80 MHz output with selectable down spread. ÎÎ40-pin QFN package ÎÎOperating voltage 3.3 V ±5% ÎÎIndustrial temperature (-40 to +85°C) Using a serially programmable SMBus interface, the PI6C49016 incorporates spread spectrum modulation on the four 100 MHz PCI-Express outputs with -0.5% down spread and the 80 MHz output with selectable down spread. Block Diagram VDD VDDO 100MHz PCI-Express 0 100MHz PCI-Express 1 PLL1 with SS SCLK SDATA 100MHz PCI-Express 2 PD_RESET 125MHz (2.5V) PLL2 PLL3 with SS X1/CLK 25 MHz Clock Buffer/ Crystal Ocsillator 80MHz 66.66MHz PLL4 X2 External caps required with crystal for accurate tuning of the clock GND 13-0102 1 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Pin Description Power Grouping GND 18 Power for crystal oscillator VDD 19 Output Power for 125 MHz 25 Power for 125 MHz PLL 35, 37 Digital power PCIE0N GND VDD PCIE1 Power for 60/66 MHz PLL and outputs PCIE0 13, 22, 28 VDD VDD VDD PCIE1N Power for 80 MHz PLL and output VDD 12 GND Power for PCIe clocks Cdd 1, 3, 7, 30 PCIE2N Group Description PCIE2 Pins 31 1 NC NC NC GND GND VDD VDD GND 66.66M SCLK VDD SDATA GND 125M VDDX VDDO X2 X1 PD_RESET GNDX VDD VDD 11 80M GND 21 40-pin QFN Pin List Pin# Pin Name Pin Type Pin Description 1 VDD Power 3.3V Supply Pin 2 GND Power Ground 3 VDD Power 3.3V Supply Pin 4 NC - - 5 NC - - 6 GND Power Ground 7 VDD Power 3.3V Supply Pin 8 SCLK Input SMBus clock input 9 SDATA I/O SMBus data input 10 GND Power Ground 11 80M Output 80 MHz LVCMOS output. Tri-state with weak pulldown when disabled 12 VDD Power 3.3V Supply Pin 13 VDD Power 3.3V Supply Pin 14 GNDX Power Ground 15 PD_RESET Input Global reset input powers down PLLs plus tri-states outputs and sets the I2C tables to their default state when pulled low. Controlled by external POR 13-0102 2 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Pin List Pin# Pin Name Pin Type Pin Description 16 X1 XI Crystal input. Connect to 25 MHz fundamental mode crystal or clock 17 X2 XO Crystal output. Connect to 25 MHz fundamental mode crystal. Float for clock input 18 VDDX Power 3.3V Supply Pin 19 VDDO Power 125 MHz output supply voltage. Connect to +2.5 V. 20 125M Output 125 MHz, +2.5 V LVCMOS output. Tri-stated with a weak pull-down when disabled. 21 GND Power Ground 22 VDD Power 3.3V Supply Pin 23 66.66M Output 66.66 MHz LVCMOS output. Tri-stated with a weak pull-down when disabled 24 GND Power Ground 25 VDD Power 3.3V Supply Pin 26 GND Power Ground 27 NC - - 28 VDD Power 3.3V Supply Pin 29 GND Power Ground 30 VDD Power 3.3V Supply Pin 31 PCIE0N Output Differential 100 MHz PCI Express Clock output 32 PCIE0 Output Differential 100 MHz PCI Express Clock output 33 PCIE1 Output Differential 100 MHz PCI Express Clock output 34 PCIE1N Output Differential 100 MHz PCI Express Clock output 35 VDD Power 3.3V Supply Pin 36 GND Power Ground 37 VDD Power 3.3V Supply Pin 38 Cdd Input Input pin for off chip bypass capacitor. Connect to 0.01 μF capacitor 39 PCIE2N Output Differential 100 MHz PCI Express Clock output 40 PCIE2 Output Differential 100 MHz PCI Express Clock output Notes: VDD and GND Pins Layout Guide 1. Small value decoupling caps. (0.1uF, 1uF, and 2.2uF) should be placed close each VDD pin or its via 2. Connect all GND pins to package thermal pad which must be connected to the GND plane for better thermal distribution and signal conducting with reasonable via count (>8) 13-0102 3 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Selection Table 1 – 80M Spread Spectrum Selection Table S1 S0 Spread % 0 0 -1.0% 0 1 OFF 1 0 -0.5% 1 1 -0.75% Refer to Byte0 control register. Default setting is S1:S0 = 01 13-0102 4 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Serial Data Interface (SMBus) PI6C49016 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 0 0 1 0/1 How to Write 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 Start bit D2H Ack Register offset Ack Byte Count =N Ack Data Byte 0 Ack Note: 1. … 8 bits 1 1 bit Data Byte N-1 Ack Stop bit Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock) 1 bit M: Start bit 8 bits M: Send "D2h" 1 bit 8 bits S: sends Ack M: send starting databyte location: N 1 bit S: sends Ack 1 bit M: Start bit 8 bits M: Send "D3h" 1 bit 8 bits S: sends Ack S: sends # of data bytes that will be sent: X 1 bit 8 bits 1 bit M: sends Ack S: sends starting data byte N M: sends Ack … 8 bits 1 bit 1 bit … S: sends data byte N+X-1 M: Not Acknowledge M: Stop bit Byte 0: Spread Spectrum Control Register Bit Description Type Power Up Condition Output(s) Affected Notes 7 Spread Select for 100 MHz push-pull PCI-Express clocks RW 0 All 100MHz PCIExpress outputs 0=spread off 1 = -0.5% down spread 6 Reserved R - - - 5 Global PD_RESET bit. Enables or disables all outputs. RW 1 All outputs 0 = disabled 1 = enabled 4 Spread Select for 80MHz S1 RW 0 3 Spread Select for 80MHz S0 RW 1 80M See Table 1 on Page4 2 OE for 66.66 MHz output RW 1 66.66M 0 = disabled 1 = enabled 1 Reserved R - - - 0 OE for single-ended 125MHz RW 1 Single-ended 125MHz 0 = disabled 1 = enabled 13-0102 5 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Byte 1: Control Register Bit Description Type Power Up Condition Output(s) Affected Notes 7 OE for 80MHz output RW 1 80MHz 1 = enabled 0 = disabled 6 to 0 Reserved R - - - Byte 2: Control Register Bit Description Type Power Up Condition Output(s) Affected Notes 7 to 0 Reserved R - - - Bit Description Type Power Up Condition Output(s) Affected Notes 7 Reserved RW - - - 6 Reserved RW - - - 5 Reserved RW - - - 4 OE for 100 MHz PCI-Express output PCIE2 RW 1 100 MHz PCI-Express output PCIE2 1 = enabled 0 = disabled 3 Reserved RW - - - 2 OE for 100 MHz PCI-Express output PCIE1 RW 1 100 MHz PCI-Express output PCIE1 1 = enabled 0 = disabled 1 OE for 100 MHz PCI-Express output PCIE0 RW 1 100 MHz PCI-Express output PCIE0 1 = enabled 0 = disabled 0 Reserved R - - - Bit Description Type Power Up Condition Output(s) Affected Notes 7 to 0 Reserved R - - - Byte 3: Control Register Byte 4: Control Register 13-0102 6 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Byte 5: Control Register Bit Description Type Power Up Condition Output(s) Affected Notes 7 Revision ID bit 3 R 0 - - 6 Revision ID bit 2 R 0 - - 5 Revision ID bit 1 R 0 - - 4 Revision ID bit 0 R 0 - - 3 Vendor ID bit 3 R 0 - - 2 Vendor ID bit 2 R 0 - - 1 Vendor ID bit 1 R 0 - - 0 Vendor ID bit 0 R 0 - - Bit Description Type Power Up Condition Output(s) Affected Notes 7 to 0 Reserved R - - - Byte 6: Control Register 13-0102 7 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Maximum Supply Voltage, VDD......................................................................7V All Inputs and Outputs...................................................... –0.5V to VDD +0.5V Ambient Operating Temperature............................................ –40°C to +85°C Storage Temperature............................................................... –65°C to +150°C Junction Temperature................................................................................ 125°C Peak Soldering Temperature..................................................................... 260°C ESD Protection (HBM).................................................................... 2000V Note: Stresses above the ratings listed below can cause permanent damage to the PI6C49016. These ratings, which are standard values for Pericom commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Parameters Min. Ambient Operating Temperatur Typ. Max. -40 Power Supply Voltage (measured in respect to GND) +3.135 Output Supply Voltage, VDDO2 +2.25 Minimum Pulse Width of PD_RESET Input 3.3 Units +85 °C +3.465 V +3.6 V 100 ns DC Electrical Characteristics Unless otherwise specified, VDD=3.3V±5%, VDDO2=2.5V,Ambient Temperature –40°C to +85°C Parameter Symbol Operating Supply Voltage Output Supply Voltage Input High Voltage Input Low Voltage Operating Supply Current IDD at Output Disable Condition Min Typ Max VDD 3.135 3.3 3.465 VDDO2 2.25 2.5 3.6 VIH X1/ICLK, SCLK, SDATA, PD_RESET 2 X1/ICLK, SCLK, SDATA, PD_RESET –0.3 IDD No load, all supply pins, PD_RESET = 1 90 PD_RESET = 0 6 Single-ended clocks ±35 PD_RESET 240 All single-ended clocks 110 All input pins 6 VIL Short Circuit Current IOS Internal Pull-Up/PullDown Resistor RPU/RPD Input Capacitance CIN 13-0102 Conditions 8 www.pericom.com PI6C49016 VDD Units V 0.8 Rev. B 100 mA kΩ pF 06/25/13 PI6C49016 Low Power Networking Clock Generator Electrical Characteristics - Single-Ended Unless otherwise specified, VDD=3.3V±5%, VDDO2=2.5V, Ambient Temperature –40°C to +85°C Parameter Input Clock Frequency Symbol Conditions Min FIN Output Frequency Error Output Rise Time tOR Output Fall Time tOF Output Clock Duty Cycle High-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage Peak-to-Peak Jitter Cycle-to-Cycle Jitter Phase Noise Modulation Rate Clock Stabilization Time from Power Up 20% to 80% 0.7 V to 1.7V 125 MHz 80% to 20% 1 Measured at VDD/2, 125M Measured at VDD/2, all other outputs Typ Max 25 MHz 0 ppm 0.5 47 0.5 50 1 0.4 1 53 45 50 55 1 Units ns % VOH IOH = -4mA VDD-0.4 V VOH IOH = -8mA 2.4 V VOL IOL = 8mA 0.4 66.66 MHz clock output ±150 125 MHz clock output ±100 125 MHz clock output 80 MHz clock output2, 3 66.66 MHz, 500 kHz offset 80MHz PD_RESET goes high to 1% of final frequency V ps ±100 ±100 -56 32 3 60 dB kHz 10 ms Note 1: CL = 15 pF Note 2: Cycle-to-cycle jitter is measured at 25°C. Note 3: Spread OFF. 13-0102 9 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Electrical Characteristics - 100MHz Differential Push-Pull Outputs Unless otherwise specified, VDD=3.3V±5%, Ambient Temperature –40°C to +85°C Parameter Symbol Conditions Min Typ Output Frequency Cycle-to-Cycle Jitter PCIe 2.0 RMS Phase Jitter J RM52.0 100 MHz ps PCIe Gen1 filter function 86 PCIe 2.0 Test Method @ 100 MHz Output 3.1 ps 0 % Spread Range -0.5 Spread Rate Duty Cycle Units 150 TCC/Jitter Peak-to-Peak Phase Jitter Max 32 TDC 45 Clock Stabilization from Power Up kHz 50 55 3.5 % ms Rising Edge Rate Note3, 4 0.6 4.0 V/ns Falling Edge Rate Note3, 4 0.6 4.0 V/ns Rise-Fall Matching Note3, 11 VT = 50%(measurement threshold), Intra-pair skew 50 ps VT = 50%(measurement threshold), Inter-pair skew 200 ps Output Skew Clock Source DC Impedance(Zo) High-Level Output Voltage Low-Level Output Voltage Absolute Crossing Point Voltage TOSKEW ZC-DC VOH VCROSS VCROSS Average Clock Period TPERIOD Absolute Period (including jitter and spread spectrum) Notes: 17 Note2 (Rs = 33ohm) VOL Variation of VCROSS over all rising clock edges Accuracy 20 Delta AVG TPERIOD ABS Note2, 5, 6 Ω 0.65 0.71 0.85 V -0.20 0 0.05 V 0.55 V 140 mV 0.25 Note2, 5, 8 Note3, 9, 10 -300 2800 ppm Note3, 7 9.847 10.203 ns 1. Measured at the end of an 8-inch trace with a 5pF load. 2. Measurement taken from a single-ended waveform. 3. Measurement taken from a differential waveform. 4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. 5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the falling edge 100M–. 6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 13-0102 10 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Notes (Continued) 7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation. 8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–. 9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations. 10. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or greater. With spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in maximum period resulting from the -0.5% down spread. 11. Matching applies to rising edge rate for PCIe and falling edge rate for PCIeN. It is measured using a ±75 mV window centered on the median cross point where PCIe rising meets PCIeN falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The rising edge rate of PCIe should be compared to the falling edge rate of PCIeN. The maximum allowed difference should not exceed 20% of the slowest edge rate. 13-0102 11 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Application Notes Crystal circuit connection The following diagram shows PI6C49016 crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1= 27pF, C2= 27pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. Crystal Oscillator Circuit XTAL_IN C1 27pF SaRonix-eCera FL2500047 Crystal�(CL�=�18pF) XTAL_OUT C2 27pF ASIC X1 CL= crystal spec. loading cap. X2 Cj Cj = chip in/output cap. (3~5pF) Cj Cb = PCB trace/via cap. (2~4pF) Cb Rf C1 Pseudo sine C1,2 = load cap. components Rd Cb Rd = drive level res. (100ohm) C2 Final choose/trim C1=C2=2 *CL - (Cb +Cj) for the target +/-ppm Example: C1=C2=2*(18pF) – (4pF+5pF)=27pF Recommended Crystal Specification Pericom recommends: a) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf b) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf 13-0102 12 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Decoupling Capacitors Decoupling capacitors of 0.01 ìF should be connected between VDD and GND as close to the device as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into PI6C49016 pin. Output Termination The PCI-Express differential clock outputs of the PI6C49016 are push-pull and require an external series resistor. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01μF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from PI6C49016.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. 13-0102 13 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator PCI-Express Layout Guidelines Common Recommendations for Differential Routing Dimension or Value Unit Figure L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch 1,2 L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch 1,2 L3 length, Route as non-coupled 50 ohm trace. RS 0.2 max 33 inch ohm 1,2 1,2 Dimension or Value Unit Figure 2 min to 16 max inch 1 1.8 min to 14.4 max inch 1 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Notes Notes Figure 1: Down Device Routing L1 L1’ Rs Rs L2 L4 L4’ L2’ Output Buffer PCI Express Board Down Device REF_CLK Input Figure 2: PCI-Express Connector Routing L1 L1’ Rs Rs L2 L4 L4’ L2’ Output Buffer 13-0102 PCI-Express Add-in Board REF_CLK Input 14 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Rs 33Ω 5% PI6C49016 Clock TLA Rs 33Ω 5% Clock# TLB 2pF 5% 2pF 5% Figure 4. Configuration Test Load Board Termination 13-0102 15 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator DATE: 07/12/11 Notes: 1. All dimensions are in mm. 2. Refer JEDEC MO-220. 3. Bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. DESCRIPTION: 40-contact, Thin Fine Pitch Quad Flat No-Lead, TQFN PACKAGE CODE: ZD (ZD40) DOCUMENT CONTROL #: PD-2021 REVISION: C Note: 11-0148 • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information(1-3) Ordering Code Package Code PI6C49016ZDIE ZD Package Description 40-pin, Pb-free & Green, TQFN, (ZD40) Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 13-0102 All trademarks are property of their respective owners. 16 www.pericom.com PI6C49016 Rev. B 06/25/13