CY62148DV30 4-Mbit (512 K × 8) MoBL® Static RAM 4-Mbit (512 K × 8) MoBL® Static RAM Features ■ Temperature Ranges ❐ Industrial: –40 °C to 85 °C ■ Very high speed: 55 ns ❐ Functional Description Wide voltage range: 2.20 V–3.60 V ■ Pin-compatible with CY62148CV25, CY62148CV30 and CY62148CV33 ■ Ultra low active power ❐ ❐ The CY62148DV30 [1] is a high-performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption when deselected (CE HIGH).The eight input and output pins (I/O0 through I/O7) are placed in a high-impedance state when: Typical active current: 1.5 mA at f = 1 MHz Typical active current: 8 mA at f = fmax (55-ns speed) ■ Ultra low standby power ■ Deselected (CE HIGH) ■ Easy memory expansion with CE, and OE features ■ Outputs are disabled (OE HIGH) ■ Automatic power-down when deselected ■ When the write operation is active(CE LOW and WE LOW) ■ Complementary metal oxide semiconductor (CMOS) for optimum speed/power ■ Available in Pb-free 32-pin Small-outline integrated circuit (SOIC package) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. For a complete list of related documentation, click here. Logic Block Diagram I/O0 Data in Drivers I/O1 512K x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 I/O3 I/O4 I/O5 COLUMN DECODER CE I/O6 POWER DOWN I/O7 A13 A14 A15 A16 A17 A18 WE OE Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document Number: 38-05341 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Page 1 of 15 CY62148DV30 Contents Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05341 Rev. *I Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC® Solutions ...................................................... 15 Cypress Developer Community ................................. 15 Technical Support ..................................................... 15 Page 2 of 15 CY62148DV30 Pin Configuration Figure 1. 32-pin SOIC pinout Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 4 32 31 30 29 5 6 28 27 7 8 9 10 11 12 26 25 1 2 3 13 14 15 16 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3 Product Portfolio Power Dissipation Product VCC Range (V) Range CY62148DV30LL Industrial Speed (ns) Min Typ[2] Max 2.2 3.0 3.6 55 Operating ICC (mA) f = 1 MHz f = fmax Standby ISB2 (A) Typ[2] Max Typ[2] Max Typ[2] Max 1.5 3 8 10 2 8 Note 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 38-05341 Rev. *I Page 3 of 15 CY62148DV30 DC input voltage [3, 4] ...................–0.3 V to VCC(max) + 0.3 V Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ..................................... 55 °C to +125 °C Supply voltage to ground potential [3, 4] ...............–0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in High Z state [3, 4] ......................–0.3 V to VCC(max) + 0.3 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (per MIL-STD-883, method 3015) ......................... > 2001 V Latch-up current .................................................... > 200 mA Operating Range Product Range Ambient Temperature VCC[5] CY62148DV30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions 55 ns Min Typ [2] Max Unit IOH = –0.1 mA VCC = 2.20 V 2.0 – – V IOH = –1.0 mA VCC = 2.70 V 2.4 – – V IOL = 0.1 mA VCC = 2.20 V – – 0.4 V IOL = 2.1 mA VCC = 2.70 V – – 0.4 V VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 V VCC = 2.7 V to 3.6 V 2.2 – VCC + 0.3 V VCC = 2.2 V to 2.7 V –0.3 – 0.6 V VCC = 2.7 V to 3.6 V –0.3 – 0.8 V IIX Input leakage current GND < VI < VCC –1 – +1 A IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 A ICC VCC operating supply current 8 10 mA – 1.5 3 mA f = fmax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels ISB1 Automatic CE Power-down current – CMOS inputs CE > VCC0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V), f = fmax (address and data only), f = 0 (OE, and WE), VCC = 3.60 V – 2 8 A ISB2 Automatic CE Power-down current – CMOS inputs CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V – 2 8 A Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns. 4. VIH(max) = VCC+0.75 V for pulse durations less than 20 ns. 5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. Document Number: 38-05341 Rev. *I Page 4 of 15 CY62148DV30 Capacitance Parameter [7] Description CIN Input capacitance COUT Output capacitance Test Conditions Max Unit 10 pF 10 pF Test Conditions SOIC Unit Still air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 55 C/W 22 C/W TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance Parameter [7] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 ALL INPUT PULSES VCC VCC OUTPUT 50 pF GND R2 90% 10% 90% 10% Fall time: 1 V/ns Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 2.5 V (2.2 V – 2.7 V) 3.0 V (2.7 V – 3.6 V) Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Document Number: 38-05341 Rev. *I Page 5 of 15 CY62148DV30 Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ [6] Max Unit 1.5 – – V 6 A VDR VCC for data retention ICCDR Data retention current tCDR[7] Chip deselect to data retention time 0 – – ns tR[8] Operation recovery time 55 – – ns VCC = 1.5 V, CE > VCC 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V – Data Retention Waveform Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 1.5 V tCDR VDR > 1.5 V 1.5 V tR CE Notes 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) 100 s. Document Number: 38-05341 Rev. *I Page 6 of 15 CY62148DV30 Switching Characteristics Over the Operating Range Parameter [9] Description 55 ns Min Max Unit Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid – 55 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 55 ns tDOE OE LOW to data valid – 25 ns [10] 5 – ns – 20 ns tLZOE tHZOE OE LOW to Low Z OE HIGH to High Z [10, 11] [10] tLZCE CE LOW to Low Z 10 – ns tHZCE CE HIGH to High Z [10, 11] – 20 ns tPU CE LOW to power-up 0 – ns CE HIGH to power-up – 55 ns tPD Write Cycle [12, 13] tWC Write cycle time 55 – ns tSCE CE LOW to write end 40 – ns tAW Address set-up to write end 40 – ns tHA Address hold from write end 0 – ns tSA Address set-up to write start 0 – ns tPWE WE pulse width 40 – ns tSD Data set-up to write end 25 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to High Z [10, 11] – 20 ns 10 – ns tLZWE WE HIGH to Low Z [10] Notes 9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 13. The minimum write cycle pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 38-05341 Rev. *I Page 7 of 15 CY62148DV30 Switching Waveforms Figure 4. Read Cycle No. 1 (Address Transition Controlled) [14, 15] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [15, 16] ADDRESS tRC CE tACE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZOE tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05341 Rev. *I Page 8 of 15 CY62148DV30 Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (WE Controlled) [17, 18] tWC ADDRESS tSCE CE tAW tSA WE tHA tPWE OE tSD DATA I/O NOTE 19 tHD DATAIN VALID tHZOE Notes 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state. 19. During this period, the I/Os are in output state and input signals should not be applied. Document Number: 38-05341 Rev. *I Page 9 of 15 CY62148DV30 Switching Waveforms (continued) Figure 7. Write Cycle No. 2 (CE Controlled) [20, 21] tWC ADDRESS tSCE CE tHA tSA tAW tPWE WE OE tSD DATA I/O tHD DATAIN VALID Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [21, 22] tWC ADDRESS tSCE CE tAW WE tHA tSA tPWE tSD DATA I/O NOTE 23 tHD DATAIN VALID tHZWE tLZWE Notes 20. Data I/O is high impedance if OE = VIH. 21. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state. 22. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. 23. During this period, the I/Os are in output state and input signals should not be applied. Document Number: 38-05341 Rev. *I Page 10 of 15 CY62148DV30 Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power-down Standby (ISB) L H L Data out (I/O0-I/O7) Read Active (ICC) L H H High Z Output disabled Active (Icc) L L X Data in (I/O0-I/O7) Write Active (Icc) Ordering Information Speed (ns) 55 Ordering Code CY62148DV30LL-55SXI Package Diagram Package Type 51-85081 32-pin SOIC (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 4 8 D V30 LL - 55 S X I Temperature Grade: I = Industrial Pb-free Package Type: S = 32 pin SOIC Speed Grade: 55 ns LL = Low Power Voltage Range = 3 V typical Process Technology: D = 130 nm Bus Width: 8 = × 8 Density: 4 = 4-Mbit Family Code: 621 = MoBL SRAM family Company ID: CY = Cypress Document Number: 38-05341 Rev. *I Page 11 of 15 CY62148DV30 Package Diagrams Figure 9. 32-pin SOIC (450 Mils) Package Outline, 51-85081 51-85081 *E Document Number: 38-05341 Rev. *I Page 12 of 15 CY62148DV30 Acronyms Acronym Document Conventions Description Units of Measure CMOS Complementary Metal Oxide Semiconductor I/O Input/Output °C degree Celsius MoBL More Battery Life MHz megahertz SOIC Small-Outline Integrated Circuit µA microampere SRAM Static Random Access Memory mA milliampere ns nanosecond pF picofarad V volt W watt Document Number: 38-05341 Rev. *I Symbol Unit of Measure Page 13 of 15 CY62148DV30 Document History Page Document Title: CY62148DV30, 4-Mbit (512 K × 8) MoBL® Static RAM Document Number: 38-05341 Rev. ECN No. Issue Date Orig. of Change ** 127480 06/17/03 HRT Description of Change Created new data sheet *A 131041 01/23/04 CBD Changed from Advance to Preliminary *B 222180 See ECN AJU Changed from Preliminary to Final Added 70 ns speed bin Modified footnote #6 and #12 Removed MAX value for VDR on “Data Retention Characteristics” table Modified input and output capacitance values Added Pb-free ordering information Removed 32-pin STSOP package *C 498575 See ECN NXR Added Automotive-A Operating Range Removed SOIC package from Product Offering Updated Ordering Information Table *D 729917 See ECN VKN Added SOIC package and its related information Updated Ordering Information Table *E 2896036 03/19/10 AJU Added Table of Contents. Removed inactive parts from Ordering Information. Updated Packaging Information Updated links in Sales, Solutions, and Legal Information. *F 3166059 02/08/2011 RAME Removed Automotive related info Removed 70 ns speed bin related info Remove TSOP and VFBGA package related info Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated to new template. *G 4315741 03/20/2014 VINI Updated Package Diagrams: spec 51-85081 – Changed revision from *C to *E. Updated to new template. Completing Sunset Review. *H 4576406 01/16/2015 VINI Added related documentation hyperlink in page 1. Updated Switching Characteristics: Added Note 13 and referred the same note in “Write Cycle”. Updated Switching Waveforms: Added Note 22 and referred the same note in Figure 8. *I 4702987 03/27/2015 VINI Updated Maximum Ratings: Referred Notes 3, 4 in “Supply voltage to ground potential”. Completing Sunset Review. Document Number: 38-05341 Rev. *I Page 14 of 15 CY62148DV30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2003-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05341 Rev. *I Revised March 27, 2015 Page 15 of 15 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.