CY7B993V, CY7B994V:High Speed Multi Phase PLL Clock Buffer

CY7B993V/CY7B994V
RoboClock®
High-Speed Multi-Phase PLL Clock Buffer
High Speed Multi Phase PLL Clock Buffer
Features
Functional Description
■
500 ps Max Total Timing Budget (TTB™) window
■
12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz
(CY7B994V) Input/Output Operation
■
Matched Pair Output Skew < 200 ps
■
Zero Input-to-Output Delay
■
18 LVTTL Outputs Driving 50 Terminated Lines
■
16 Outputs at 200 MHz: Commercial Temperature
■
6 Outputs at 200 MHz: Industrial Temperature
■
3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable
Reference Inputs
■
Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns
■
Multiply/Divide Ratios of 1–6, 8, 10, 12
■
Individual Output Bank Disable
■
Output High Impedance Option for Testing Purposes
■
Fully Integrated Phase Locked Loop (PLL) with Lock Indicator
■
<50-ps Typical Cycle-to-Cycle Jitter
■
Single 3.3V ± 10% Supply
■
100-pin TQFP Package
■
100-pin BGA Package
Cypress Semiconductor Corporation
Document Number: 38-07127 Rev. *M
The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user selectable control over system clock
functions. This multiple output clock driver provides the system
integrator with functions necessary to optimize the timing of
high-performance computer and communication systems.
These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Eighteen configurable outputs each drive terminated
transmission lines with impedances as low as 50 while delivering
minimal and specified output skews at LVTTL levels. The outputs are
arranged in five banks. Banks 1 to 4 of four outputs allow a divide
function of 1 to 12, while simultaneously allowing phase
adjustments in 625 ps to 1300 ps increments up to 10.4 ns. One
of the output banks also includes an independent clock invert
function. The feedback bank consists of two outputs, which
allows divide-by functionality from 1 to 12 and limited phase
adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that allows
smooth change-over to secondary clock source, when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
For a complete list of related documentation, click here.
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 3, 2016
CY7B993V/CY7B994V
RoboClock®
Logic Block Diagram
FBKA+
FBKA–
FBKB+
FBKB–
FBSEL
REFA+
REFA–
REFB+
REFB–
REFSEL
Feedback Bank
Bank 4
Bank 3
Document Number: 38-07127 Rev. *M
LOCK
Phase
Freq.
Detector
FBF0
FBDS0
FBDS1
FBDIS
3
3
3
Divide and
Phase
Select
Matrix
4F0
4F1
4DS0
4DS1
DIS4
3
3
3
3
Divide and
Phase
Select
Matrix
3F0
3F1
3DS0
3DS1
DIS3
INV3
3
3
3
3
Divide and
Phase
Select
Matrix
3
3
3
3
3
Divide and
Phase
Select
Matrix
3
3
3
3
Divide and
Phase
Select
Matrix
Bank 2
2F0
2F1
2DS0
2DS1
DIS2
Bank 1
1F0
1F1
1DS0
1DS1
DIS1
VCO
Filter
FS
OUTPUT_MODE
Control Logic
Divide and Phase
Generator
3
3
QFA0
QFA1
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
Page 2 of 22
CY7B993V/CY7B994V
RoboClock®
Contents
Pinouts .............................................................................. 4
Pin Definition .................................................................... 6
Block Diagram Description .............................................. 7
Phase Frequency Detector and Filter .......................... 7
VCO, Control Logic, Divider,
and Phase Generator ......................................................... 7
Time Unit Definition ..................................................... 7
Divide and Phase Select Matrix .................................. 8
Output Disable Description .......................................... 9
INV3 Pin Function ..................................................... 10
Lock Detect Output Description ................................. 10
Factory Test Mode Description ................................. 10
Safe Operating Zone ................................................. 10
Absolute Maximum Conditions ..................................... 11
Operating Range ............................................................. 11
Electrical Characteristics ............................................... 11
Thermal Resistance ........................................................ 13
Document Number: 38-07127 Rev. *M
AC Test Loads and Waveforms ..................................... 13
Switching Characteristics .............................................. 14
AC Timing Diagrams ...................................................... 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Page 3 of 22
CY7B993V/CY7B994V
RoboClock®
Pinouts
VCCQ
FBKA+
FBKA–
FBSEL
FBKB–
FBKB+
GND
GND
QFA1
VCCN
QFA0
GND
GND
1QA0
VCCN
1QA1
GND
GND
1QB0
VCCN
1QB1
GND
FBDS0
FBDS1
LOCK
Figure 1. 100-pin TQFP pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND
1
75
VCCQ
3F1
2
74
REFA+
4F1
3
73
REFA –
3F0
4
72
REFSEL
4F0
5
71
REFB–
4DS1
6
70
REFB+
3DS1
7
69
2F0
GND
8
68
FS
4QB1
9
67
GND
VCCN
10
66
2QA0
4QB0
11
65
VCCN
GND
12
64
2QA1
GND
13
63
GND
4QA1
14
62
GND
VCCN
15
61
2QB0
4QA0
16
60
VCCN
GND
17
59
2QB1
2DS1
18
58
GND
1DS1
19
57
FBF0
VCCQ
20
56
1F0
4DS0
21
55
GND
3DS0
22
54
VCCQ
2DS0
23
53
FBDIS
1DS0
24
52
DIS4
GND
25
51
DIS3
CY7B993/4V
Document Number: 38-07127 Rev. *M
GND
VCCQ
OUTPUT_MODE
GND
INV3
VCCQ
GND
3QB1
VCCN
3QB0
GND
GND
3QA1
VCCN
3QA0
GND
DIS2
DIS1
1F1
2F1
VCCQ
VCCQ
GND
GND
GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 4 of 22
CY7B993V/CY7B994V
RoboClock®
Pinouts (continued)
Figure 2. 100-pin BGA pinout
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
7
8
9
10
1QB1
1QB0
1QA1
1QA0
QFA0
QFA1
FBKB+
VCCQ
FBKA–
FBKA+
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCQ
FBKB–
FBSEL
REFA+
GND
GND
GND
GND
GND
GND
VCCQ
GND
GND
REFA–
LOCK
4F0
3F1
(3_level) (3_level)
GND
FBDS1 FBDS0
2F0
(3_level) (3_level) (3_level)
3F0
4F1
(3_level) (3_level)
4QB1
VCCN
4DS1
(3_level)
GND
4QB0
VCCN
3DS1
(3_level)
GND
GND
4QA1
2DS1
(3_level)
VCCQ
GND
4QA0
1DS1
1DS0
(3_level) (3_level)
4DS0
3DS0
2DS0
(3_level) (3_level) (3_level)
2F1
1F1
(3_level) (3_level)
DIS2
Document Number: 38-07127 Rev. *M
VCCQ
REFSEL REFB–
GND
FS
(3_level)
VCCN
REFB+
GND
GND
FBF0
(3_level)
VCCN
2QA0
GND
GND
GND
VCCQ
1F0
(3_level)
2QA1
VCCQ
GND
GND
VCCQ
DIS1
VCCN
VCCN
VCCN
3QA0
3QA1
OUTPUT
MODE FBDIS
(3_level)
2QB0
GND
INV3
(3_level)
DIS3
2QB1
GND
3QB0
3QB1
DIS4
Page 5 of 22
CY7B993V/CY7B994V
RoboClock®
Pin Definition
Pin Name [1]
I/O
Pin Type
Pin Description
FBSEL
Input
LVTTL
Feedback Input Select. When LOW, FBKA inputs are selected. When HIGH, the FBKB
inputs are selected. This input has an internal pull-down.
FBKA+, FBKA–
FBKB+, FBKB–
Input
LVTTL/
LVDIFF
Feedback Inputs. One pair of inputs selected by the FBSEL is used to feedback the clock
output xQn to the phase detector. The PLL operates such that the rising edges of the
reference and feedback signals are aligned in both phase and frequency. These inputs can
operate as differential PECL or single-ended TTL inputs. When operating as a single-ended
LVTTL input, the complementary input must be left open.
REFA+, REFA–
REFB+, REFB–
Input
LVTTL/
LVDIFF
Reference Inputs. These inputs can operate as differential PECL or single-ended TTL
reference inputs to the PLL. When operating as a single-ended LVTTL input, the complementary input must be left open.
REFSEL
Input
LVTTL
Reference Select Input. The REFSEL input controls how the reference input is configured.
When LOW, it uses the REFA pair as the reference input. When HIGH, it uses the REFB
pair as the reference input. This input has an internal pull-down.
FS
Input
3-level
Input
Frequency Select. This input must be set according to the nominal frequency (fNOM) (see
Table 1 on page 7).
FBF0
Input
3-level
Input
Feedback Output Phase Function Select. This input determines the phase function of
the Feedback bank’s QFA[0:1] outputs (see Table 3 on page 8).
FBDS[0:1]
Input
3-level
Input
Feedback Divider Function Select. These inputs determine the function of the QFA0 and
QFA1 outputs (see Table 4 on page 8).
FBDIS
Input
LVTTL
Feedback Disable. This input controls the state of QFA[0:1]. When HIGH, the QFA[0:1] is
disabled to the “HOLD-OFF” or “High Z” state; the disable state is determined by
OUTPUT_MODE. When LOW, the QFA[0:1] is enabled (see Table 5 on page 9). This input
has an internal pull-down.
[1:4]F[0:1]
Input
3-level
Input
Output Phase Function Select. Each pair controls the phase function of the respective
bank of outputs (see Table 3 on page 8).
[1:4]DS[0:1]
Input
3-level
Input
Output Divider Function Select. Each pair controls the divider function of the respective
bank of outputs (see Table 4 on page 8).
DIS[1:4]
Input
LVTTL
Output Disable. Each input controls the state of the respective output bank. When HIGH,
the output bank is disabled to the “HOLD-OFF” or “High Z” state; the disable state is
determined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled (see Table 5
on page 9). These inputs each have an internal pull-down.
INV3
Input
3-level
Input
Invert Mode. This input only affects Bank 3. When this input is LOW, each matched output
pair becomes complementary (3QA0+, 3QA1–, 3QB0+, 3QB1–). When this input is HIGH,
all four outputs in the same bank are inverted. When this input is MID all four outputs are
non inverting.
LOCK
Output
LVTTL
PLL Lock Indicator. When HIGH, this output indicates the internal PLL is locked to the
reference signal. When LOW, the PLL is attempting to acquire lock.
OUTPUT_MODE Input
3-Level
Input
Output Mode. This pin determines the clock outputs’ disable state. When this input is HIGH,
the clock outputs disable to high impedance (High Z). When this input is LOW, the clock
outputs disable to “HOLD-OFF” mode. When in MID, the device enters factory test mode.
QFA[0:1]
Output
LVTTL
Clock Feedback Output. This pair of clock outputs is intended to be connected to the FB
input. These outputs have numerous divide options and three choices of phase
adjustments. The function is determined by the setting of the FBDS[0:1] pins and FBF0.
[1:4]Q[A:B][0:1]
Output
LVTTL
Clock Output. These outputs provide numerous divide and phase select functions
determined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs.
VCCN
PWR
Output Buffer Power. Power supply for each output pair.
VCCQ
PWR
Internal Power. Power supply for the internal circuitry.
GND
PWR
Device Ground.
Note
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
Document Number: 38-07127 Rev. *M
Page 6 of 22
CY7B993V/CY7B994V
RoboClock®
Block Diagram Description
Table 1. Frequency Range Select
Phase Frequency Detector and Filter
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+, or REFB–) and the FB inputs (FBKA+, FBKA–,
FBKB+, or FBKB–). Correction information is then generated to
control the frequency of the voltage-controlled oscillator (VCO).
These two blocks, along with the VCO, form a PLL that tracks
the incoming REF signal.
The CY7B993V/994V have a flexible REF and FB input scheme.
These inputs allow the use of either differential LVPECL or
single-ended LVTTL inputs. To configure as single-ended LVTTL
inputs, the complementary pin must be left open (internally pulled
to 1.5V). The other input pin can then be used as an LVTTL input.
The REF inputs are also tolerant to hot insertion.
The REF inputs can be changed dynamically. When changing
from one reference input to the other of the same frequency, the
PLL is optimized to ensure that the clock output period is not less
than the calculated system budget (tMIN = tREF (nominal
reference clock period) – tCCJ (cycle-to-cycle jitter) – tPDEV (Max
period deviation)) while reacquiring the lock.
VCO, Control Logic, Divider, and Phase Generator
The VCO accepts analog control inputs from the PLL filter block.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the device.
fNOM is directly related to the VCO frequency. There are two
versions: a low-speed device (CY7B993V) where fNOM ranges
from 12 MHz to 100 MHz, and a high-speed device (CY7B994V)
that ranges from 24 MHz to 200 MHz. The FS setting for each
device is shown in Table 1.
FS[2]
CY7B993V
CY7B994V
fNOM (MHz)
fNOM (MHz)
Min
Max
Min
Max
LOW
12
26
24
52
MID
24
52
48
100
HIGH
48
100
96
200
Time Unit Definition
Selectable skew is in discrete increments of time unit (tU). The
value of a tU is determined by the FS setting and the maximum
nominal output frequency. The equation to be used to determine
the tU value is as follows:
tU = 1/(fNOM*N)
N is a multiplication factor which is determined by the FS setting.
fNOM is nominal frequency of the device. N is defined in Table 2.
Table 2. N Factor Determination
CY7B993V
FS
CY7B994V
N
fNOM (MHz) at
which tU =1.0 ns
N
fNOM (MHz) at
which tU =1.0 ns
64
15.625
32
31.25
MID
32
31.25
16
62.5
HIGH
16
62.5
8
125
LOW
The fNOM frequency is seen on “divide-by-one” outputs. For the
CY7B994V, the upper fNOM range extends from 96 MHz to
200 MHz.
Note
2. The level to be set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO and Phase Generator. fNOM always appears on an output when the
output is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.
Document Number: 38-07127 Rev. *M
Page 7 of 22
CY7B993V/CY7B994V
RoboClock®
Divide and Phase Select Matrix
The Divide and Phase Select Matrix is comprised of five
independent banks: four banks of clock outputs and one bank for
feedback. Each clock output bank has two pairs of low-skew,
high-fanout output buffers ([1:4]Q[A:B][0:1]), two phase function
select inputs ([1:4]F[0:1]), two divider function selects
([1:4]DS[0:1]), and one output disable (DIS[1:4]).
Table 4. Output Divider Function
Function
Selects
[1:4]DS1 [1:4]DS0
and
and
Bank1 Bank2 Bank3 Bank4 Feedback
Bank
FBDS1 FBDS0
The feedback bank has one pair of low-skew, high-fanout output
buffers (QFA[0:1]). One of these outputs may connect to the
selected feedback input (FBK[A:B]±). This feedback bank also
has one phase function select input (FBF0), two divider function
selects FSDS[0:1], and one output disable (FBDIS).
LOW
The phase capabilities that are chosen by the phase function
select pins are shown in Table 3. The divide capabilities for each
bank are shown in Table 4.
Table 3. Output Skew Select Function
Function
Selects
[1:4]F1
LOW
Output Skew Function
[1:4]F0
and Bank1 Bank2 Bank3 Bank4 Feedback
Bank
FBF0
LOW
–4tU
–4tU
–8tU
–8tU
–4tU
LOW
MID
LOW
HIGH
–3tU
–3tu
–7tU
–7tU
NA
–2tU
–2tU
–6tU
–6tU
NA
BK1[3]
NA
MID
LOW
–1tU
–1tU
BK1[3]
MID
MID
0tU
0tU
0tU
0tU
0tu
BK2[3]
NA
NA
MID
HIGH
+1tU
+1tU
BK2[3]
HIGH
LOW
+2tU
+2tU
+6tU
+6tU
HIGH
MID
+3tU
+3tU
+7tU
+7tU
NA
HIGH
HIGH
+4tU
+4tU
+8tU
+8tU
+4tU
Output Divider Function
LOW
/1
/1
/1
/1
/1
LOW
MID
/2
/2
/2
/2
/2
LOW
HIGH
/3
/3
/3
/3
/3
MID
LOW
/4
/4
/4
/4
/4
MID
MID
/5
/5
/5
/5
/5
MID
HIGH
/6
/6
/6
/6
/6
HIGH
LOW
/8
/8
/8
/8
/8
HIGH
MID
/10
/10
/10
/10
/10
HIGH
HIGH
/12
/12
/12
/12
/12
Figure 3 on page 9 illustrates the timing relationship of programmable skew outputs. All times are measured with respect to REF
with the output used for feedback programmed with 0tU skew.
The PLL naturally aligns the rising edge of the FB input and REF
input. If the output used for feedback is programmed to another
skew position, then the whole tU matrix shifts with respect to REF.
For example, if the output used for feedback is programmed to
shift –8tU, then the whole matrix is shifted forward in time by 8tU.
Thus an output programmed with 8tU of skew is effectively
skewed 16tU with respect to REF.
Note
3. BK1, BK2 denotes following the skew setting of Bank1 and Bank2, respectively.
Document Number: 38-07127 Rev. *M
Page 8 of 22
CY7B993V/CY7B994V
RoboClock®
U
U
U
t 0 +5t
t 0 +6t
t 0 +7t
U
U
t 0 +4t
t 0 +8t
U
U
t 0 +2t
t 0 +3t
U
t 0 +1t
t0
t 0 – 1t U
t 0 – 2t U
t 0 – 3t U
t 0 – 4t U
t 0 – 5t U
t 0 – 6t U
t 0 – 7t U
t 0 – 8t U
Figure 3. Typical Outputs with FB Connected to a Zero-Skew Output [4]
FBInput
REFInput
1F[1:0]
2F[1:0]
3F[1:0]
4F[1:0]
(N/A)
LL
–8tU
(N/A)
LM
–7tU
(N/A)
LH
–6tU
LL
(N/A)
–4tU
LM
(N/A)
–3tU
LH
(N/A)
–2tU
ML
(N/A)
–1tU
MM
MM
0t U
MH
(N/A)
+1t U
HL
(N/A)
+2t U
HM
(N/A)
+3t U
HH
(N/A)
+4t U
(N/A)
HL
+6t U
(N/A)
HM
+7t U
(N/A)
HH
+8t U
Output Disable Description
The feedback Divide and Phase Select Matrix Bank has two
outputs, and each of the four Divide and Phase Select Matrix
Banks have four outputs. The outputs of each bank can be
independently put into a HOLD-OFF or high impedance state.
The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS
inputs determines the clock outputs’ state for each bank. When
the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding
bank is enabled. When the DIS[1:4]/FBDIS is HIGH, the outputs
for that bank is disabled to a high impedance (High Z) or
HOLD-OFF state depending on the OUTPUT_MODE input.
Table 5 defines the disabled output functions.
its falling edge. Inverting outputs are driven to a logic HIGH state
on its rising edge. This ensures the output clocks are stopped
without glitch. When a bank of outputs is disabled to High Z state,
the respective bank of outputs go High Z immediately.
Table 5. DIS[1:4]/FBDIS Pin Functionality
OUTPUT_MODE
DIS[1:4]/FBDIS
Output Mode
HIGH/LOW
LOW
ENABLED
HIGH
HIGH
HIGH Z
LOW
HIGH
HOLD-OFF
MID
X
FACTORY TEST
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a maximum
of six output clock cycles from the time when the disable input
(DIS[1:4]/FBDIS) is HIGH. When disabled to the HOLD-OFF
state, non-inverting outputs are driven to a logic LOW state on
Note
4. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
Document Number: 38-07127 Rev. *M
Page 9 of 22
CY7B993V/CY7B994V
RoboClock®
INV3 Pin Function
Bank3 has signal invert capability. The four outputs of Bank3 act
as two pairs of complementary outputs when the INV3 pin is
driven LOW. In complementary output mode, 3QA0 and 3QB0
are non-inverting; 3QA1and 3QB1 are inverting outputs. All four
outputs are inverted when the INV3 pin is driven HIGH. When
the INV3 pin is left in MID, the outputs do not invert. Inversion of
the outputs are independent of the skew and divide functions.
Therefore, clock outputs of Bank3 can be inverted, divided, and
skewed at the same time.
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit (tPD).
When in the locked state, after four or more consecutive
feedback clock cycles with phase-errors, the LOCK output is
forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase-errorless
feedback clock cycles are required to allow the LOCK output to
indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH, a
“Watchdog” circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW. This
time out period is based upon a divided down reference clock.
HIGH. When the DIS4 input is driven HIGH in factory test mode,
all clock outputs go to High Z; after the selected reference clock
pin has five positive transitions, all the internal finite state
machines (FSM) are set to a deterministic state. The
deterministic state of the state machines depend on the
configurations of the divide selects, skew selects, and frequency
select input. All clock outputs stay in high impedance mode and
all FSMs stay in the deterministic state until DIS4 is deasserted.
When DIS4 is deasserted (with OUTPUT_MODE still at MID),
the device re-enters factory test mode.
Safe Operating Zone
Figure 4 illustrates the operating condition at which the device
does not exceed its allowable maximum junction temperature of
150 °C. Figure 4 shows the maximum number of outputs that can
operate at 185 MHz (with 25 pF load and no air flow) or 200 MHz
(with 10 pF load and no air flow) at various ambient
temperatures. At the limit line, all other outputs are configured to
divide-by-two (i.e., operating at 92.5 MHz) or lower frequencies.
The device operates below maximum allowable junction
temperature of 150 °C when its configuration (with the specified
constraints) falls within the shaded region (safe operating zone).
Figure 4 shows that at 85 °C, the maximum number of outputs
that can operate at 200 MHz is 6; and at 70 °C, the maximum
number of outputs that can operate at 185 MHz is 16 (with 25 pF
load and 0-m/s air flow).
Figure 4. Typical Safe Operating Zone
Typical Safe Operating Zone
(25-pF Load, 0-m /s air flow )
This assumes that there is activity on the selected REF input. If
there is no activity on the selected REF input then the LOCK
detect pin may not accurately reflect the state of the internal PLL.
The device enters factory test mode when the OUTPUT_MODE
is driven to MID. In factory test mode, the device operates with
its internal PLL disconnected; input level supplied to the
reference input is used in place of the PLL output. In TEST mode
the selected FB input(s) must be tied LOW. All functions of the
device are still operational in factory test mode except the
internal PLL and output bank disables. The OUTPUT_MODE
input is designed to be a static input. Dynamically toggling this
input from LOW to HIGH may temporarily cause the device to go
into factory test mode (when passing through the MID state).
Factory Test Reset
Ambient Temperature (C)
Factory Test Mode Description
100
95
90
85
80
75
70
Safe Operating Zone
65
60
55
50
2
4
6
8
10
12
14
16
18
Num ber of Outputs at 185 MHz
When in factory test mode (OUTPUT_MODE = MID), the device
can be reset to a deterministic state by driving the DIS4 input
Document Number: 38-07127 Rev. *M
Page 10 of 22
CY7B993V/CY7B994V
RoboClock®
Absolute Maximum Conditions
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.[5]
Storage Temperature ............................... –50 C to +125 C
Ambient Temperature with
Power Applied ......................................... –40 C to +125 C
Supply Voltage to Ground Potential .............–0.5 V to +4.6 V
DC Input Voltage ................................ –0.3 V to VCC + 0.5 V
Output Current into Outputs (LOW) ............................ 40 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 1100V
Latch up Current .................................................. > ±200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
VCC
0 C to +70 C
3.3 V 10%
–40 C to +85C
3.3 V 10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Max
Unit
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH
VOL
IOZ
LVTTL HIGH Voltage
LVTTL LOW Voltage
QFA[0:1], [1:4]Q[A:B][0:1]
VCC = Min, IOH = –30 mA
2.4
–
V
LOCK
IOH = –2 mA, VCC = Min
2.4
–
V
QFA[0:1], [1:4]Q[A:B][0:1]
VCC = Min, IOL = 30 mA
–
0.5
V
LOCK
IOL= 2 mA, VCC = Min
–
0.5
V
–100
100
A
2.0
VCC + 0.3
V
2.0
VCC + 0.3
V
–0.3
0.8
V
High impedance State Leakage Current
LVTTL Compatible Input Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4])
VIH
LVTTL Input HIGH
FBK[A:B]±, REF[A:B]±
Min < VCC < Max
REFSEL, FBSEL, FBDIS,
DIS[1:4]
VIL
LVTTL Input LOW
FBK[A:B]±, REF[A:B]±
Min < VCC < Max
–0.3
0.8
V
II
LVTTL VIN >VCC
FBK[A:B]±, REF[A:B]±
VCC = GND, VIN = 3.63 V
–
100
A
IlH
LVTTL Input HIGH
Current
FBK[A:B]±, REF[A:B]±
VCC = Max, VIN = VCC
–
500
A
–
500
A
–500
–
A
–500
–
A
Min < VCC < Max
0.87 × VCC
–
V
Min < VCC < Max
0.47 × VCC 0.53 × VCC
REFSEL, FBSEL, FBDIS, DIS[1:4]
IlL
LVTTL Input LOW
Current
REFSEL, FBSEL, FBDIS, DIS[1:4] VIN = VCC
FBK[A:B]±, REF[A:B]±
VCC = Max, VIN = GND
REFSEL, FBSEL, FBDIS, DIS[1:4]
Three-level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST))
VIHH
Three-level Input HIGH[6]
MID[6]
VIMM
Three-level Input
VILL
Three-level Input LOW[6]
Min < VCC < Max
–
0.13 × VCC
V
IIHH
Three-level Input HIGH Three-level input pins excl. FBF0
Current
FBF0
VIN = VCC
–
200
A
–
400
A
Three-level Input MID Three-level input pins excl. FBF0
Current
FBF0
VIN = VCC/2
Three-level Input LOW Three-level input pins excl. FBF0
Current
FBF0
VIN = GND
IIMM
IILL
V
–50
50
A
–100
100
A
–200
–
A
–400
–
A
Notes
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all data sheet limits are achieved.
Document Number: 38-07127 Rev. *M
Page 11 of 22
CY7B993V/CY7B994V
RoboClock®
Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
Min
Max
Unit
400
VCC
mV
LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±)
VDIFF
Input Differential Voltage
VIHHP
Highest Input HIGH Voltage
1.0
VCC
V
VILLP
Lowest Input LOW Voltage
GND
VCC – 0.4
V
VCOM
Common Mode Range (crossing voltage)
0.8
VCC
V
Operating Current
ICCI
ICCN
Internal Operating
Current
CY7B993V
Output Current
Dissipation/Pair[8]
CY7B993V
VCC = Max, fMAX[7]
CY7B994V
CY7B994V
VCC = Max,
CLOAD = 25 pF,
RLOAD = 50 at VCC/2,
fMAX
–
250
mA
–
250
mA
–
40
mA
–
50
mA
Notes
7. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B993V, fNOM = 200 MHz for CY7B994V),
and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of
25 pF terminated to 50 at VCC/2.
Document Number: 38-07127 Rev. *M
Page 12 of 22
CY7B993V/CY7B994V
RoboClock®
Capacitance
Parameter
CIN
Description
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Input capacitance
Min
Max
Unit
–
5
pF
Thermal Resistance
Parameter [9]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Thin
100-pin TQFP 100-ball
BGA
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
Unit
51
42
°C/W
11
16
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms [10]
3.3V
OUTPUT
For all other outputs
R1 = 100
CL
R2 = 100
CL < 25 pF to 185 MHz
or 10 pF at 200 MHz
(Includes fixture and
probe capacitance)
For LOCK output only
R1 = 910
R2 = 910
CL < 30 pF
R1
R2
(a) LVTTL AC Test Load
3.3V
2.0V
0.8V
GND
< 1 ns
2.0V
0.8V
< 1 ns
(b) TTL Input Test Waveform
Notes
9. These parameters are guaranteed by design and are not tested.
10. These figures are for illustrations only. The actual ATE loads may vary.
Document Number: 38-07127 Rev. *M
Page 13 of 22
CY7B993V/CY7B994V
RoboClock®
Switching Characteristics
Over the Operating Range [11, 12, 13, 14, 15]
Parameter
fIN
fOUT
CY7B993/4V-2
Description
Clock Input Frequency
Clock Output Frequency
CY7B993/4V-5
Unit
Min
Typ
Max
Min
Typ
Max
CY7B993V
12
–
100
12
–
100
MHz
CY7B994V
24
–
200
24
–
200
MHz
CY7B993V
12
–
100
12
–
100
MHz
CY7B994V
24
–
200
24
–
200
MHz
[16, 17]
tSKEWPR
Matched-Pair Skew
–
–
200
–
–
200
ps
tSKEWBNK
Intrabank Skew [16, 17]
–
–
200
–
–
250
ps
tSKEW0
Output-Output Skew (same frequency and phase, rise to rise, fall
to fall) [16, 17]
–
–
250
–
–
550
ps
tSKEW1
Output-Output Skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall) [16, 17]
–
–
250
–
–
650
ps
tSKEW2
Output-Output Skew (invert to nominal of different banks,
compared banks at same frequency, rising edge to falling edge
aligned, other banks at same frequency) [16, 17]
–
–
250
–
–
700
ps
tSKEW3
Output-Output Skew (all output configurations outside of
tSKEW1and tSKEW2) [16, 17]
–
–
500
–
–
800
ps
tSKEWCPR
Complementary Outputs Skew (crossing to crossing,
complementary outputs of the same bank) [16, 17, 18, 19]
–
–
200
–
–
300
ps
tCCJ1-3
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
–
50
150
–
50
150
ps
Peak
tCCJ4-12
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
–
50
100
–
50
100
ps
Peak
tPD
Propagation Delay, REF to FB Rise
–250
–
250
–500
–
500
ps
Notes
11. This is for non-three level inputs.
12. Assumes 25 pF Max load capacitance up to 185 MHz. At 200 MHz the Max load is 10 pF.
13. Both outputs of pair must be terminated, even if only one is being used.
14. Each package must be properly decoupled.
15. AC parameters are measured at 1.5V unless otherwise indicated.
16. Test Load CL= 25 pF, terminated to VCC/2 with 50up to185 MHz and 10 pF load to 200 MHz.
17. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs
are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
18. Complementary output skews are measured at complementary signal pair intersections.
19. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-07127 Rev. *M
Page 14 of 22
CY7B993V/CY7B994V
RoboClock®
Switching Characteristics (continued)
Over the Operating Range [11, 12, 13, 14, 15]
Parameter
Description
CY7B993/4V-2
CY7B993/4V-5
Min
Typ
Max
Min
Typ
Max
Unit
TTB
Total Timing Budget window (same frequency and phase)[19, 20]
–
–
500
–
–
700
ps
tPDDELTA
Propagation Delay difference between two devices[19]
–
–
200
–
–
200
ps
tREFpwh
REF input (Pulse Width HIGH)
[21]
2.0
–
–
2.0
–
–
ns
tREFpwl
REF input (Pulse Width LOW)[21]
2.0
–
–
2.0
–
–
ns
[22]
tr/tf
Output Rise/Fall Time
0.15
–
2.0
0.15
–
2.0
ns
tLOCK
PLL Lock Time from Power up
–
–
10
–
–
10
ms
tRELOCK1
PLL Relock Time (from same frequency, different phase) with
Stable Power Supply
–
500
–
500
s
tRELOCK2
PLL Relock Time (from different frequency, different phase) with
Stable Power Supply[23]
–
1000
–
1000
s
tODCV
Output duty cycle deviation from 50%[24]
–1.0
1.0
–1.0
1.0
ns
tPWH
Output HIGH time deviation from 50%[25]
–
1.5
–
1.5
ns
tPWL
Output LOW time deviation from
50%[25]
–
2.0
–
2.0
ns
tPDEV
Period deviation when changing from reference to reference[26]
–
0.025
–
0.025
UI
tOAZ
DIS[1:4]/FBDIS HIGH to output high impedance
from ACTIVE[27, 28]
1.0
10
1.0
10
ns
tOAZ
DIS[1:4]/FBDIS LOW to output ACTIVE
from output high impedance [28, 29]
0.5
14
0.5
14
ns
Notes
20. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error. TTB is equal to or smaller than the maximum specified value at a given frequency.
21. Tested initially and after any design or process changes that may affect these parameters.
22. Rise and fall times are measured between 2.0V and 0.8V.
23. fNOM must be within the frequency range defined by the same FS state.
24. AC parameters are measured at 1.5V unless otherwise indicated.
25. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
26. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
27. Test Load CL= 25 pF, terminated to VCC/2 with 50up to185 MHz and 10 pF load to 200 MHz.
28. Measured at 0.5V deviation from starting voltage.
29. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz.
Document Number: 38-07127 Rev. *M
Page 15 of 22
CY7B993V/CY7B994V
RoboClock®
AC Timing Diagrams
Figure 6. AC Timing Diagrams [30]
tREFpwl
QFA0 or
[1:4]Q[A:B]0
tREFpwh
REF
t SKEWPR
t SKEWPR
t PWH
tPD
t PWL
2.0V
FB
QFA1 or
[1:4]Q[A:B]1
0.8V
tCCJ1-3,4-12
Q
[1:4]QA[0:1]
t SKEWBNK
t SKEWBNK
[1:4]QB[0:1]
REF TO DEVICE 1 and 2
tODCV
tPD
tODCV
Q
FB DEVICE1
tPDELTA
tPDELTA
t SKEW0,1
t SKEW0,1
Other Q
FB DEVICE2
tSKEWCPR
COMPLEMENTARY A
Q
tSKEW2
tSKEW2
COMPLEMENTARY B
crossing
crossing
INVERTED Q
Note
30. AC parameters are measured at 1.5V unless otherwise indicated.
Document Number: 38-07127 Rev. *M
Page 16 of 22
CY7B993V/CY7B994V
RoboClock®
Ordering Information
Propagation Max Speed
Delay (ps)
(MHz)
Ordering Code
Package Type
Operating Range
250
200
CY7B994V-2BBI
100-ball Thin BGA
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2BBIT
100-ball Thin BGA – Tape and Reel
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5BBC
100-ball Thin BGA
Commercial, 0 °C to 70 °C
500
200
CY7B994V-5BBCT
100-ball Thin BGA – Tape and Reel
Commercial, 0 °C to 70 °C
250
100
CY7B993V-2AXC
100-pin TQFP
Commercial, 0 °C to 70 °C
250
100
CY7B993V-2AXCT
100-pin TQFP – Tape and Reel
Commercial, 0 °C to 70 °C
250
100
CY7B993V-2AXI
100-pin TQFP
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2AXC
100-pin TQFP
Commercial, 0 °C to 70 °C
250
200
CY7B994V-2AXCT
100-pin TQFP – Tape and Reel
Commercial, 0 °C to 70 °C
250
200
CY7B994V-2AXI
100-pin TQFP
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2AXIT
100-pin TQFP – Tape and Reel
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2BBXI
100-ball Thin BGA
Industrial, –40 °C to 85 °C
250
200
CY7B994V-2BBXIT
100-ball Thin BGA – Tape and Reel
Industrial, –40 °C to 85 °C
500
100
CY7B993V-5AXC
100-pin TQFP
Commercial, 0 °C to 70 °C
500
100
CY7B993V-5AXCT
100-pin TQFP – Tape and Reel
Commercial, 0 °C to 70 °C
500
100
CY7B993V-5AXI
100-pin TQFP
Industrial, –40 °C to 85 °C
500
100
CY7B993V-5AXIT
100-pin TQFP – Tape and Reel
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5AXC
100-pin TQFP
Commercial, 0 °C to 70 °C
500
200
CY7B994V-5AXCT
100-pin TQFP – Tape and Reel
Commercial, 0 °C to 70 °C
500
200
CY7B994V-5BBXI
100-ball Thin BGA
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5BBXIT
100-ball Thin BGA – Tape and Reel
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5AXI
100-pin TQFP
Industrial, –40 °C to 85 °C
500
200
CY7B994V-5AXIT
100-pin TQFP – Tape and Reel
Industrial, –40 °C to 85 °C
Pb-free
Ordering Code Definitions
CY 7B99XV - X
XX
X
X
X
X = blank or T
blank = Standard; T = Tape and Reel
Temperature Range: X = I or C
I = Industrial = –40 °C to 85 °C; C = Commercial = 0 °C to 70 °C
X = Pb-free indicator (blank = leaded)
Package Type: XX = BB or A
A = 100-pin TQFP; BB = 100-ball BGA
Propagation delay: X = 2 or 5
2 = 250 ps max; 5 = 500 ps max
Base part number
Company ID: CY = Cypress
Document Number: 38-07127 Rev. *M
Page 17 of 22
CY7B993V/CY7B994V
RoboClock®
Package Diagrams
Figure 7. 100-pin TQFP (14 × 14 × 1.4 mm) A100SA Package Outline, 51-85048
51-85048 *J
Document Number: 38-07127 Rev. *M
Page 18 of 22
CY7B993V/CY7B994V
RoboClock®
Package Diagrams (continued)
Figure 8. 100-ball Thin BGA (11 × 11 × 1.4 mm) BB100 Package Outline, 51-85107
51-85107 *E
Document Number: 38-07127 Rev. *M
Page 19 of 22
CY7B993V/CY7B994V
RoboClock®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
Ball Grid Array
FS
Frequency Select
°C
degree Celsius
I/O
Input/Output
KHz
kilohertz
LVPECL
Low Voltage Positive Emitter Coupled Logic
K
kilohm
LVTTL
Low Voltage Transistor-Transistor Logic
MHz
megahertz
PLL
Phase-Locked Loop
µA
microampere
TQFP
Thin Quad Flat Pack
mA
milliampere
TTL
Transistor-Transistor Logic
ms
millisecond
VCO
Voltage Controlled Oscillator
mV
millivolt
ns
nanosecond

ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Document Number: 38-07127 Rev. *M
Symbol
Unit of Measure
Page 20 of 22
CY7B993V/CY7B994V
RoboClock®
Document History Page
Document Title: CY7B993V/CY7B994V RoboClock®, High-Speed Multi-Phase PLL Clock Buffer
Document Number: 38-07127
Revision
ECN
Orig. of
Change
Submission
Date
**
109957
SZV
12/16/01
Changed from Spec number: 38-00747 to 38-07127
*A
114376
CTK
05/06/02
Added three industrial packages
*B
116570
HWT
09/04/02
Added TTB Features
Description of Change
*C
122794
RBI
12/14/02
Power up requirements to operating conditions information
*D
123694
RGL
03/04/03
Added Min Fout value of 12 MHz for CY7B993V and 24 MHz for CY7B994V to
switching characteristics table
Corrected prop delay limit parameter from (tPDSL,M,H) to tPD in the Lock Detect
Output Description paragraph
*E
128462
RGL
07/29/03
Added clock input frequency (fin) specifications in the switching characteristics
table
*F
391560
RGL
See ECN
Added Lead-free devices
Added typical values for jitter
*G
2896548
KVM
03/19/10
Changed “Lead-Free” to “Pb-Free” in Ordering Information table.
Removed obsolete part numbers: CY7B993V-2AC, CY7B993V-2ACT,
CY7B993V-2AI, CY7B993V-2AIT, CY7B994V-2AC, CY7B994V-2ACT,
CY7B994V-2BBCT, CY7B994V-2AI, CY7B994V-2AIT, CY7B993V-5AC,
CY7B993V-5ACT, CY7B993V-5AI, CY7B993V-5AIT, CY7B994V-5AC,
CY7B994V-5ACT, CY7B994V-5BBI, CY7B994V-5BBIT, CY7B994V-5AI,
CY7B994V-5AIT and CY7B993V-2AXIT
Added numerical temperature ranges to Ordering Information table
*H
3055192
CXQ
10/11/2010
Removed Part number CY7B994V-5BBXC and CY7B994V-5BBXCT.
Added Ordering Code Definitions.
*I
3076912
CXQ
11/02/2010
Updated Ordering Code Definitions.
*J
3240908
CXQ
04/26/2011
Updated minimum Storage Temperature and 100-pin TQFP package diagram
*K
4196053
CINM
11/19/2013
Updated Package Diagrams:
spec 51-85048 – Changed revision from *E to *H.
spec 51-85107 – Changed revision from *C to *E.
Added Acronyms and Units of Measure.
Updated to new template.
Completing Sunset Review.
*L
4570131
CINM
11/14/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Removed the prune part numbers CY7B994V-2BBXC and
CY7B994V-2BBXCT.
Updated Figure 7 in Package Diagrams:
spec 51-85048 – Changed revision from *H to *I.
*M
5257270
PSR
05/03/2016
Added Thermal Resistance.
Updated Package Diagrams:
spec 51-85048 – Changed revision from *I to *J.
Updated to new template.
Document Number: 38-07127 Rev. *M
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CY7B993V/CY7B994V
RoboClock®
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© Cypress Semiconductor Corporation, 2001-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
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provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
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expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 38-07127 Rev. *M
Revised May 3, 2016
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TTB™ is a trademark of Cypress Semiconductor Corporation. RoboClock and PSoC are the registered trademarks of Cypress Semiconductor Corporation.
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