Document No. 002-02765 Rev. ** ECN #:4903496 Cypress Semiconductor Product Qualification Report QTP# 150502 VERSION ** August, 2015 4Mb F-RAM Memory Product Qualification 130nm Technology, TI Fab CY15B104Q-SXI* 4-Mbit (512 K × 8) Serial (SPI) F-RAM CY15B104Q-PZXI* 4-Mbit (512 K × 8) Serial (SPI) F-RAM CY15B104Q-LHXI* 4-Mbit (512 K × 8) Serial (SPI) F-RAM FOR ANY QUESTIONS ON THIS REPORT, PLEASE CONTACT [email protected] or via a CYLINK CRM CASE Prepared By: Becky Thomas Reliability Engineer Reviewed By: Zhaomin Ji Reliability Manager Approved By: Don Darling Reliability Director Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 1 of 11 Document No. 002-02765 Rev. ** ECN #:4903496 PACKAGE/PRODUCT QUALIFICATION HISTORY QTP Number Description of Qualification Purpose Date 02-60-5112 / 124901 TI Process Qualification 130nm F-RAM Process Aug 2008 / Dec 2012 150502 New Product Qualification, 4Mb F-RAM Memory Aug 2015 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 2 of 11 Document No. 002-02765 Rev. ** ECN #:4903496 PRODUCT DESCRIPTION (for qualification) Qualification Purpose: New Product Qualification, 4Mb F-RAM Memory Marketing Part #: CY15B104Q-SXI*, CY15B104Q-PZXI*, CY15B104Q-LHXI* Device Description: 4Mb F-RAM Serial and Parallel Memory Cypress Division: Cypress Semiconductor Corporation – Memory Products Division (MPD) TECHNOLOGY/FAB PROCESS DESCRIPTION Number of Metal Layers: Proprietary* Metal Composition: Passivation Type and Thickness: Proprietary* Proprietary* Generic Process Technology/Design Rule (-drawn): CMOS / 130nm Gate Oxide Material/Thickness (MOS): Proprietary* Name/Location of Die Fab (prime) Facility: Texas Instruments / Dallas Die Fab Line ID/Wafer Process ID: DMOS 5 / E035.1 *Texas Instruments’ proprietary information is available with signed NDA. PACKAGE AVAILABILITY PACKAGE ASSEMBLY FACILITY SITE 8-pin SOIC UTAC, Thailand (UT) 8-pin PDIP UTAC, Thailand (UT) 8-pin TDFN UTAC, Thailand (UT) Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 3 of 11 Document No. 002-02765 Rev. ** ECN #:4903496 MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION Package Designation: Package Outline, Type, or Name: Mold Compound Name/Manufacturer: SZ820 Mold Compound Flammability Rating: SOIC 8L (208mils) G770HCD / Sumitomo UL-94 Mold Compound Alpha Emission Rate: <0.1 Oxygen Rating Index: >28% 38 Lead Frame Designation: FMP Lead Frame Material: Copper Substrate Material: N/A Lead Finish, Composition / Thickness: Matte Sn Die Backside Preparation Method/Metallization: Backgrind Die Separation Method: Wafer Saw Die Attach Supplier: Henkel Die Attach Material: 8200T Bond Diagram Designation 001-86123 Wire Bond Method: Thermosonic Wire Material/Size: CuPd / 0.8 mil Thermal Resistance Theta JA C/W: 118 C/W Package Cross Section Yes/No: Yes Assembly Process Flow: 001-85398M Name/Location of Assembly (prime) facility: UTAC, Thailand (UT) MSL LEVEL 3 REFLOW PROFILE 260C ELECTRICAL TEST / FINISH DESCRIPTION Test Location: Sort Test: CMI, Cypress Minnesota, USA / Class Test and Finish: UTAC, Thailand Note: Please contact a Cypress Representative for other package availability. Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 4 of 11 Document No. 002-02765 Rev. ** ECN #:4903496 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENTS Stress/Test Data Retention (Plastic) Endurance Test High Temperature Operating Life Early Failure Rate High Temperature Operating Life Latent Failure Rate High Accelerated Saturation Test (HAST) Pressure Cooker Test Temperature Cycle Electrostatic Discharge Human Body Model (ESD-HBM) Electrostatic Discharge Charge Device Model (ESD-CDM) Static Latch up Test Condition (Temp/Bias) Result P/F 125 C, non-biased JESD22-A117 and JESD22-A103 Endurance of all bits (3.6 E4 cycles) + Endurance on 1 byte (2.5 E9 cycles) followed by 168, 500 and 1,000 hour, 125C data retention Dynamic Operating Condition, Vcc = 3.60V, 125 C JESD22-A108 Dynamic Operating Condition, Vcc = 3.60V, 125 C JESD22-A108 JEDEC STD 22-A110: 130C, 85%RH, 3.6V Precondition: JESD22 Moisture Sensitivity Level 3 (192 Hrs., 30 C, 60% RH) JESD22-A102: 121 C, 100%RH, 15 PSIG Precondition: JESD22 Moisture Sensitivity Level 3 (192 Hrs., 30 C, 60% RH) MIL-STD-883C, Method 1010, Condition C, -65 C to 150 C Precondition: JESD22 Moisture Sensitivity Level 3 (192 Hrs., 30 C, 60% RH) (1100V, 2200V, 3300V, 4000V, 5000V) JEDEC EIA/JESD22-A114-B (500V, 750V, 1000V, 1250V, 1500V, 1750V, 2000V) JESD22-C101 ± 140mA at 85C, 5.4V overvoltage; ± 200mA at 85C, 5.94V overvoltage; ± 140mA at125C, 5.4V overvoltage; ± 300mA at 85C, 5.94V overvoltage JESD78B P Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 5 of 11 P P P P P P P P P Document No. 002-02765 Rev. ** ECN #:4903496 RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENTS Stress/Test Acoustic Microscopy Neutron Emission (SER) Test Condition (Temp/Bias) J-STD-020 Precondition: JESD22 Moisture Sensitivity Level 3 (192 Hrs., 30 C, 60% RH) Vccnom, room temperature, JESD89 Result P/F P <0.3 FIT/Mb Neutron Single Latch-up (SEL) Vccmax, Data Sheet max temperature, JESD89 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 6 of 11 No Event Document No. 002-02765 Rev. ** ECN #:4903496 RELIABILITY FAILURE RATE SUMMARY Stress/Test Device Tested/ Device Hours # Fails Activation Energy Thermal AF3 Failure Rate High Temperature Operating Life Early Failure Rate 10,640 Devices 1 N/A N/A 94 PPM High Temperature Operating Life1,2 Long Term Failure Rate 547,000 DHRs* 0 0.7 55 14 FITs 636,000 DHRs *Leverage HTOL data from TI 130nm F-RAM Process QTP#124901 (SPEC#001-85093) 1 2 3 Assuming an ambient temperature of 55C and a junction temperature rise of 15C. Chi-squared 60% estimations used to calculate the failure rate. Thermal Acceleration Factor is calculated from the Arrhenius equation E 1 1 AF = exp A - k T 2 T1 where: EA =The Activation Energy of the defect mechanism. K = Boltzmann's constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at use conditions. Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 7 of 11 Document No. 002-02765 Rev. ** ECN #:4903496 Reliability Test Data QTP #: 150502 Device Fab Lot # Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism 15 15 15 0 0 0 STRESS: ACOUSTIC Microscopy, Before and After MSL3 Preconditioning CY15B104Q-LHXIES CY15B104Q-SXI CY15B104Q-SXI 4516569 4519064 4520727 611512437 611516600 611518815 UTAC - UT UTAC - UT UTAC - UT COMP COMP COMP STRESS: HIGH TEMPERATURE OPERATING LIFE- EARLY FAILURE RATE (125C, 96 hours, 3.60V) CY15B104Q-LHXIES CY15B104Q-SXIES CY15B104Q-SXIES CY15B104Q-LHXIES CY15B104Q-SXIES CY15B104Q-SXIES CY15B104Q-SXIES 4516569 4516569 4519064 4519064 4520727 4520727 4526146 611512437 611512433 611516600 611521518 611518815 611519376 611523035 UTAC - UT UTAC - UT UTAC - UT UTAC - UT UTAC - UT UTAC - UT UTAC - UT 96 96 96 96 96 96 96 799 1000 2998 800 3000 542 1500 0 0 1 0 0 0 0 ISB failure, FA#S1526012* STRESS: HIGH TEMPERATURE OPERATING LIFE- LATENT FAILURE RATE (125C, 3.60V) CY15B104Q-LHXIES CY15B104Q-LHXIES 4516569 4516569 611512437 611512437 UTAC - UT UTAC - UT 168 1,000 116 116 0 0 CY15B104Q-LHXIES CY15B104Q-LHXIES 4516569 4516569 611512433 611512433 UTAC - UT UTAC - UT 168 1,000 120 120 0 0 CY15B104Q-SXIES 4519064 611516600 UTAC - UT 1,000 200 0 CY15B104Q-SXIES 4520727 611518815 UTAC - UT 1,000 200 0 STRESS: DATA RETENTION (125C) CY15B104Q-LHXIES CY15B104Q-LHXIES 4516569 4516569 611512437 611512437 UTAC - UT UTAC - UT 500 1000 80 80 0 0 CY15B104Q-SXIES CY15B104Q-SXIES 4519064 4519064 611516600 611516600 UTAC - UT UTAC - UT 500 1,000 80 80 0 0 CY15B104Q-SXIES 4520727 611518815 UTAC - UT 1,000 80 0 STRESS: ENDURANCE- 3.6 E4 cycles 100% of Bits + 2.5 E9 cycles 1 Byte Followed By 1,000 hour Data Retention at 125C CY15B104Q-SXIES CY15B104Q-SXIES CY15B104Q-SXIES CY15B104Q-SXIES 4516569 4516569 4516569 4516569 611512433 611512433 611512433 611512433 STRESS: ESD- CHARGED DEVICE MODEL (500V) CY15B104Q-LHXIES 4516569 611512437 CY15B104Q-SXIES 4516569 611512433 CY15B104Q-PZXIES 4516569 611512435 UTAC - UT UTAC - UT UTAC - UT UTAC - UT CYCLING 168 500 1000 85 85 85 85 0 0 0 0 UTAC - UT UTAC - UT UTAC - UT COMP COMP COMP 9 9 9 0 0 0 *Note: FA# S1526012 found a fab defect that caused a leakage path between a M5 VSS bus and a M4 VDD power bus. CAR# 201532006 was issued to TI DMOS 5 fab, and TI has reviewed the history of the manufacturing lot and believes that this is a random defect. Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 8 of 11 Document No. 002-02765 Rev. ** ECN #:4903496 Reliability Test Data QTP #: 150502 Device Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: ESD- CHARGED DEVICE MODEL (750V) CY15B104Q-LHXIES 4516569 611512437 CY15B104Q-SXIES 4516569 611512433 CY15B104Q-PZXIES 4516569 611512435 Fab Lot # UTAC - UT UTAC - UT UTAC - UT COMP COMP COMP 3 3 3 0 0 0 STRESS: ESD- CHARGED DEVICE MODEL (1,000V) CY15B104Q-LHXIES 4516569 611512437 CY15B104Q-SXIES 4516569 611512433 CY15B104Q-PZXIES 4516569 611512435 UTAC - UT UTAC - UT UTAC - UT COMP COMP COMP 3 3 3 0 0 0 STRESS: ESD- CHARGED DEVICE MODEL (1,250V) CY15B104Q-LHXIES 4516569 611512437 CY15B104Q-SXIES 4516569 611512433 CY15B104Q-PZXIES 4516569 611512435 UTAC - UT UTAC - UT UTAC - UT COMP COMP COMP 3 3 3 0 0 0 STRESS: ESD- CHARGED DEVICE MODEL (1,500V) CY15B104Q-LHXIES 4516569 611512437 CY15B104Q-SXIES 4516569 611512433 CY15B104Q-PZXIES 4516569 611512435 UTAC - UT UTAC - UT UTAC - UT COMP COMP COMP 3 3 3 0 0 0 STRESS: ESD- CHARGED DEVICE MODEL (1,750V) CY15B104Q-LHXIES 4516569 611512437 CY15B104Q-SXIES 4516569 611512433 CY15B104Q-PZXIES 4516569 611512435 UTAC - UT UTAC - UT UTAC - UT COMP COMP COMP 3 3 3 0 0 0 STRESS: ESD- CHARGED DEVICE MODEL (2,000V) CY15B104Q-LHXIES 4516569 611512437 CY15B104Q-SXIES 4516569 611512433 CY15B104Q-PZXIES 4516569 611512435 UTAC - UT UTAC - UT UTAC - UT COMP COMP COMP 3 3 3 0 0 0 UTAC - UT COMP 3 0 UTAC - UT COMP 8 0 UTAC - UT COMP 3 0 UTAC - UT COMP 3 0 UTAC - UT COMP 3 0 STRESS: ESD-HUMAN BODY CIRCUIT (1,100V) CY15B104Q-LHXIES 4516569 611512437 STRESS: ESD-HUMAN BODY CIRCUIT (2,200V) CY15B104Q-LHXIES 4516569 611512437 STRESS: ESD-HUMAN BODY CIRCUIT (3,300V) CY15B104Q-LHXIES 4516569 611512437 STRESS: ESD-HUMAN BODY CIRCUIT (4,000V) CY15B104Q-LHXIES 4516569 611512437 STRESS: ESD-HUMAN BODY CIRCUIT (5,000V) CY15B104Q-LHXIES 4516569 611512437 Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 9 of 11 Document No. 002-02765 Rev. ** ECN #:4903496 Reliability Test Data QTP #: 150502 Device Fab Lot # Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: STATIC LATCH-UP TESTING (85C, ±140mA, 5.4V) CY15B104Q-LHXIES 4516569 611512437 UTAC - UT COMP 6 0 COMP 3 0 COMP 3 0 COMP 3 0 STRESS: STATIC LATCH-UP TESTING (85C, ±200mA, 5.94V) CY15B104Q-LHXIES 4516569 611512437 UTAC - UT STRESS: STATIC LATCH-UP TESTING (125C, ±140mA, 5.4V) CY15B104Q-LHXIES 4516569 611512437 UTAC - UT STRESS: STATIC LATCH-UP TESTING (85C, ±300mA, 5.94V) CY15B104Q-LHXIES 4516569 611512437 UTAC - UT STRESS: TEMPERATURE CYCLE, CONDITION C (-65C TO 150C), with MSL3 Preconditioning CY15B104Q-LHXIES 4516569 611512437 UTAC - UT 500 80 CY15B104Q-LHXIES 4516569 611512437 UTAC - UT 1,000 80 0 0 CY15B104Q-SXIES CY15B104Q-SXIES 4519064 4519064 611516600 611516600 UTAC - UT UTAC - UT 500 1,000 80 80 0 0 CY15B104Q-LHXIES CY15B104Q-LHXIES 4519064 4519064 611521518 611521518 UTAC - UT UTAC - UT 500 1,000 80 80 0 0 STRESS: HIGHLY ACCELLERATED SATURATION TEST (130C, 85%RH, 3.6V) with MSL3 Preconditioning CY15B104Q-LHXIES 4516569 611512437 UTAC - UT 96 28 0 CY15B104Q-LHXIES 4516569 611512437 UTAC - UT 128 28 0 CY15B104Q-SXIES CY15B104Q-SXIES 4519064 4519064 611516600 611516600 UTAC - UT UTAC - UT 96 128 28 28 0 0 CY15B104Q-LHXIES CY15B104Q-LHXIES 4519064 4519064 611521518 611521518 UTAC - UT UTAC - UT 96 128 28 28 0 0 STRESS: PRESSURE COOKER TEST (121C, 100%RH) with MSL3 Preconditioning CY15B104Q-LHXIES 4516569 611512437 UTAC - UT 168 80 0 CY15B104Q-SXIES 4519064 611516600 UTAC - UT 168 80 0 UTAC - UT COMP 3 0 UTAC - UT COMP 3 0 STRESS: Neutron Emission (SER) FM25V20A-G STRESS: Neutron Single Latch-up (SEL) FM25V20A-G Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 10 of 11 Document No.002-02765 Rev. ** ECN # 4903496 Document History Page Document Title: Document Number: QTP#150502: PRODUCT QUALIFICATION REPORT, 4MB SERIAL (SPI) F-RAM MEMORY 002-02765 ECN Orig. of Rev. No. Change ** 4903496 BECK Description of Change Initial Release Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 11 of 11