ON Semiconductor MJE13007 SWITCHMODE NPN Bipolar Power Transistor For Switching Power Supply Applications The MJE13007 is designed for high–voltage, high–speed power switching inductive circuits where fall time is critical. It is particularly suited for 115 and 220 V switchmode applications such as Switching Regulators, Inverters, Motor Controls, Solenoid/Relay drivers and Deflection circuits. • VCEO(sus) 400 V • Reverse Bias SOA with Inductive Loads @ TC = 100°C • 700 V Blocking Capability • SOA and Switching Applications Information • Standard TO–220 POWER TRANSISTOR 8.0 AMPERES 400 VOLTS 80 WATTS MAXIMUM RATINGS Rating Symbol MJE13007 Unit VCEO 400 Vdc Collector–Emitter Breakdown Voltage VCES 700 Vdc Emitter–Base Voltage VEBO 9.0 Vdc Collector Current — Continuous Collector Current — Peak (1) IC ICM 8.0 16 Adc Base Current — Continuous Base Current — Peak (1) IB IBM 4.0 8.0 Adc Emitter Current — Continuous Emitter Current — Peak (1) IE IEM 12 24 Adc Total Device Dissipation @ TC = 25°C Derate above 25°C PD 80 0.64 Watts W/°C TJ, Tstg – 65 to 150 °C RθJC RθJA °1.56° °62.5° °C/W TL 260 °C Collector–Emitter Sustaining Voltage Operating and Storage Temperature THERMAL CHARACTERISTICS Thermal Resistance — Junction to Case — Junction to Ambient Maximum Lead Temperature for Soldering Purposes: 1/8″ from Case for 5 Seconds CASE 221A–09 TO–220AB MJE13007 (1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle ≤ 10%. *Measurement made with thermocouple contacting the bottom insulated mounting surface of the *package (in a location beneath the die), the device mounted on a heatsink with thermal grease applied *at a mounting torque of 6 to 8•lbs. Semiconductor Components Industries, LLC, 2001 May, 2001 – Rev. 3 1 Publication Order Number: MJE13007/D MJE13007 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit VCEO(sus) 400 — — Vdc — — — — 0.1 1.0 — — 100 *OFF CHARACTERISTICS Collector–Emitter Sustaining Voltage (IC = 10 mA, IB = 0) Collector Cutoff Current (VCES = 700 Vdc) (VCES = 700 Vdc, TC = 125°C) ICES Emitter Cutoff Current (VEB = 9.0 Vdc, IC = 0) IEBO mAdc µAdc SECOND BREAKDOWN Second Breakdown Collector Current with Base Forward Biased IS/b See Figure 6 Clamped Inductive SOA with Base Reverse Biased — See Figure 7 *ON CHARACTERISTICS DC Current Gain (IC = 2.0 Adc, VCE = 5.0 Vdc) (IC = 5.0 Adc, VCE = 5.0 Vdc) hFE — 8.0 5.0 — — 40 30 — — — — — — — — 1.0 2.0 3.0 3.0 — — — — — — 1.2 1.6 1.5 fT 4.0 14 — MHz Cob — 80 — pF td — 0.025 0.1 µs tr — 0.5 1.5 ts — 1.8 3.0 tf — 0.23 0.7 Collector–Emitter Saturation Voltage (IC = 2.0 Adc, IB = 0.4 Adc) (IC = 5.0 Adc, IB = 1.0 Adc) (IC = 8.0 Adc, IB = 2.0 Adc) (IC = 5.0 Adc, IB = 1.0 Adc, TC = 100°C) VCE(sat) Base–Emitter Saturation Voltage (IC = 2.0 Adc, IB = 0.4 Adc) (IC = 5.0 Adc, IB = 1.0 Adc) (IC = 5.0 Adc, IB = 1.0 Adc, TC = 100°C) VBE(sat) Vdc Vdc DYNAMIC CHARACTERISTICS Current–Gain — Bandwidth Product (IC = 500 mAdc, VCE = 10 Vdc, f = 1.0 MHz) Output Capacitance (VCB = 10 Vdc, IE = 0, f = 0.1 MHz) SWITCHING CHARACTERISTICS Resistive Load (Table 1) Delay Time Rise Time Storage Time (VCC = 125 Vdc, IC = 5.0 A, IB1 = IB2 = 1.0 1 0 A, A tp = 25 µs µs, Duty Cycle ≤ 1.0%) Fall Time Inductive Load, Clamped (Table 1) Voltage Storage Time VCC = 15 Vdc, IC = 5.0 A Vclamp = 300 Vdc TC = 25°C TC = 100°C tsv — — 1.2 1.6 2.0 3.0 µs Crossover Time IB(on) = 1.0 A, IB(off) = 2.5 A LC = 200 µH TC = 25°C TC = 100°C tc — — 0.15 0.21 0.30 0.50 µs TC = 25°C TC = 100°C tfi — — 0.04 0.10 0.12 0.20 µs Fall Time * Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%. http://onsemi.com 2 MJE13007 VCE(sat), COLLECTOR-EMITTER SATURATION VOLTAGE (VOLTS) VBE(sat), BASE-EMITTER SATURATION VOLTAGE (VOLTS) 1.4 IC/IB = 5 1.2 1 0.8 TC = -40°C IC/IB = 5 2 1 0.5 TC = -40°C 0.1 25°C 0.05 100°C 0.4 0.01 0.02 5 0.2 25°C 0.6 10 0.05 0.1 0.2 0.5 1 2 5 0.02 0.01 0.01 0.02 10 100°C 0.05 0.1 0.2 0.5 1 2 5 10 IC, COLLECTOR CURRENT (AMPS) Figure 1. Base–Emitter Saturation Voltage Figure 2. Collector–Emitter Saturation Voltage VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) IC, COLLECTOR CURRENT (AMPS) 3 TJ = 25°C 2.5 2 1.5 IC = 8 A IC = 5 A 1 IC = 3 A IC = 1 A 0.5 0 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 5 10 IB, BASE CURRENT (AMPS) Figure 3. Collector Saturation Region 100 10000 C, CAPACITANCE (pF) hFE , DC CURRENT GAIN 25°C 10 40°C VCE = 5 V 1 0.01 TJ = 25°C Cib TJ = 100°C 0.1 1 10 1000 Cob 100 10 0.1 1 10 100 IC, COLLECTOR CURRENT (AMPS) VR, REVERSE VOLTAGE (VOLTS) Figure 4. DC Current Gain Figure 5. Capacitance http://onsemi.com 3 1000 MJE13007 10 Extended SOA @ 1 µs, 10 µs 20 10 5 IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS) 100 50 1 µs 10 µs TC = 25°C 2 1 0.5 DC 1 ms 5 ms 0.2 0.1 0.05 BONDING WIRE LIMIT THERMAL LIMIT SECOND BREAKDOWN LIMIT CURVES APPLY BELOW RATED VCEO 0.02 0.01 10 8 6 TC ≤ 100°C GAIN ≥ 4 LC = 500 µH 4 VBE(off) -5 V 2 0 50 70 100 200 300 500 1000 20 30 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 7. Maximum Reverse Bias Switching Safe Operating Area Figure 6. Maximum Forward Bias Safe Operating Area POWER DERATING FACTOR 1 There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC — VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 6 is based on TC = 25°C; TJ(pk) is variable depending on power level. Second breakdown pulse limits are valid for duty cycles to 10% but must be derated when TC ≥ 25°C. Second breakdown limitations do not derate the same as thermal limitations. Allowable current at the voltages shown on Figure 6 may be found at any case temperature by using the appropriate curve on Figure 8. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. Use of reverse biased safe operating area data (Figure 7) is discussed in the applications information section. SECOND BREAKDOWN DERATING 0.8 0.6 THERMAL DERATING 0.4 0.2 0 20 40 60 80 100 120 140 160 TC, CASE TEMPERATURE (°C) Figure 8. Forward Bias Power Derating r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0V -2 V 100 200 300 400 500 600 700 800 VCEV, COLLECTOR-EMITTER CLAMP VOLTAGE (VOLTS) 0 1 0.7 0.5 D = 0.5 D = 0.2 0.2 D = 0.1 0.1 0.07 0.05 0.02 P(pk) D = 0.05 t1 D = 0.02 t2 D = 0.01 0.01 0.01 0.02 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.05 0.1 0.2 0.5 1 2 5 10 20 t, TIME (msec) Figure 9. Typical Thermal Response for MJE13007 http://onsemi.com 4 RθJC(t) = r(t) RθJC RθJC = 1.56°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RθJC(t) 50 100 200 500 10k MJE13007 SPECIFICATION INFORMATION FOR SWITCHMODE APPLICATIONS INTRODUCTION at 25°C and 100°C. Increasing the reverse bias will give some improvement in device blocking capability. The sustaining or active region voltage requirements in switching applications occur during turn–on and turn–off. If the load contains a significant capacitive component, high current and voltage can exist simultaneously during turn–on and the pulsed forward bias SOA curves (Figure 6) are the proper design limits. For inductive loads, high voltage and current must be sustained simultaneously during turn–off, in most cases, with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. This can be accomplished by several means such as active clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as a Reverse Bias Safe Operating Area (Figure 7) which represents voltage–current conditions that can be sustained during reverse biased turn–off. This rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. The primary considerations when selecting a power transistor for SWITCHMODE applications are voltage and current ratings, switching speed, and energy handling capability. In this section, these specifications will be discussed and related to the circuit examples illustrated in Table 2.(1) VOLTAGE REQUIREMENTS Both blocking voltage and sustaining voltage are important in SWITCHMODE applications. Circuits B and C in Table 2 illustrate applications that require high blocking voltage capability. In both circuits the switching transistor is subjected to voltages substantially higher than VCC after the device is completely off (see load line diagrams at IC = Ileakage ≈ 0 in Table 2). The blocking capability at this point depends on the base to emitter conditions and the device junction temperature. Since the highest device capability occurs when the base to emitter junction is reverse biased (VCEV), this is the recommended and specified use condition. Maximum I CEV at rated VCEV is specified at a relatively low reverse bias (1.5 Volts) both (1) For detailed information on specific switching applications, see (1) ON Semiconductor Application Note AN719, AN873, AN875, AN951. http://onsemi.com 5 MJE13007 Table 1. Test Conditions For Dynamic Performance RESISTIVE SWITCHING REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING VCC TEST CIRCUITS +15 V 150Ω 3W 1 µF MTP8P10 MTP8P10 100Ω 3W MUR105 +10V MJE210 50Ω MUR8100E RB1 RC IC A RB2 IB IB 150Ω 3W 500 µF +125 V L MPF930 MPF930 COMMON Vclamp = 300 Vdc TUT RB SCOPE 5.1 k D 1 VCE TUT 51 MTP12N10 Voff -4 V 1 µF CIRCUIT VALUES V(BR)CEO(sus) TEST WAVEFORMS 100 µF L = 10 mH RB2 = 8 VCC = 20 Volts IC(pk) = 100 mA Inductive Switching L = 200 mH RB2 = 0 VCC = 15 Volts RB1 selected for desired IB1 tf CLAMPED tf UNCLAMPED ≈ t2 IC ICM t1 tf Vclamp t2 t TYPICAL WAVEFORMS t1 ADJUSTED TO OBTAIN IC Lcoil (ICM) t1 ≈ VCC t2 ≈ VCEM VCC = 125 V RC = 25 Ω D1 = 1N5820 OR EQUIV. L = 500 mH RB2 = 0 VCC = 15 Volts RB1 selected for desired IB1 t VCE TIME RBSOA Lcoil (ICM) Vclamp TEST EQUIPMENT SCOPE TEKTRONIX 475 OR EQUIVALENT VCE PEAK 0 VCE IB1 IB http://onsemi.com 6 25 µs +11 V IB2 9V tr, tf < 10 ns DUTY CYCLE = 1.0% RB AND RC ADJUSTED FOR DESIRED IB AND IC MJE13007 VOLTAGE REQUIREMENTS (continued) SWITCHING TIME NOTES In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage waveforms since they are in phase. However, for inductive loads which are common to SWITCHMODE power supplies and any coil driver, current and voltage waveforms are not in phase. Therefore, separate measurements must be made on each waveform to determine the total switching time. For this reason, the following new terms have been defined. tsv = Voltage Storage Time, 90% IB1 to 10% Vclamp trv = Voltage Rise Time, 10–90% Vclamp tfi = Current Fall Time, 90–10% IC tti = Current Tail, 10–2% IC tc = Crossover Time, 10% Vclamp to 10% IC An enlarged portion of the turn–off waveforms is shown in Figure 12 to aid in the visual identity of these terms. For the designer, there is minimal switching loss during storage time and the predominant switching power losses occur during the crossover interval and can be obtained using the standard equation from AN222A: PSWT = 1/2 VCCIC(tc) f Typical inductive switching times are shown in Figure 13. In general, trv + tfi ≅ tc. However, at lower test currents this relationship may not be valid. As is common with most switching transistors, resistive switching is specified at 25°C and has become a benchmark for designers. However, for designers of high frequency converter circuits, the user oriented specifications which make this a “SWITCHMODE” transistor are the inductive switching speeds (tc and tsv) which are guaranteed at 100°C. In the four application examples (Table 2) load lines are shown in relation to the pulsed forward and reverse biased SOA curves. In circuits A and D, inductive reactance is clamped by the diodes shown. In circuits B and C the voltage is clamped by the output rectifiers, however, the voltage induced in the primary leakage inductance is not clamped by these diodes and could be large enough to destroy the device. A snubber network or an additional clamp may be required to keep the turn–off load line within the Reverse Bias SOA curve. Load lines that fall within the pulsed forward biased SOA curve during turn–on and within the reverse bias SOA curve during turn–off are considered safe, with the following assumptions: 1. The device thermal limitations are not exceeded. 2. The turn–on time does not exceed 10 µs (see standard pulsed forward SOA curves in Figure 6). 3. The base drive conditions are within the specified limits shown on the Reverse Bias SOA curve (Figure 7). CURRENT REQUIREMENTS An efficient switching transistor must operate at the required current level with good fall time, high energy handling capability and low saturation voltage. On this data sheet, these parameters have been specified at 5.0 amperes which represents typical design conditions for these devices. The current drive requirements are usually dictated by the VCE(sat) specification because the maximum saturation voltage is specified at a forced gain condition which must be duplicated or exceeded in the application to control the saturation voltage. SWITCHING REQUIREMENTS In many switching applications, a major portion of the transistor power dissipation occurs during the fall time (tfi). For this reason considerable effort is usually devoted to reducing the fall time. The recommended way to accomplish this is to reverse bias the base–emitter junction during turn–off. The reverse biased switching characteristics for inductive loads are shown in Figures 12 and 13 and resistive loads in Figures 10 and 11. Usually the inductive load components will be the dominant factor in SWITCHMODE applications and the inductive switching data will more closely represent the device performance in actual application. The inductive switching characteristics are derived from the same circuit used to specify the reverse biased SOA curves, (see Table 1) providing correlation between test procedures and actual use conditions. http://onsemi.com 7 MJE13007 SWITCHING PERFORMANCE 10000 7000 5000 VCC = 125 V IC/IB = 5 IB(on) = IB(off) TJ = 25°C PW = 25 µs tr t, TIME (ns) 1000 100 VCC = 125 V IC/IB = 5 IB(on) = IB(off) TJ = 25°C PW = 25 µs ts 2000 1000 700 500 tf 200 td 10 1 2 3 4 5 6 IC, COLLECTOR CURRENT (AMP) 7 100 8 9 10 1 2 3 4 5 6 IC, COLLECTOR CURRENT (AMP) Figure 10. Turn–On Time (Resistive Load) 10000 IC 90% Vclamp tsv 90% IC tfi trv Vclamp IB 10% Vclamp 90% IB1 10% IC IC/IB = 5 IB(off) = IC/2 Vclamp = 300 V LC = 200 µH VCC = 15 V TJ = 25°C 5000 2000 tti tc Vclamp 7 8 9 10 Figure 11. Turn–Off Time (Resistive Load) t, TIME (ns) t, TIME (ns) 10000 2% IC 1000 500 tsv tc 200 100 tfi 50 20 10 0.1 TIME 0.2 0.3 0.5 0.7 1 2 3 5 7 IC, COLLECTOR CURRENT (AMP) Figure 12. Inductive Switching Measurements Figure 13. Typical Inductive Switching Times http://onsemi.com 8 10 MJE13007 Table 2. Applications Examples of Switching Circuits CIRCUIT LOAD LINE DIAGRAMS SERIES SWITCHING REGULATOR TURN-ON (FORWARD BIAS) SOA ton ≤ 10 µs VO VCC COLLECTOR CURRENT 16 A A PD = 3200 W 2 ton TURN-OFF (REVERSE BIAS) SOA 1.5 V ≤ VBE(off) ≤ 9 V 300 V 8A N COLLECTOR CURRENT VO TURN-OFF 400 V 1 VCC 700 V 1 VCC COLLECTOR VOLTAGE 1 See AN569 for Pulse Power Derating Procedure. 16 A TURN-ON (FORWARD BIAS) SOA ton ≤ 10 µs IC VCC + N (Vo) COLLECTOR CURRENT VCC VCE VCC + N (Vo) VCC 400 V 1 700 V 1 COLLECTOR VOLTAGE TURN-ON (FORWARD BIAS) SOA ton ≤ 10 µs t IC DUTY CYCLE ≤ 10% PD = 3200 W 2 TC = 100°C 8A TURN-OFF (REVERSE BIAS) SOA 1.5 V ≤ VBE(off) ≤ 9 V TURN-ON 1 VCE 2 VCC DUTY CYCLE ≤ 10% 2 VCC TURN-OFF VCC 400 V 1 700 V 1 t COLLECTOR VOLTAGE See AN569 for Pulse Power Derating Procedure. TURN-ON (FORWARD BIAS) SOA ton ≤ 10 µs 16 A IC DUTY CYCLE ≤ 10% SOLENOID COLLECTOR CURRENT TC = 100°C D t VCC Notes: VCC toff ton 300 V + SOLENOID DRIVER t LEAKAGE SPIKE See AN569 for Pulse Power Derating Procedure. 16 A VO VCC + N (Vo) + LEAKAGE SPIKE TURN-ON Notes: C DUTY CYCLE ≤ 10% TURN-OFF + VCC PUSH–PULL INVERTER/CONVERTER toff ton TURN-OFF (REVERSE BIAS) SOA 1.5 V ≤ VBE(off) ≤ 9 V 300 V 8A t TIME PD = 3200 W 2 TC = 100°C 1 t TIME VCE DUTY CYCLE ≤ 10% VCC toff DUTY CYCLE ≤ 10% TURN-ON Notes: B IC DUTY CYCLE ≤ 10% TC = 100°C + FLYBACK INVERTER TIME DIAGRAMS PD = 3200 W 2 300 V 8A TURN-OFF (REVERSE BIAS) SOA 1.5 V ≤ VBE(off) ≤ 9 V DUTY CYCLE ≤ 10% TURN-OFF VCC 400 V 1 700 V 1 COLLECTOR VOLTAGE Notes: 1 toff t VCE VCC TURN-ON + ton See AN569 for Pulse Power Derating Procedure. http://onsemi.com 9 t MJE13007 PACKAGE DIMENSIONS TO–220AB CASE 221A–09 ISSUE AA –T– B SEATING PLANE C F T S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q 1 2 3 U H K Z L R V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. J G D N http://onsemi.com 10 INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04 MJE13007 Notes http://onsemi.com 11 MJE13007 SWITCHMODE is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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