RLP1N06CLE Data Sheet July 1999 1A, 55V, 0.750 Ohm,Voltage Clamping, Current Limited, N-Channel Power MOSFET • 1A, 55V Formerly developmental type TA09880. PACKAGE TO-220AB • rDS(ON) = 0.750Ω • ILIMIT at 150oC = 1.1A to 1.5A Maximum • Built-in Voltage Clamp • Built-in Current Limiting • ESD Protected, 2kV Minimum • Controlled Switching Limits EMI and RFI • 175oC Rated Junction Temperature • Logic Level Gate • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information RLP1N06CLE 2839.4 Features The RLP1N06CLE is an intelligent monolithic power circuit which incorporates a lateral bipolar transistor, resistors, zener diodes, and a PowerMOS transistor. The current limiting of this device allows it to be used safely in circuits where it is anticipated that a shorted load condition may be encountered. The drain to source voltage clamping offers precision control of the circuit voltage when switching inductive loads. Logic level gates allow this device to be fully biased on with only 5V from gate to source. Input protection is provided for ESD up to 2kV. PART NUMBER File Number BRAND Symbol L1N06CLE D NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 6-428 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RLP1N06CLE TC = 25oC, Unless Otherwise Specified Absolute Maximum Ratings Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage (RGS = 20kΩ, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Electrostatic Voltage at TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Gate to Source Voltage (Reverse Voltage Gate Bias Not Allowed) . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Power Dissipation Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RLP1N06CLE 55 55 2 Self Limited 5.5 36 0.24 -55 to 175 UNITS V V kV 300 260 oC oC V W W/oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 20mA, VGS = 0V (Figure 7) 55 - 70 V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 8) 1 - 2.5 V TC = 25oC - - 5 µA TC = 150oC - - 20 µA TC = 25oC TC = 150oC TC = 25oC - - 5 µA - - 20 µA - - 0.750 Ω TC = 150oC - - 1.500 Ω TC = 25oC 1.8 - 3 A TC = 150oC 0.9 - 1.5 A - - 6.5 µs - - 1.5 µs Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Limiting Current IGSS rDS(ON) IDS(LIM) Turn-On Time t(ON) Turn-On Delay Time td(ON) VGS = 5V ID = 1A, VGS = 5V (Figure 6) VDS = 15V, VGS = 5V (Figure 2) VDD = 30V, ID = 1A, VGS = 5V, RGS = 25Ω RL = 30Ω tr 1 - 5 µs td(OFF) - - 7.5 µs Rise Time Turn-Off Delay Time VDS = 45V, VGS = 0V tf 1 - 5 µs Turn-Off Time t(OFF) - - 12.5 µs Thermal Resistance Junction to Case RθJC - - 4.17 oC/W Thermal Resistance Junction to Ambient RθJA TO-220AA - - 62 oC/W Electrostatic Voltage ESD Human Model (100pF, 1.5kΩ) MIL-STD-883B (Category B2) 2000 - - V MIN TYP MAX Fall Time Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Reverse Recovery Time SYMBOL TEST CONDITIONS VSD ISD = 1A - - 1.5 V trr ISD = 1A - - 1 ms NOTES: 2. Pulsed: pulse duration = 80µs maximum, duty cycle = 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. 6-429 UNITS RLP1N06CLE Typical Performance Curves Unless Otherwise Specified 2.0 NORMALIZED DRAIN CURRENT POWER DISSIPATION MULTIPLIER 1.2 1.0 0.8 0.6 0.4 0.2 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS = 10V, VGS = 5V 1.5 1.0 0.5 0 0 125 50 75 100 TC , CASE TEMPERATURE (oC) 25 0 -50 175 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 100µs 1ms 1 10ms DC OPERATION IN THIS AREA LIMITED BY IDS(LIM) VDSS MAX = 55V 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1.5 VGS = 6V VGS = 5V 1.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0.5 0 100 VGS = 4V VGS = 3V 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 FIGURE 4. SATURATION CHARACTERISTICS 3.0 3.0 VDS >> IDS x rDS(ON) PULSE DURATION = 80µs 2.5 DUTY CYCLE = 0.5% MAX -25oC 2.0 25oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE IDS(ON), DRAIN TO SOURCE CURRENT (A) 175 VGS = 7V FIGURE 3. FORWARD BIAS SAFE OPERATING AREA 1.5 1.0 150oC 0.5 0 150 2.0 0.1 1 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 2.5 TJ = MAX RATED TC = 25oC OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0 FIGURE 2. NORMALIZED CURRENT LIMIT vs CASE TEMPERATURE IDS, DRAIN TO SOURCE CURRENT (A) IDS, DRAIN TO SOURCE CURRENT (A) 10 -25 0 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 5. TRANSFER CHARACTERISTICS 6-430 6 VGS = 5V, ID = 0.5A PULSE DURATION = 80µs 2.5 DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 0.5 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (oC) 150 FIGURE 6. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 175 RLP1N06CLE Typical Performance Curves Unless Otherwise Specified (Continued) 2.0 NORMALIZED GATE THRESHOLD VOLTAGE 2.0 ID = 20mA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS ID = 250µA 1.6 1.2 0.8 0.4 0 -50 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (oC) 150 1.5 1.0 0.5 0 -50 175 FIGURE 7. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (oC) 150 175 FIGURE 8. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 300 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD C, CAPACITANCE (pF) 250 RL VDS 200 COSS VGS 150 + VGS 100 0V CISS DUT RGS 50 CRSS 0 5 15 20 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 25 FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 80 TJ = 175oC ILIM = 1.35A RθJC = 4.17oC/W HSTR = 0oC/W 20 1oC/W 15 2oC/W 10 5oC/W FREE AIR RθJA = 80oC/W 10oC/W 5 0 25 25oC/W 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) 175 VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) 25 FIGURE 10. SWITCHING TEST CIRCUIT DUTY CYCLE = 20% 10% 5% 2% 60 40 50% 20 MAX PULSE WIDTH = 100ms TJ = 175oC, ILIM = 1.35A, RθJC = 4.17oC/W 0 25 50 75 100 125 150 175 TA, AMBIENT TEMPERATURE (oC) NOTE: Heatsink thermal resistance = 2oC/W FIGURE 11. DC OPERATION IN CURRENT LIMITING 6-431 FIGURE 12. MAXIMUM VDS vs TA IN CURRENT LIMITING RLP1N06CLE Typical Performance Curves 80 TJ = 175oC ILIM = 1.35A RθJC = 4.17oC/W VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) 80 Unless Otherwise Specified (Continued) 60 DUTY CYCLE = 20% 10% 5% 2% 40 20 50% MAX PULSE WIDTH = 100ms 0 25 50 75 100 125 150 TJ = 175oC ILIM = 1.35A RθJC = 4.17oC/W 60 40 DUTY CYCLE = 20% MAX PULSE WIDTH = 100ms 50 2% VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) 80 5% 1% 40 10% 20 DUTY CYCLE = 20% 50% 75 100 125 150 125 150 60 40 5% 20 10% 50% 50 75 100 125 150 NOTE: No external heatsink FIGURE 15. MAXIMUM VDS vs TA IN CURRENT LIMITING FIGURE 16. MAXIMUM VDS vs TA IN CURRENT LIMITING 10 RθJC = RθJC = 4.17oC/W 4.17oC/W 8 8 150oC 125oC 100oC 75oC STARTING 50oC TEMP = 25oC TIME TO 175oC (s) TIME TO 175oC (s) 175 TA, AMBIENT TEMPERATURE (oC) NOTE: Heatsink thermal resistance = 25oC/W 10 DUTY CYCLE = 1% 2% 0 25 175 MAX PULSE WIDTH = 100ms TJ = 175oC ILIM = 1.35A RθJA = 80oC/W TA, AMBIENT TEMPERATURE (oC) 6 4 150oC STARTING 125oC 100oC 75oC 50oC TEMP = 25oC 6 4 2 2 0 175 FIGURE 14. MAXIMUM VDS vs TA IN CURRENT LIMITING MAX PULSE WIDTH = 100ms TJ = 175oC ILIM = 1.35A RθJC = 4.17oC/W 50 100 NOTE: Heatsink thermal resistance = 10oC/W FIGURE 13. MAXIMUM VDS vs TA IN CURRENT LIMITING 0 25 75 TA, AMBIENT TEMPERATURE (oC) NOTE: Heatsink thermal resistance = 5oC/W 60 2% 50% TA, AMBIENT TEMPERATURE (oC) 80 5% 20 0 25 175 10% 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Heatsink thermal resistance = 2oC/W Heatsink thermal capacitance = 4j/oC FIGURE 17. TIME TO 175oC IN CURRENT LIMITING 6-432 25 0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Heatsink thermal resistance = 5oC/W Heatsink thermal capacitance = 2j/oC FIGURE 18. TIME TO 175oC IN CURRENT LIMITING 25 RLP1N06CLE Typical Performance Curves Unless Otherwise Specified (Continued) 10 10 RθJC = RθJC = 4.17oC/W 4.17oC/W 8 150oC 100oC TIME TO 175oC (s) TIME TO 175oC (s) 8 50oC 6 125oC 75oC STARTING TEMP = 25oC 4 2 0 6 4 125oC 150oC 75oC 100oC STARTING TEMP = 25oC 50oC 2 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 25 NOTE: Heatsink thermal resistance = 10oC/W Heatsink thermal capacitance = 1j/oC 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 NOTE: Heatsink thermal resistance = 25oC/W Heatsink thermal capacitance = 0.5j/oC FIGURE 19. TIME TO 175oC IN CURRENT LIMITING FIGURE 20. TIME TO 175oC IN CURRENT LIMITING 10 RθJA = 80oC/W TIME TO 175oC (s) 8 6 4 2 125oC 150oC 0 0 75oC 100oC STARTING TEMP = 25oC 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 NOTE: No external heatsink FIGURE 21. TIME TO 175oC IN CURRENT LIMITING Detailed Description Temperature Dependence of Current Limiting and Switching Speed The RLP1N06CLE is a monolithic power device which incorporates a logic level PowerMOS transistor with a resistor in series with the source. The base and emitter of a lateral bipolar transistor is connected across this resistor, and the collector of the bipolar transistor is connected to the gate of the PowerMOS transistor. When the voltage across the resistor reaches the value required to forward bias the emitter base junction of the bipolar transistor, the bipolar transistor “turns on”. A series resistor is incorporated in series with the gate of the PowerMOS transistor allowing the bipolar transistor to drive the gate of the PowerMOS transistors to a voltage which just maintains a constant current in the PowerMOS transistor. Since both the resistance of the resistor 6-433 in series with the PowerMOS transistor source and voltage required to forward bias the base emitter junction of the bipolar transistor vary with the temperature, the current at which the device limits is a function of temperature. This dependence is shown in figure 2. The resistor in series with the gate of the PowerMOS transistor results in much slower switching than in most PowerMOS transistors. This is an advantage where fast switching can cause EMI or RFI. The switching speed is very predictable, and a minimum as well as maximum fall time is given in the device characteristics for this type. DC Operation of the RLP1N06CLE The limit of the drain to source voltage for operation in current limiting on a steady state (DC) basis is shown as Figure 11. The dissipation in the device is simply the applied drain to source voltage multiplied by the limiting current. This RLP1N06CLE device, like most Power MOSFET devices today, is limited to 175oC. The maximum voltage allowable can, therefore be expressed as: o ( 175 C – T AMBIENT ) V DS = ---------------------------------------------------------I LIM × ( R θJC + R θCA ) (EQ. 1) Duty Cycle Operation of the RLP1N06CLE In many applications either the drain to source voltage or the gate drive is not available 100% of the time. The copper header on which the RLP1N06CLE is mounted has a very large thermal storage capability, so for pulse widths of less than 100 milliseconds, the temperature of the header can be considered a constant case temperature calculated simply as: T C = ( V DS × I D × D × R θCA ) + T AMBIENT (EQ. 2) Generally the heat storage capability of the silicon chip in a power transistor is ignored for duty cycle calculations. Making this assumption, limiting junction temperature to 175oC and using the TC calculated above, the expression for maximum VDS under duty cycle operation is: 175 – T C V DS = -----------------------------------------I LIM × D × R θJC Limited Time Operations of the RLP1N06CLE Protection for a limited period of time is sufficient for many applications. As stated above the heat storage in the silicon chip can usually be ignored for computations of over 10 milliseconds and the thermal equivalent circuit reduces to a simple enough circuit to allow easy computation on the limiting conditions. The variation in limiting current with temperature complicates the calculation of junction temperature, but a simple straight line approximation of the variation is accurate enough to allow meaningful computations. The curves shown as figures 17 thru 21 give an accurate indication of how long the specified voltage can be applied to the device in the current limiting mode without exceeding the maximum specified 175oC junction temperature. In practice this tells you how long you have to alleviate the condition causing the current limiting to occur. (EQ. 3) These values are plotted as Figures 12 thru 16. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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