S E M I C O N D U C T O R RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE 0.3A, 60V, ESD Rated, Current Limited, Voltage Clamped Logic Level N-Channel Enhancement-Mode Power MOSFETs July 1996 Features • • • • • • • Packages JEDEC TO-220AB 0.30A, 60V rDS(ON) = 6.0Ω Built in Current Limit ILIMIT 0.140 to 0.210A at 150oC Built in Voltage Clamp Temperature Compensating PSPICE Model 2kV ESD Protected Controlled Switching Limits EMI and RFI SOURCE DRAIN GATE DRAIN (FLANGE) JEDEC TO-251AA Description SOURCE DRAIN GATE The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE are intelligent monolithic power circuits which incorporate a lateral bipolar transistor, resistors, zener diodes and a power MOS transistor. The current limiting of these devices allow it to be used safely in circuits where a shorted load condition may be encountered. The drain-source voltage clamping offers precision control of the circuit voltage when switching inductive loads. The “Logic Level” gate allows this device to be fully biased on with only 5.0V from gate to source, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. DRAIN (FLANGE) JEDEC TO-252AA DRAIN (FLANGE) GATE SOURCE The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE incorporate ESD protection and are designed to withstand 2kV (Human Body Model) of ESD. Symbol D PACKAGING AVAILABILITY PART NUMBER PACKAGE BRAND RLD03N06CLE TO-251AA 03N06C RLD03N06CLESM TO-252AA 03N06C RLP03N06CLE TO-220AB 03N06CLE G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RLD03N06CLESM9A. S Formerly developmental type TA49026. Absolute Maximum Ratings TC = +25oC Drain Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate Source Voltage (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Reverse Voltage Gate Bias Not Allowed Drain Current RMS Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Power Dissipation TC = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PT Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . . ESD Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSTG, TJ RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE 60 60 +5.5 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright © Harris Corporation 1996 1 UNITS V V V Self Limited 30 0.2 2 -55 to +175 W W/oC KV oC File Number 3948.3 Specifications RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Electrical Specifications TC = +25oC, Unless Otherwise Specified PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain-Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V 60 - 85 V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 1 - 2.5 V TJ = +25oC - - 50 µA TJ = +150oC - - 200 µA TJ = +25oC - - 5 µA TJ = +150oC - - 20 µA TJ = +25oC - - 6.0 Ω TJ = +150oC - - 12.0 Ω TJ = +25oC 280 - 420 mA TJ = +150oC 140 - 210 mA - - 7.5 µs - - 2.5 µs tR - - 5.0 µs tD(OFF) - - 7.5 µs tF - - 5.0 µs Turn-Off Time tOFF - - 12.5 µs Input Capacitance CISS - 100 - pF Output Capacitance COSS - 65 - pF Reverse Transfer Capacitance CRSS - 3.0 - pF Thermal Resistance Junction to Case RθJC - - 5.0 oC/W Thermal Resistance Junction to Ambient RθJA TO-220 Package - - 80 oC/W TO-251 and TO-252 Packages - - 100 oC/W MIN TYP MAX UNITS Zero Gate Voltage Drain Current Gate-Source Leakage Current On Resistance Limiting Current Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time IDSS IGSS rDS(ON) IDS(LIMIT) tON tD(ON) VDS = 45V, VGS = 0V VGS = 5V ID = 0.100A, VGS = 5V VDS = 15V, VGS = 5V VDD = 30V, ID = 0.10A, RL = 300Ω, VGS = 5V, RGS = 25Ω VDS = 25V, VGS = 0V, f = 1MHz Source-Drain Diode Ratings and Specifications PARAMETERS SYMBOL TEST CONDITIONS Forward Voltage VSD ISD = 0.1A - - 1.5 V Reverse Recovery Time tRR ISD = 0.1A, dISD/dt = 100A/µs - - 1.0 ms 2 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Typical Performance Curves TC = +25oC 1 10 ZθJC , NORMALIZED THERMAL RESPONSE ID , DRAIN CURRENT (A) OPERATION IN THIS AREA IS LIMITED BY JUNCTION TEMPERATURE 25oC DC 175oC OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 1 10 VDS , DRAIN-TO-SOURCE VOLTAGE (V) 0.5 PDM 0.2 0.1 0.05 0.02 0.01 SINGLE PULSE 0.1 0.01 10-5 100 10-4 POWER DISSIPATION MULTIPLIER 1.0 0.5 0 -80 -40 0 40 80 120 160 100 101 0.8 0.6 0.4 0.2 0.0 200 0 25 50 ID(ON) , ON STATE DRAIN CURRENT (A) VGS = 4V 0.30 VGS = 3V 0.20 0.10 2.0 3.0 125 150 175 4.0 VDD = 15V 0.60 VGS = 7.5V 1.0 100 FIGURE 4. NORMALIZED POWER DISSIPATION vs TEMPERATURE DERATING CURVE PULSE DURATION = 250µs, TC = +25oC VGS = 5V 75 TC , CASE TEMPERATURE (oC) FIGURE 3. TYPICAL NORMALIZED DRAIN CURRENT vs JUNCTION TEMPERATURE ID , DRAIN CURRENT (A) 10-1 1.0 TJ , JUNCTION TEMPERATURE (oC) 0 10-2 1.2 1.5 0 10-3 FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 2.0 0.40 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC t, RECTANGULAR PULSE DURATION (s) FIGURE 1. SAFE OPERATING AREA CURVE ID , NORMALIZED DRAIN CURRENT 1 -55oC 0.50 0.40 VDS , DRAIN-TO-SOURCE VOLTAGE (V) +25oC 0.30 0.20 +175oC 0.10 0 0.0 5.0 PULSE TEST PULSE DURATION = 250µs DUTY CYCLE = 0.5% MAX 1.0 2.0 3.0 4.0 VGS , GATE-TO-SOURCE VOLTAGE (V) FIGURE 5. TYPICAL SATURATION CHARACTERISTICS FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS 3 5.0 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE PULSE DURATION = 250µs, 2.5 VGS = 5V, ID = 0.30A VGS = VDS, 2.0 VGS(TH) , NORMALIZED GATE THRESHOLD VOLTAGE 2.0 1.5 1.0 1.5 1.0 0.5 0.5 0.0 -80 -40 0 40 80 120 160 0.0 -80 200 TJ , JUNCTION TEMPERATURE (oC) I(CLAMP) , CLAMPED DRAIN CURRENT (A) BVDSS , NORMALIZED DRAIN-TOSOURCE BREAKDOWN VOLTAGE 1.5 1.0 0.5 0.0 -80 -40 0 40 80 0 120 160 200 FIGURE 9. NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE vs TEMPERATURE FREQUENCY (f) = 1MHz CISS 100 COSS CRSS 0 5 10 15 160 200 TC = +25oC TEMPERATURES LISTED ARE STARTING JUNCTION TEMPERATURES +25oC +50oC +75oC +100oC +150oC 0.1 0.001 0.01 +125oC 0.1 tAV , TIME IN CLAMP (s) 1 45 3.75 VDD = BVDSS 2.50 30 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 15 RL = 600Ω IG(REF) = 0.1mA VGS = 5V 0 20 10 5.00 60 200 0 120 FIGURE 10. SELF-CLAMPED INDUCTIVE SWITCHING VDS , DRAIN SOURCE VOLTAGE (V) VGS = 0V, 80 1 TJ , JUNCTION TEMPERATURE (oC) 300 40 FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs TEMPERATURE ID = 20mA 2.0 -40 TJ , JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE C, CAPACITANCE (pF) ID = 250µA 0.00 I G ( REF ) 10 ---------------------I G ( AC T ) 25 VDS , DRAIN-TO-SOURCE VOLTAGE (V) FIGURE 11. TYPICAL CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 1.25 VGS , GATE SOURCE VOLTAGE (V) rDS(ON) , NORMALIZED ON RESISTANCE Typical Performance Curves (Continued) t, TIME (µs) I G ( REF ) 40 I---------------------G ( AC T ) FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT. REFER TO HARRIS APPLICATION NOTES AN7254 AND AN7260 4 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Test Circuit and Waveform VDD tON tD(ON) tOFF tD(OFF) tR RL VDS VDS tF 90% 90% VGS 10% 10% DUT 90% 0V 50% VGS RGS 50% PULSE WIDTH 10% FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 14. RESISTIVE SWITCHING WAVEFORMS Detailed Description Duty Cycle Operation Temperature Dependence of Current Limiting and Switching Speed Performance In many applications either the drain to source voltage or the gate drive is not available 100% of the time. The copper header on which the RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE is mounted has a very large thermal storage capability, so for pulse widths of less then 1ms, the temperature of the header can be considered a constant, thereby the junction temperature can be calculated simply as shown in Equation 2: The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE are a monolithic power device which incorporates a Logic Level power MOSFET transistor with a current sensing scheme and control circuitry to enable the device to self limit the drain source current flow. The current sensing scheme supplies current to a resistor that is connected across the base to emitter of a bipolar transistor in the control section. The collector of this bipolar transistor is connected to the gate of the power MOSFET transistor. When the ratiometric current from the current sensing reaches the value required to forward bias the base emitter junction of this bipolar transistor, the bipolar “turns on”. A resistor is incorporated in series with the gate of the power MOSFET transistor allowing the bipolar transistor to adjust the drive on the gate of the power MOSFET transistor to a voltage which then maintains a constant current in the power MOSFET transistor. Since both the ratiometric current sensing scheme and the base emitter unction voltage of the bipolar transistor vary with temperature, the current at which the device limits is a function of temperature. This dependence is shown in Figure 3. T C = ( V DS • I D • D • R θCA ) + TA MBIENT Generally the heat storage capability of the silicon chip in a power transistor is ignored for duty cycle calculations. Making this assumption, limiting junction temperature to 175oC and using the TC calculated in Equation 2, the expression for maximum VDS under duty cycle operation is shown in Equation 3: o 150 C – T C V DS = -----------------------------------------I LM • D • R θJC Limited Time Operations Protection for a limited period of time is sufficient for many applications. As stated above the heat storage in the silicon chip can usually be ignored for computations of over 10 ms, thereby the thermal equivalent circuit reduces to a simple enough circuit to allow easy computation on the limiting conditions. The variation in limiting current with temperature complicates the calculation of junction temperature, but a simple straight line approximation of the variation is accurate enough to allow meaningful computations. The curves shown as Figures 22 through 25 (RLP03N06CLE) and Figure 26 through 29 (RLD03N06CLE and RLD03N06CLESM) give an accurate indication of how long the specified voltage can be applied to the device in the current limiting mode without exceeding the maximum specified 175oC junction temperature. In practice this tells you how long you have to alleviate the condition causing the current limiting to occur. DC Operation The limit on the drain to source voltage for operation in current limiting on a steady state (DC) basis is shown in the equation below. The dissipation in the device is simply the applied drain to source voltage multiplied by the limiting current. This device, like most power MOSFET devices today, is limited to 175oC. The maximum voltage allowable can, therefore, be expressed as shown in Equation 1: θJC θJA (EQ. 3) These values are plotted as Figures 16 through 21 for various heatsink thermal resistances. The resistor in series with the gate of the power MOSFET transistor also results in much slower switching performance than in standard power MOSFET transistors. This is an advantage where fast switching can cause EMI or RFI. The switching speed is very predictable. ( 150°C – TA MBIENT ) V DS = ------------------------------------------------------I LM • ( R +R ) (EQ. 2) (EQ. 1) The results of this equation are plotted in Figure 15 for various heatsinks. 5 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Performance Curves HEAT SINK THERMAL RESISTANCE = HSTR DUTY CYCLE = DC HSTR = 0oC/W HSTR = 1oC/W HSTR = 2oC/W 75 HSTR = 5oC/W TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W 60 HSTR = 10oC/W 45 30 HSTR = 25oC/W 15 0 HSTR = 80oC/W 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) VDS , DRAIN TO SOURCE VOLTAGE (V) MAX PULSE WIDTH = 100ms DC = 2% DC = 50% 60 DC = 5% DC = 10% 45 30 15 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W 0 100 125 150 TA , AMBIENT TEMPERATURE (oC) 60 DC = 10% 45 30 15 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W 125 150 TA , AMBIENT TEMPERATURE (oC) DUTY CYCLE = DC 175 MAX PULSE WIDTH = 100ms DC = 20% DC = 2% 75 DC = 5% 60 DC = 10% DC = 50% 45 30 15 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W 0 75 175 FIGURE 17. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 2oC/W) DUTY CYCLE = DC DC = 5% 90 75 DC = 20% DC = 2% FIGURE 16. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HEATSINK THERMAL RESISTANCE = 1oC/W) VDS , DRAIN TO SOURCE VOLTAGE (V) DUTY CYCLE = DC 90 DC = 20% DC = 50% 75 0 100 175 FIGURE 15. DC OPERATION IN CURRENT LIMITING 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175 FIGURE 18. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 5oC/W) MAX PULSE WIDTH = 100ms DUTY CYCLE = DC 90 MAX PULSE WIDTH = 100ms 90 DC = 20% VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) MAX PULSE WIDTH = 100ms 90 VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , APPLIED VOLTAGE (V) 90 DC = 2% 75 DC = 50% 60 DC = 5% DC = 10% 45 30 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W 15 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) DC = 20% FIGURE 19. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 10oC/W) DC = 2% DC = 5% 60 45 DC = 50% 30 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W 15 0 175 DC = 10% 75 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 175 FIGURE 20. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 25oC/W) 6 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Performance Curves DUTY CYCLE = DC 90 DC = 10% 75 MAX PULSE WIDTH = 100ms DC = 2% DC = 5% 10 DC = 1% 60 DC = 20% 45 30 DC = 50% 25 50 6 4 2 15 0 STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC 8 TJ = 175oC ILIM = 0.210A RθJC = 5.0oC/W TIME TO 175oC (s) VDS , DRAIN TO SOURCE VOLTAGE (V) (Continued) 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 0 175 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90 FIGURE 22. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 25oC/W) (HEATSINK THERMAL CAPACITANCE = 0.5J/oC) FIGURE 21. MAXIMUM VDS vs AMBIENT TEMPERATURE IN CURRENT LIMITING. (HSTR = 80oC/W) 10 10 75oC STARTING TJ = STARTING TJ = 100oC STARTING TJ = 125oC STARTING TJ = 150oC 8 TIME TO 175oC (s) TIME TO 175oC (s) 8 6 4 2 STARTING TJ = 75oC 6 STARTING TJ = 100oC 4 STARTING TJ = 125oC 2 STARTING TJ = 150oC 0 0 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90 FIGURE 23. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 10oC/W) (HEATSINK THERMAL CAPACITANCE = 1.0J/oC) 10 90 10 STARTING TJ = 75oC 8 TIME TO 175oC (s) TIME TO 175oC (s) 50 70 30 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 24. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 5oC/W) (HEATSINK THERMAL CAPACITANCE = 2.0J/oC) 8 STARTING TJ = 100oC 6 4 STARTING TJ = 125oC 2 STARTING TJ = 75oC STARTING TJ = 100oC STARTING TJ = 125oC 6 STARTING TJ = 150oC 4 2 STARTING TJ = 0 10 10 150oC 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 90 FIGURE 25. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 2oC/W) (HEATSINK THERMAL CAPACITANCE = 4J/oC) 10 30 50 70 VDS , DRAIN TO SOURCE VOLTAGE (V) 90 FIGURE 26. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 25oC/W) (HEATSINK THERMAL CAPACITANCE = 0.5J/oC) 7 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Performance Curves (Continued) 10 10 8 8 STARTING TJ = 75oC STARTING TJ = 100 C TIME TO 175oC (s) TIME TO 175oC (s) o STARTING TJ = 125oC 6 STARTING TJ = 150oC 4 STARTING TJ = 75oC 6 STARTING TJ = 100oC 4 STARTING TJ = 125oC 2 2 STARTING TJ = 150oC 0 0 10 30 50 70 10 90 50 30 VDS , DRAIN TO SOURCE VOLTAGE (V) 70 FIGURE 27. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 10oC/W) (HEATSINK THERMAL CAPACITANCE = 1.0J/oC) FIGURE 28. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 5oC/W) (HEATSINK THERMAL CAPACITANCE = 2.0J/oC) 10 STARTING TJ = 75oC TIME TO 175oC (s) 8 6 STARTING TJ = 100oC 4 STARTING TJ = 125oC 2 STARTING TJ = 150oC 0 10 90 VDS , DRAIN TO SOURCE VOLTAGE (V) 50 30 70 90 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 29. TIME TO 175oC IN CURRENT LIMITING (HEATSINK THERMAL RESISTANCE = 2oC/W) (HEATSINK THERMAL CAPACITANCE = 4J/oC) 8 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE Temperature Compensated PSPICE Model for the RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE SUBCKT RLD03N06CLE 2 1 3; CA 12 8 0.547e-9 CB 15 14 0.547e-9 CIN 6 8 0.301e-9 rev 4/18/94 DBREAK DPLCAP 10 11 + EBREAK ESG 6 8 + 17 18 GATE 1 RGATE LGATE DESD1 LDRAIN 2 5 1e-9 LGATE 1 9 2.96e-9 LSOURCE 3 7 2.96e-9 DESD2 9 VTO + EVTO + 18 8 21 MOS2 CIN RIN 91 DBODY MOS1 6 8 12 LSOURCE RSOURCE1 RSOURCE2 3 SOURCE 7 70 S1A MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1.123 RGATE 9 20 3200 RIN 6 8 1e9 RSOURCE1 8 70 RDSMOD 1.12 RSOURCE2 70 7 RSMOD 2.16 RVTO 18 19 RVTOMOD 1 RDRAIN 16 - IT 8 17 1 QCONTROL 20 70 7 QMOD 1 DRAIN LDRAIN 2 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 20 17 18 66.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 5 S2A 14 13 13 8 S1B RVTO CB + + 6 8 EGS 18 17 S2B 13 CA RBREAK 15 EDS 14 IT 5 8 19 VBAT + S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.22 .MODEL DBDMOD D (IS = 7.97e-17 RS = 1.82 TRS1 = 3.91e-3 TRS2 = 1.24e-5 CJO = 3.00e-10 TT = 1.83e-7) .MODEL DBKMOD D (RS = 3150 TRS1 =0 TRS2 = 0) .MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0) .MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 74.2e-12 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.67 KP = 3.40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL QMOD NPN (BF =5) .MODEL RBKMOD RES (TC1 = 4e-4 TC2 = 1.13e-8) .MODEL RDSMOD RES (TC1 = 6.80e-3 TC2 = 6.5e-6) .MODEL RSMOD RES (TC1 = 2.95e-3 TC2 = -1e-6) .MODEL RVTOMOD RES (TC1 = -2.22e-3 TC2 = -1.95e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF = -1) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF = -3) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.85 VOFF = 2.15) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.15 VOFF = -2.85) .ENDS NOTE: 1. For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records 1991. 9 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE TO-220AB 3 LEAD JEDEC TO-220AB PLASTIC PACKAGE A INCHES E ØP A1 Q H1 TERM. 4 D 45o E1 D1 L1 b1 L b c MIN MAX MIN MAX NOTES A 0.170 0.180 4.32 4.57 - A1 0.048 0.052 1.22 1.32 - b 0.030 0.034 0.77 0.86 3, 4 b1 0.045 0.055 1.15 1.39 2, 3 c 0.014 0.019 0.36 0.48 2, 3, 4 D 0.590 0.610 14.99 15.49 - D1 - 0.160 E 0.395 0.410 E1 - 0.030 e 60o 1 2 e1 3 e J1 e1 LEAD NO. 1 - GATE LEAD NO. 2 - DRAIN LEAD NO. 3 - SOURCE TERM. 4 - DRAIN MILLIMETERS SYMBOL 0.100 TYP 0.200 BSC H1 0.235 0.255 J1 0.100 0.110 L 0.530 0.550 10.04 - 4.06 - 10.41 - 0.76 - 2.54 TYP 5 5.08 BSC 5 5.97 6.47 - 2.54 2.79 6 13.47 13.97 - L1 0.130 0.150 3.31 3.81 2 ØP 0.149 0.153 3.79 3.88 - Q 0.102 0.112 2.60 2.84 - NOTES: 1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-220AB outline dated 3-24-87. 2. Lead dimension and finish uncontrolled in L1. 3. Lead dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 1 dated 1-93. 10 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE TO-251AA 3 LEAD JEDEC TO-251AA PLASTIC PACKAGE E b2 H1 INCHES A MIN MAX MIN MAX TERM. 4 A 0.086 0.094 2.19 2.38 - SEATING PLANE A1 0.018 0.022 0.46 0.55 3, 4 A1 D b1 L1 L c b 1 2 3 J1 e e1 LEAD NO. 1 - GATE LEAD NO. 2 - DRAIN LEAD NO. 3 - SOURCE TERM. 4 - DRAIN MILLIMETERS SYMBOL NOTES b 0.028 0.032 0.72 0.81 3, 4 b1 0.033 0.040 0.84 1.01 3 b2 0.205 0.215 5.21 5.46 3, 4 c 0.018 0.022 0.46 0.55 3, 4 D 0.270 0.290 6.86 7.36 - E 0.250 0.265 6.35 6.73 - e 0.090 TYP 2.28 TYP 5 e1 0.180 BSC 4.57 BSC 5 H1 0.035 0.045 0.89 1.14 - J1 0.040 0.045 1.02 1.14 6 L 0.355 0.375 9.02 9.52 - L1 0.075 0.090 1.91 2.28 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-251AA outline dated 9-88. 2. Solder finish uncontrolled in this area. 3. Dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder plating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 2 dated 10-95. 11 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE TO-252AA SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE INCHES A E A1 b2 H1 SEATING PLANE D L2 1 L 3 b1 b e e1 b3 L3 0.094 2.19 2.38 - 0.018 0.022 0.46 0.55 4, 5 b 0.028 0.032 0.72 0.81 4, 5 b1 0.033 0.040 0.84 1.01 4 b2 0.205 0.215 5.21 5.46 4, 5 b3 0.190 - 4.83 - 2 0.46 0.55 4, 5 6.86 7.36 - c E 0.250 0.265 6.35 6.73 J1 e e1 0.090 TYP 0.180 BSC - 2.28 TYP 7 4.57 BSC 7 H1 0.035 0.045 0.89 1.14 - J1 0.040 0.045 1.02 1.14 - L 0.100 0.115 2.54 2.92 - L1 0.020 - 0.51 - 4, 6 L2 0.025 0.040 0.64 1.01 3 L3 0.170 - 4.32 - 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. B of JEDEC TO-252AA outline dated 9-88. 2. L3 and b3 dimensions establish a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled in this area. 4. Dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder plating. 6. L1 is the terminal length for soldering. 7. Position of lead to be measured 0.090 inches (2.28mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 5 dated 10-95. 0.090 (2.3) MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS - DRAIN 0.086 0.022 0.063 (1.6) TERM. 4 A A1 0.290 0.090 (2.3) - SOURCE NOTES 0.018 0.118 (3.0) - GATE MAX 0.270 BACK VIEW LEAD NO. 3 MIN c 0.070 (1.8) LEAD NO. 1 MAX D 0.265 (6.7) 0.063 (1.6) MIN L1 0.265 (6.7) TERM. 4 MILLIMETERS SYMBOL 12 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE TO-252AA 16mm TAPE AND REEL 22.4mm 4.0mm 1.5mm DIA. HOLE 2.0mm 13mm 1.75mm C L 16mm 330mm 50mm 8.0mm 16.4mm USER DIRECTION OF FEED COVER TAPE GENERAL INFORMATION 1. USE "9A" SUFFIX ON PART NUMBER. 2. 2500 PIECES PER REEL. 3. ORDER IN MULTIPLES OF FULL REELS ONLY. 4. MEETS EIA-481 REVISION "A" SPECIFICATIONS. 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