RFT3055LE
Data Sheet
August 1999
2.0A, 60V, 0.150 Ohm, N-Channel, Logic
Level, ESD Rated, Power MOSFET
• 2.0A, 60V
• rDS(ON) = 0.150Ω
• 2kV ESD Protected
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Formerly developmental type TA49158.
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
RFT3055LE
PACKAGE
SOT-223
4537.3
Features
This product is an N-Channel power MOSFET manufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. It was designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
PART NUMBER
File Number
BRAND
Symbol
3055L
D
NOTE: RFT3055LE is available only in tape and reel.
G
S
Packaging
SOT-223
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
8-143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFT3055LE
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
RFT3055LE
60
60
±10
UNITS
V
V
V
2.0
Figure 5
Figures 6, 16, 17
1.1
9.09
-55 to 150
A
W
mW/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
PARAMETER
SYMBOL
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
60
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
1
-
2
V
VDS = 60V, VGS = 0V
-
-
1
µA
Zero Gate Voltage Drain Current
IDSS
VDS = 60V, VGS = 0V, TA = 150oC
-
-
50
µA
VGS = ±10V
-
-
10
µA
ID = 2.0A, VGS = 5V (Figure 9)
-
0.110
0.150
Ω
VDD = 30V, ID ≅ 2.0A,
RL = 15Ω, VGS = 5V,
RGS = 5Ω
(Figure 12)
-
-
120
ns
-
10
-
ns
-
70
-
ns
td(OFF)
-
30
-
ns
tf
-
25
-
ns
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
TEST CONDITIONS
Fall Time
Turn-Off Time
tOFF
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Gate Charge at 10V
Threshold Gate Charge
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Ambient
RθJA
VDD = 30V,
ID ≅ 2.0A,
RL = 15Ω
Ig(REF) = 1.0mA
(Figure 15)
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
-
-
85
ns
-
28
35
nC
-
15
18
nC
-
1.0
1.2
nC
-
850
-
pF
-
170
-
pF
-
100
-
pF
Pad Area = 0.171 in2 (see note 2)
-
-
110
oC/W
Pad Area = 0.068 in2
-
-
128
oC/W
Pad Area = 0.026 in2
-
-
147
oC/W
MIN
TYP
MAX
UNITS
ISD = 2.0A
-
-
1.5
V
ISD = 2.0A, dISD/dt = 100A/µs
-
-
100
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
VSD
trr
TEST CONDITIONS
NOTE:
2. 110 oC/W measured using FR-4 board with 0.171in2 footprint for 1000 seconds.
8-144
RFT3055LE
Typical Performance Curves
Unless otherwise specified
2.5
RθJA = 110oC/W
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
2.0
1.5
1.0
0.5
0
0
0
25
50
75
100
25
150
125
50
TA , AMBIENT TEMPERATURE (oC)
75
100
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
ZθJA, NORMALIZED
THERMAL IMPEDANCE
150
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
2
1
125
TA, AMBIENT TEMPERATURE (oC)
RθJA = 110oC/W
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.01
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
102
103
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
10
100µs
1ms
1
10ms
100ms
0.1
0.01
0.1
30
TJ = MAX RATED
TA = 25oC
RθJA = 110oC/W
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
DC
100 200
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
8-145
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
100
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
150 - TA
125
I = I25
10
RθJA = 110oC/W
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10-3
10-2
10-1
100
101
102
t, PULSE WIDTH (s)
FIGURE 5. PEAK CURRENT CAPABILITY
103
RFT3055LE
Typical Performance Curves
20
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10
STARTING TJ = 25oC
STARTING TJ = 150oC
1
0.1
0.01
VGS = 5V
VGS = 4.5V
VGS = 10V
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
20
Unless otherwise specified (Continued)
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
16
VGS = 4V
12
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
8
VGS = 3V
4
0
100
0
1
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
16
150oC
-55oC
25oC
12
8
4
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
ID, DRAIN CURRENT (A)
20
1.5
3.0
4.5
1.5
1.25
1.0
0.75
0.5
-80
0
0
1.75
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V, ID = 2A
6.0
FIGURE 8. TRANSFER CHARACTERISTICS
40
80
120
160
1.1
1.0
0.9
0.8
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
8-146
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.15
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
0
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
0.7
-80
-40
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 250µA
1.1
1.05
1.0
0.95
0.9
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFT3055LE
Typical Performance Curves
Unless otherwise specified (Continued)
200
250
rDS(ON), ON-STATE RESISTANCE (mΩ)
VDD = 30V, ID = 2A, RL = 15Ω
SWITCHING TIME (ns)
tR
150
100
tF
tD(OFF)
50
tD(ON)
0
0
30
20
40
10
RGS, GATE TO SOURCE RESISTANCE (Ω)
ID = 0.5A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
200
150
100
50
2
50
FIGURE 12. SWITCHING TIME vs GATE RESISTANCE
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 13. SOURCE TO DRAIN ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
10
VGS , GATE TO SOURCE VOLTAGE (V)
1200
CISS
C, CAPACITANCE (pF)
ID = 2A
900
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
600
COSS
300
CRSS
WAVEFORMS IN
DESCENDING ORDER:
ID = 2A
ID = 0.5A
8
6
4
2
0
0
0
0
5
VDD = 15V
10
15
20
25
30
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
8-147
6
12
18
Qg, GATE CHARGE (nC)
24
30
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
RFT3055LE
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
DUT
VGS = 5V
VGS
-
VGS = 1V
Ig(REF)
0
Qg(TH)
Ig(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORM
tON
tOFF
td(ON)
td(OFF)
VDS
VDS
VGS
tf
tr
RL
90%
90%
+
VGS
-
10%
10%
0
0V
RGS
90%
DUT
VGS
0
FIGURE 20. SWITCHING TIME TEST CIRCUIT
8-148
10%
50%
50%
PULSE WIDTH
FIGURE 21. RESISTIVE SWITCHING WAVEFORMS
RFT3055LE
Thermal Resistance vs. Mounting Pad
Area
( T J ( MAX ) – T A )
P D ( MAX ) = -------------------------------------------R θJA
RθJA = 75.9 - 19.3 * ln(AREA)
147oC/W - 0.026in2
RθJA (oC/W)
The maximum rated junction temperature, TJ(MAX), and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PD(MAX),
in an application. Therefore the application’s ambient
temperature, TA (oC), and thermal impedance RθJA (oC/W)
must be reviewed to ensure that TJ(MAX) is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
200
150
128oC/W - 0.068in2
110oC/W - 0.171in2
100
(EQ. 1)
50
0.01
In using surface mount devices such as the SOT-223
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of the
PD(MAX) is complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer’s
preliminary application evaluation. Figure 22 defines the
RθJA for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow.This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
8-149
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 22. THERMAL RESISTANCE vs MOUNTING PAD
AREA
Displayed on the curve are the three RθJA values listed in
the Electrical Specifications table. The three points were
chosen to depict the compromise between the copper board
area, the thermal resistance and ultimately the power
dissipation, PD(MAX). Thermal resistances corresponding to
other component side copper areas can be obtained from
Figure 22 or by calculation using Equation 2. The area, in
square inches is the top copper area including the gate and
source pads.
R θJA = 75.9 – 19.3 × ln ( Area )
(EQ. 2)
RFT3055LE
PSPICE Electrical Model
.SUBCKT RFT3055LE 2 1 3 ;
REV May 98
CA 12 8 1.68e-9
CB 15 14 1.78e-9
CIN 6 8 7.69e-10
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
DRAIN
2
5
10
RLDRAIN
RSLC1
51
+
5
ESLC
51
RSLC2
EBREAK 11 7 17 18 64.28
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
11
50
ESG
IT 8 17 1
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 4.6e-9
LSOURCE 3 7 4.6e-9
LGATE
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
EBREAK 17
18
RDRAIN
16
6
8
+
EVTHRES
+ 19
8
EVTEMP
RGATE +
18
9
20 22
21
6
DBODY
MWEAK
MMED
MSTRO
DESD1
91
DESD2
LSOURCE
CIN
RSOURCE
8
SOURCE
3
7
RLSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 24e-3
RGATE 9 20 9.84
RLDRAIN 2 5 10
RLGATE 1 9 46
RLSOURCE 3 7 46
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 49e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
S1A
12
13
8
S2A
15
14
13
S1B
RBREAK
18
17
S2B
13
CA
RVTEMP
CB
+
EGS
EDS
IT
14
+
6
8
19
VBAT
5
8
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),4))}
.MODEL DBODYMOD D (IS = 3.61e-13 RS = 1.78e-2 TRS1 = 1.7e-2 TRS2 = -4.69e-6 CJO = 3.88e-10 TT = 3.6e-8)
.MODEL DBREAKMOD D (RS = 4.73e-1 TRS1 = -2.19e-3 TRS2 = 4.7e-5)
.MODEL DESD1MOD D (BV = 12.5 NBV = 17.5 IBV = 2.5e-4 RS = 22)
.MODEL DESD2MOD D (BV = 12.86 NBV = 22 IBV = 2.5e-4 RS = 0)
.MODEL DPLCAPMOD D (CJO = 4.803e-10 IS = 1e-30 N = 10)
.MODEL MMEDMOD NMOS (VTO = 1.78 KP = 1.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 9.84)
.MODEL MSTROMOD NMOS (VTO = 2.08 KP = 10.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.55 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 98.4 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = -6.22e-7)
.MODEL RDRAINMOD RES (TC1 = 4.5e-3 TC2 = 6e-5)
.MODEL RSLCMOD RES (TC1 = 0 TC2 = 0)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = 0 TC2 = -4e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.9e-3 TC2 = 1.3e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.4 VOFF= -2.4)
VON = -2.4 VOFF= -4.4)
VON = -2.0 VOFF= 1.15)
VON = 1.15 VOFF= -2.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8-150
RFT3055LE
SPICE Thermal Model
9
REV May 98
RFT3055LE
Copper Area = 0.077in2
CTHERM1 9 8 7.5e-5
CTHERM2 8 7 3.5e-4
CTHERM3 7 6 1.2e-3
CTHERM4 6 5 1.5e-2
CTHERM5 5 4 6.0e-2
CTHERM6 4 3 3.0e-1
CTHERM7 3 2 1.6
CTHERM8 2 1 6
RTHERM1
JUNCTION
CTHERM1
8
RTHERM2
RTHERM1 9 8 8.2e-2
RTHERM2 8 7 2.7e-1
RTHERM3 7 6 1.9
RTHERM4 6 5 3.1
RTHERM5 5 4 12
RTHERM6 4 3 38
RTHERM7 3 2 32
RTHERM8 2 1 22
CTHERM2
7
RTHERM3
CTHERM3
6
RTHERM4
CTHERM4
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
1
8-151
AMBIENT
RFT3055LE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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8-152
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