SFR/U9210 Advanced Power MOSFET FEATURES BVDSS = -200 V Avalanche Rugged Technology RDS(on) = 3.0 Ω Rugged Gate Oxide Technology Lower Input Capacitance ID = -1.6 A Improved Gate Charge Extended Safe Operating Area D-PAK Lower Leakage Current : 10 µA (Max.) @ VDS = -200V Lower RDS(ON) : 2.084 Ω (Typ.) I-PAK 2 1 1 3 2 3 1. Gate 2. Drain 3. Source Absolute Maximum Ratings Symbol VDSS Characteristic Drain-to-Source Voltage Value o ID Continuous Drain Current (TC=25 C) Continuous Drain Current (TC=100 C) Drain Current-Pulsed VGS Gate-to-Source Voltage EAS Single Pulsed Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy dv/dt Peak Diode Recovery dv/dt 1 O -6.4 + _ 30 A O 1 O 1 O O3 119 mJ -1.6 A 2 o Total Power Dissipation (TC=25 C) Linear Derating Factor TL A -1.08 o Total Power Dissipation (TA=25 C) * TJ , TSTG V -1.6 o IDM PD Units -200 Operating Junction and V 1.9 mJ -5.0 V/ns 2.5 W 19 W 0.15 W/ C o - 55 to +150 Storage Temperature Range o Maximum Lead Temp. for Soldering C 300 Purposes, 1/8” from case for 5-seconds Thermal Resistance Symbol Characteristic Typ. Max. RθJC Junction-to-Case -- 6.58 RθJA Junction-to-Ambient * -- 50 RθJA Junction-to-Ambient -- 110 Units o C/W * When mounted on the minimum pad size recommended (PCB Mount). Rev. B ©1999 Fairchild Semiconductor Corporation P-CHANNEL POWER MOSFET SFR/U9210 Electrical Characteristics (TC=25oC unless otherwise specified) Symbol Characteristic BVDSS Drain-Source Breakdown Voltage ∆BV/∆TJ Breakdown Voltage Temp. Coeff. VGS(th) IGSS IDSS RDS(on) Min. Typ. Max. Units -200 -- --- -2.0 -- -4.0 Gate-Source Leakage , Forward -- -- -100 Gate-Source Leakage , Reverse -- -- 100 -- -- -10 -- -- -100 -- -- 3.0 Ω VGS=-10V,ID=-0.8A 4 O Ω VDS=-40V,ID=-0.8A 4 O Gate Threshold Voltage Drain-to-Source Leakage Current Static Drain-Source On-State Resistance -- 1.0 -- Ciss Input Capacitance -- 220 285 Coss Output Capacitance -- 45 65 Crss Reverse Transfer Capacitance -- 16 25 td(on) Turn-On Delay Time -- 10 30 Rise Time -- 20 50 Turn-Off Delay Time -- 27 65 Fall Time -- 12 35 Qg Total Gate Charge -- 9 11 Qgs Gate-Source Charge -- 1.8 -- Qgd Gate-Drain(£¢Miller£¢) Charge -- 4.8 -- tf See Fig 7 -0.2 Forward Transconductance td(off) VGS=0V,ID=-250µA o V/ C ID=-250µA -- gfs tr V Test Condition V nA µA pF VDS=-5V,ID=-250µA VGS=-30V VGS=30V VDS=-200V o VDS=-160V,TC=125 C VGS=0V,VDS=-25V,f =1MHz See Fig 5 VDD=-100V,ID=-1.75A, ns RG=18 Ω See Fig 13 4 O 5 O VDS=-160V,VGS=-10V, nC ID=-1.75A See Fig 6 & Fig 12 4 O 5 O Source-Drain Diode Ratings and Characteristics Symbol Characteristic Min. Typ. Max. Units Test Condition IS Continuous Source Current -- -- -1.6 ISM Pulsed-Source Current 1 O -- -- -6.4 VSD Diode Forward Voltage O -- -- -4.0 V TJ=25 C,IS=-1.6A,VGS=0V trr Reverse Recovery Time -- 110 -- ns TJ=25 C,IF=-1.75A Qrr Reverse Recovery Charge -- 0.42 -- µC diF/dt=100A/µs 4 A Notes ; 1 Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature O o 2 L=70mH, I =-1.6A, V =-50V, R =27Ω*, Starting T =25 C O AS DD G J 3 O ISD <_-1.75A, di/dt <_ 250A/µs, VDD <_ BVDSS , Starting T J =25oC 4 Pulse Test : Pulse Width = 250 µs, Duty Cycle < _ 2% O 5 Essentially Independent of Operating Temperature O ©1999 Fairchild Semiconductor Corporation Integral reverse pn-diode in the MOSFET o o 4 O P-CHANNEL POWER MOSFET SFR/U9210 Fig 1. Output Characteristics Fig 2. Transfer Characteristics V GS -ID , Drain Current -ID , Drain Current 100 [A] - 15 V - 10 V - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 V Bottom : - 4.5 V [A] Top : @ Notes : 1. 250 µs Pulse Test 2. TC = 25 oC 10-1 10-1 100 100 150 oC 25 C 10-1 101 2 4 8 10 Fig 4. Source-Drain Diode Forward Voltage [A] Fig 3. On-Resistance vs. Drain Current 10 -IDR , Reverse Drain Current RDS(on) , [Ω ] Drain-Source On-Resistance 6 -VGS , Gate-Source Voltage [V] 8 6 VGS = -10 V 4 2 VGS = -20 V @ Note : TJ = 25 oC 0 1 2 3 4 5 6 100 150 oC 7 0.5 -ID , Drain Current [A] Coss= Cds+ Cgd Crss= Cgd 300 C oss 200 @ Notes : 1. VGS = 0 V 2. f = 1 MHz 100 101 -VDS , Drain-Source Voltage [V] ©1999 Fairchild Semiconductor Corporation -VGS , Gate-Source Voltage Ciss= Cgs+ Cgd ( Cds= shorted ) 0 100 1.5 2.0 2.5 3.0 Fig 6. Gate Charge vs. Gate-Source Voltage [V] Fig 5. Capacitance vs. Drain-Source Voltage C rss 1.0 -VSD , Source-Drain Voltage [V] 400 C iss @ Notes : 1. VGS = 0 V 2. 250 µs Pulse Test 25 oC 10-1 0 [pF] 3. 250 µs Pulse Test - 55 oC -VDS , Drain-Source Voltage [V] Capacitance @ Notes : 1. VGS = 0 V 2. VDS = -40 V o VDS = -40 V VDS = -100 V VDS = -160 V 10 5 @ Notes : ID =-1.75 A 0 0 2 4 6 QG , Total Gate Charge [nC] 8 10 P-CHANNEL POWER MOSFET Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature RDS(on) , (Normalized) 1.2 1.1 1.0 @ Notes : 1. VGS = 0 V 2. ID = -250 µA 0.9 0.8 -75 -50 -25 0 25 50 75 100 125 150 Drain-Source On-Resistance -BVDSS , (Normalized) Drain-Source Breakdown Voltage SFR/U9210 3.0 2.5 2.0 1.5 1.0 0.0 -75 175 @ Notes : 1. VGS = -10 V 2. ID = -0.9 A 0.5 -50 -25 o Fig 9. Max. Safe Operating Area [A] 25 50 75 100 125 150 175 Fig 10. Max. Drain Current vs. Case Temperature 101 [A] 2.0 Operation in This Area is Limited by R DS(on) -ID , Drain Current -ID , Drain Current 0 TJ , Junction Temperature [oC] TJ , Junction Temperature [ C] 0.1 ms 1 ms 100 10 ms DC @ Notes : 1. TC = 25 oC 10-1 2. TJ = 150 oC 3. Single Pulse 100 101 1.6 1.2 0.8 0.4 0.0 25 102 50 75 100 Tc , Case Temperature [oC] -VDS , Drain-Source Voltage [V] Fig 11. Thermal Response D=0.5 θJC Z @ Notes : 1. Zθ J C (t)=6.58 o C/W Max. 2. Duty Factor, D=t1 /t 2 0.2 10 0 0.1 3. TJ M -T C =P D M *Z θ J C (t) 0.05 (t) , Thermal Response 10 1 P.DM 0.02 t1. t2. 0.01 10- 1 10- 5 single pulse 10- 4 10 - 3 10 - 2 10 - 1 t 1 , Square Wave Pulse Duration ©1999 Fairchild Semiconductor Corporation 100 [sec] 10 1 125 150 P-CHANNEL POWER MOSFET SFR/U9210 Fig 12. Gate Charge Test Circuit & Waveform “ Current Regulator ” 50KΩ 12V VGS Same Type as DUT Qg 200nF -10V 300nF VDS Qgd Qgs VGS DUT -3mA R1 R2 Current Sampling (IG) Resistor Charge Current Sampling (ID) Resistor Fig 13. Resistive Switching Test Circuit & Waveforms RL t on Vout td(on) VDD Vin ( 0.5 rated VDS ) RG Vin t off tr td(off) tf 10% DUT -10V Vout 90% Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD LL VDS Vary tp to obtain required peak ID tp ID VDD RG C VDD -10V tp ©1999 Fairchild Semiconductor Corporation VDS (t) ID (t) DUT IAS BVDSS Time P-CHANNEL POWER MOSFET SFR/U9210 Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT -IS L Driver VGS RG VGS VGS ( Driver ) Compliment of DUT (N-Channel) VDD • dv/dt controlled by “RG” • IS controlled by Duty Factor “D” Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current IRM IS ( DUT ) di/dt IFM , Body Diode Forward Current Vf VDS ( DUT ) Body Diode Forward Voltage Drop Body Diode Recovery dv/dt ©1999 Fairchild Semiconductor Corporation VDD TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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