EDI816256CA-RP HI-RELIABILITY PRODUCT 256Kx16 PLASTIC MONOLITHIC SRAM FEATURES The EDI816256CA is a ruggedized plastic 256Kx16 SRAM that allows the user to capitalize on the cost advantage of using a plastic component while not sacrificing all of the reliability available in a full military device. ■ 256Kx16 bit CMOS Static ■ Random Access Memory • Access Times of 15, 17, 20, 25ns The EDI816256CA uses 16 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device allows upper and lower byte access by use of the data byte control pins (LB, UB). • Data Retention Function (LPA version) • TTL Compatible Inputs and Outputs • Fully Static, No Clocks Extended temperature testing is performed with the test patterns developed for use on WEDC’s fully compliant 256Kx16 SRAMs. WEDC fully characterizes devices to determine the proper test patterns for testing at temperature extremes. This is critical because the operating characteristics of device change when it is operated beyond the commercial guarantee a device that operates reliably in the field at temperature extremes. Users of WEDC’s ruggedized plastic benefit from WEDC’s extensive experience in characterizing SRAMs for use in military systems. ■ Center Power/Ground Pins (Revolutionary) ■ 44 lead JEDEC Approved Revolutionary Pinout • Plastic SOJ Package ■ Single +5V (±10%) Supply Operation WEDC ensures Low Power devices will retain data in Data Retention mode by characterizing the devices to determine the appropriate test conditions. This is crucial for systems operating at 40°C or below and using dense memories such as 256Kx16s.WEDC’s ruggedized plastic SOJ is footprint compatible with WEDC’s full military ceramic 44 pin SOJ. PIN CONFIGURATION TOP VIEW A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 May 1999 Rev. 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 PIN DESCRIPTION A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 1 A0-17 Address Inputs LB Lower-Byte Control (I/O1-8) UB Upper-Byte Control (I/O9-16) I/O1-16 Data Input/Output CS Chip Select OE Output Enable WE Write Enable VCC +5.0V Power VSS Ground NC No Connection White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 EDI816256CA-RP TRUTH TABLE CS WE OE H L L X H X X H X L H L L L X LB UB X X H L H L L H L Mode X X H H L L H L L Data I/O Not Select I/O9-16 High Z Standby Output Disable High Z High Z Active Data Out High Z Data Out Data In High Z Data In High Z Data Out Data Out High Z Data In Data In Read Write Active Active RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS Parameter Power I/O1-8 High Z Symbol Min Max Unit Symbol Min Max Unit Operating Temperature (Mil.) TA -55 +125 °C Supply Voltage VCC 4.5 5.5 V Operating Temperature (Ind.) TA -40 +85 °C Input High Voltage VIH 2.2 V CC + 0.5 V Storage Temperature TSTG -65 +150 °C Input Low Voltage VIL -0.3 +0.8 V VG -0.5 Vcc + 0.5 V Operating Temperature (Mil.) TA -55 +125 °C VCC -0.5 7.0 V Operating Temperature (Ind.) TA -40 +85 °C Signal Voltage Relative to VSS Supply Voltage Parameter CAPACITANCE (TA = +25°C) Parameter Symbol Condition Input capacitance CIN VIN = 0V, f = 1.0MHz Max Unit 6 pF Output capicitance COUT VOUT = 0V, f = 1.0MHz 8 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 5.0V, V SS = 0V, TA = -55°C to +125°C) Parameter Sym Conditions Min Max Operating Power Supply Current I CC1 WE, CS = VIL , II/O = 0mA, Min Cycle — 300 mA Standby (TTL) Power Supply Current Full Standby Power Supply Current I CC2 I CC3 CS ≥ VIH, VIN ≤ V IL, VIN ≥ V IH CS ≥ V CC-0.2V VIN ≥ VCC-0.2V or V IN ≤ 0.2V — — — 60 25 15 mA mA mA CA LPA Units Input Leakage Current ILI VIN = 0V to VCC -10 10 µA Output Leakage Current I LO V I/O = 0V to VCC -10 10 µA Output High Voltage V OH I OH =-4mA 2.4 — V Output Low Voltage VOL I OL = 8mA — 0.4 V White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 2 EDI816256CA-RP AC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol Read Cycle -15 Min Read Cycle Time t RC Address Access Time t AA -17 Max Min 15 Max t OH Chip Select Access Time t ACS Min 17 Max 0 ns 25 ns 25 ns 12 ns 0 17 ns 20 Output Enable to Output Valid t OE Chip Select to Output in Low Z t CLZ 1 5 5 5 5 Output Enable to Output in Low Z t OLZ 1 0 0 0 0 Chip Disable to Output in High Z t CHZ 1 7 7 7 8 Output Disable to Output in High Z t OHZ 1 7 7 7 8 ns t BA 10 10 10 12 ns LB, UB Access Time 10 Max 20 0 15 Min Units 25 17 0 -25 20 15 Output Hold from Address Change -20 LB, UB Enable to Low Z Output t BLZ 1 LB, UB Disable to High Z Output t BHZ 1 10 0 10 0 0 7 ns ns ns 0 7 ns 7 8 ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol Write Cycle -15 Min -17 Max Min -20 Max Min -25 Max Min Units Max Write Cycle Time t WC 15 17 20 25 ns Chip Select to End of Write t CW 12 15 15 17 ns Address Valid to End of Write t AW 12 15 15 17 ns Data Valid to End of Write t DW 10 10 10 12 ns Write Pulse Width t WP 12 15 15 17 ns Address Setup Time t AS 0 0 0 0 ns Address Hold Time t AH 0 0 0 0 ns Output Active from End of Write t OW 1 0 0 0 0 Write Enable to Output in High Z t WHZ 1 8 8 ns 8 8 ns Data Hold Time t DH 0 0 0 0 ns LB, UB Valid to End of Write t BW 12 15 16 18 ns 1. This parameter is guaranteed by design but not tested. AC TEST CIRCUIT AC TEST CONDITIONS I OL Parameter Current Source VZ D.U.T. ≈ 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source 3 Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. V Z is typically the midpoint of VOH and V OL. I OL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 EDI816256CA-RP TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA CS tACS tCHZ tBA tBLZ tCLZ tBHZ LB, UB tRC ADDRESS tAA OE tOH DATA I/O tOE tOLZ PREVIOUS DATA VALID DATA VALID tOHZ DATA I/O DATA VALID HIGH IMPEDANCE READ CYCLE 1 (CS = OE = VIL, UB or LB = VIL, WE = VIH) READ CYCLE 2 (WE = VIH) WRITE CYCLE - WE CONTROLLED tWC ADDRESS tAW tAH tCW CS tBW LB, UB tAS tWP WE tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, WE CONTROLLED WRITE CYCLE - CS CONTROLLED WRITE CYCLE - LB, UB CONTROLLED tWC tWC ADDRESS ADDRESS tAS tAW WS32K32-XHX t tAH tCW tAS CS tAH tCW CS tBW tBW LB, UB LB, UB tWP tWP WE WE tDW DATA I/O AW tDH tDW DATA I/O DATA VALID WRITE CYCLE 2, CS CONTROLLED White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520 DATA VALID WRITE CYCLE 3, LB, UB CONTROLLED 4 tDH EDI816256CA-RP 44 LEAD, PLASTIC SOJ (400 mil) 28.7 (1.130) 28.4 (1.120) 11.30 (0.445) 11.05 (0.435) 10.16 (0.400) TYP 9.65 (0.380) #23 9.14 (0.360) #44 #22 #1 0.66 (0.026) 0.81 (0.032) 0.69 (0.027) MIN 3.76 (0.148) MAX 0.004" max 0.95 (0.0375) TYP 1.27 (0.05) TYP 0.38 (0.015) 0.53 (0.021) DIMENSIONS IN MILLIMETERS AND (INCHES) ORDERING INFORMATION EDI 8 16 256 CA X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 256Kx16 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: M44 = 44 lead Plastic SOJ DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C 5 White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520