Order this document by BS108/D SEMICONDUCTOR TECHNICAL DATA N–Channel Enhancement Mode This TMOS FET is designed for high voltage, high speed switching applications such as line drivers, relay drivers, CMOS logic, microprocessor or TTL to high voltage interface and high voltage display drivers. 1 DRAIN • Low Drive Requirement, VGS = 3.0 V max • Inherent Current Sharing Capability Permits Easy Paralleling of many Devices 200 VOLTS N–CHANNEL TMOS POWER FET LOGIC LEVEL 2 GATE 3 SOURCE 1 2 3 CASE 29–04, STYLE 30 TO–92 MAXIMUM RATINGS Rating Symbol Value Unit Drain – Source Voltage VDSS 200 Vdc Gate–Source Voltage VGS ±20 Vdc Drain Current Continuous(1) Pulsed(2) ID IDM 250 500 mAdc Total Power Dissipation @ TA = 25°C Derate above TA = 25°C PD Operating and Storage Temperature Range TJ, Tstg 350 6.4 mW mW/°C – 55 to +150 °C 1. The Power Dissipation of the package may result in a lower continuous drain current. 2. Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%. v TMOS is a registered trademark of Motorola, Inc. Motorola, Inc. 1997 v BS108 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max 200 — — — — 30 — — 10 0.5 — 1.5 — — — — 10 8.0 — — 25 — — 150 — — 30 — — 10 Unit OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0, ID = 10 µA) V(BR)DSS Zero Gate Voltage Drain Current (VDSS = 130 Vdc, VGS = 0) Vdc IDSS Gate–Body Leakage Current (VGS = 15 Vdc, VDS = 0) nAdc IGSSF nAdc ON CHARACTERISTICS (2) Gate Threshold Voltage (ID = 1.0 mA, VDS = VGS) VGS(th) Static Drain–to–Source On–Resistance (VGS = 2.0 Vdc, ID = 50 mA) (VGS = 2.8 Vdc, ID = 100 mA) rDS(on) Drain Cutoff Current (VGS = 0.2 V, VDS = 70 V) Vdc Ohms mA IDSX DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Ciss Output Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Coss Reverse Transfer Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Crss pF pF pF SWITCHING CHARACTERISTICS Turn–On Time (See Figure 1) td(on) — — 15 ns Turn–Off Time (See Figure 1) td(off) — — 15 ns 2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle = 2.0%. RESISTIVE SWITCHING +25 V TO SAMPLING SCOPE 50 Ω INPUT 23 PULSE GENERATOR 20 dB 50 Ω ATTENUATOR Vin 40 pF 50 50 1.0 M ton Vout toff 90% 90% OUTPUT V INVERTED out 10% 90% 10 V INPUT Figure 1. Switching Test Circuit 2 Vin 50% 10% PULSE WIDTH 50% Figure 2. Switching Waveforms Motorola Small–Signal Transistors, FETs and Diodes Device Data BS108 PACKAGE DIMENSIONS A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. DIMENSION F APPLIES BETWEEN P AND L. DIMENSION D AND J APPLY BETWEEN L AND K MINIMUM. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. B R P L F SEATING PLANE K D X X G J H V C SECTION X–X 1 N N CASE 029–04 (TO–226AA) ISSUE AD Motorola Small–Signal Transistors, FETs and Diodes Device Data DIM A B C D F G H J K L N P R V INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.022 0.016 0.019 0.045 0.055 0.095 0.105 0.015 0.020 0.500 ––– 0.250 ––– 0.080 0.105 ––– 0.100 0.115 ––– 0.135 ––– MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.41 0.55 0.41 0.48 1.15 1.39 2.42 2.66 0.39 0.50 12.70 ––– 6.35 ––– 2.04 2.66 ––– 2.54 2.93 ––– 3.43 ––– STYLE 30: PIN 1. DRAIN 2. GATE 3. SOURCE 3 BS108 Motorola reserves the right to make changes without further notice to any products herein. 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