STB3NC60 N - CHANNEL 600V - 3.3Ω - 3A - D2PAK/I2PAK PowerMESH ΙΙ MOSFET T YPE STB3NC60 ν ν ν ν ν V DSS R DS(on) ID 600 V < 3.6 Ω 3 A TYPICAL RDS(on) = 3.3 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED 3 1 3 12 DESCRIPTION The PowerMESH II is the evolution of the first generation of MESH OVERLAY . The layout refinements introduced greatly improve the Ron*area figure of merit while keeping the device at the leading edge for what concerns switching speed, gate charge and ruggedness. APPLICATIONS ν HIGH CURRENT, HIGH SPEED SWITCHING ν SWITCH MODE POWER SUPPLIES (SMPS) ν DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE I2PAK TO-262 (Suffix ”-1”) D2PAK TO-263 (Suffix ”T4”) INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symb ol V DS V DGR V GS Parameter Value Unit 600 V Drain- gate Voltage (R GS = 20 kΩ) 600 V G ate-source Voltage ± 30 V 3 A 1.9 A Drain-source Voltage (VGS = 0) o ID Drain Current (continuous) at Tc = 25 C ID Drain Current (continuous) at Tc = 100 C I DM (•) P tot o Drain Current (pulsed) o T otal Dissipation at T c = 25 C Derating Factor dv/dt( 1 ) T s tg Tj Peak Diode Recovery voltage slope Storage Temperature Max. O perating Junction Temperature (•) Pulse width limited by safe operating area February 2000 12 A 80 W 0.64 W/ o C 4 V/ns -65 to 150 o C 150 o C (1) ISD ≤3A, di/dt ≤ 100 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/9 STB3NC60 THERMAL DATA R thj- ca se R t hj-a mb R thc -sin k Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose 1.56 o C/W 62.5 0.5 300 o C/W C/W o C Max Valu e Unit 3 A 100 mJ o AVALANCHE CHARACTERISTICS Symbo l Parameter I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max) E AS Single Pulse Avalanche Energy o (starting Tj = 25 C, I D = IAR , V DD = 50 V) ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V ( BR)DSS Parameter Drain-source Breakdown Voltage Test Cond itions ID = 250 µA VDS = Max Rating Zero G ate Voltage Drain Current (V GS = 0) VDS = Max Rating I GSS Gate-body Leakage Current (VDS = 0) Typ . Max. 600 V GS = 0 I DSS Min. Un it V Tc = 125 o C VGS = ± 30 V 1 50 µA µA ± 100 nA ON (∗) Symbo l Parameter Test Cond itions V GS(th ) Gate Threshold Voltage VDS = V GS ID = 250 µA R DS(on ) Static Drain-source On Resistance VGS = 10V I D = 1.5 A I D(on) On State Drain Current VDS > I D(on ) x R DS(on )max VGS = 10 V Min. Typ . Max. Un it 2 3 4 V 3.3 3.6 Ω 3 A DYNAMIC Symbo l g fs (∗) C is s C os s C rs s 2/9 Parameter Test Cond itions Forward Transconductance VDS > I D(on ) x R DS(on )max Input Capacitance Output Capacitance Reverse T ransfer Capacitance VDS = 25 V f = 1 MHz I D = 1.5 A V GS = 0 Min. Typ . Max. Un it 2 S 400 57 7 pF pF pF STB3NC60 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Cond itions Min. Typ . Max. Un it t d( on) tr Turn-on T ime Rise Time VDD = 300 V I D = 1.5 A VGS = 10 V R G = 4.7 Ω (see test circuit, figure 3) 9 13 Qg Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 480 V 13 2.3 4.4 18.2 nC nC nC Typ . Max. Un it ID = 3 A V GS = 10 V ns ns SWITCHING OFF Symbo l t r(Vof f ) tf tc Parameter Off-voltage Rise Time Fall T ime Cross-over Time Test Cond itions Min. 13 15 21 VDD = 480 V I D = 3 A R G = 4.7 Ω VGS = 10 V (see test circuit, figure 5) ns ns ns SOURCE DRAIN DIODE Symbo l Parameter Test Cond itions I SD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward O n Voltage ISD = 3 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 3 A di/dt = 100 A/µs Tj = 150 o C VDD = 100 V (see test circuit, figure 5) t rr Q rr IRRM Min. Typ . V GS = 0 Max. Un it 3 12 A A 1.6 V 420 ns 1.5 µC 7.1 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area for D2PAK/I2PAK Thermal Impedancefor D2PAK/I2PAK 3/9 STB3NC60 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STB3NC60 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STB3NC60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STB3NC60 TO-262 (I2PAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. 4.3 4.6 0.169 0.1 81 A1 2.49 2.69 0.098 0.1 06 B 0.7 0.93 0.027 0.0 36 B1 1.2 1.38 0.047 0.0 54 B2 1.25 1.4 0.049 0.0 55 C 0.45 0.6 0.017 0.0 23 C2 1.21 1.36 0.047 0.0 53 D 8.95 9.35 0.352 0.3 68 e 2.44 2.64 0.096 0.1 04 E 10 1 0.2 8 0.393 0.4 04 L 13.2 13.5 0.519 0.5 31 L1 3.48 3.78 0.137 0.1 49 L2 1.27 1.4 0.050 0.0 55 E e B B2 C2 A1 A C A L1 L2 D L P0 11 P5/C 7/9 STB3NC60 TO-263 (D2PAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.3 4.6 0.169 0.1 81 A1 2.49 2.69 0.098 0.1 06 B 0.7 0.93 0.027 0.0 36 B2 1.25 1.4 0.049 0.0 55 C 0.45 0.6 0.017 0.0 23 C2 1.21 1.36 0.047 0.0 53 D 8.95 9.35 0.352 0.3 68 E 10 1 0.2 8 0.393 0.4 04 G 4.88 5.28 0.192 0.2 08 L 15 1 5.8 5 0.590 0.6 24 L2 1.27 1.4 0.050 0.0 55 L3 1.4 1.75 0.055 0.0 68 E A C2 L2 D L L3 B2 B A1 C G P0 11 P6/C 8/9 STB3NC60 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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