STE180N10 N - CHANNEL 100V - 5.5 mΩ - 180A - ISOTOP POWER MOSFET TYPE STE180N10 ■ ■ ■ ■ ■ V DSS R DS(on) ID 100 V < 7 mΩ 180 A TYPICAL RDS(on) = 5.5 mΩ 100% AVALANCHE TESTED LOW INTRINSIC CAPACITANCE GATE CHARGE MINIMIZED REDUCED VOLTAGE SPREAD INDUSTRIAL APPLICATIONS: ■ SMPS & UPS ■ MOTOR CONTROL ■ WELDING EQUIPMENT ■ OUTPUT STAGE FOR PWM, ULTRASONIC CIRCUITS ISOTOP INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symb ol V DS V DGR V GS Value Un it Drain-source Voltage (V GS = 0) Parameter 100 V Drain- gate Voltage (R GS = 20 kΩ) 100 V ± 20 V G ate-source Voltage o ID Drain Current (continuous) at Tc = 25 C 180 A ID Drain Current (continuous) at Tc = 100 C o 119 A Drain Current (pulsed) 540 A T otal Dissipation at Tc = 25 C 450 W Derating Factor 3.6 W /o C I DM (•) P tot V ISO T s tg Tj o Insulation Withstand Voltage (AC-RMS) Storage T emperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area February 1999 2500 V -55 to 150 o C 150 o C ( 1) ISD ≤180 Α, di/dτ ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/8 STE180N10 THERMAL DATA R thj -case R thc-h Thermal Resistance Junction-case Thermal Resistance Case-heatsink With conductive Grease Applied Max 0.27 o C/W Max 0.05 o C/W AVALANCHE CHARACTERISTICS Symbo l Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 60 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 25 V) 720 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 1 mA VGS = 0 I DSS V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) Min. Typ. Max. 100 Unit V 50 500 µA µA ± 400 nA Typ. Max. Unit 3 4 V 5.5 7 mΩ T c = 125 oC V GS = ± 20 V ON (∗) Symbo l Parameter Test Con ditions ID = 250 µA V GS(th) Gate Threshold Voltage V DS = V GS R DS(on) Static Drain-source On Resistance V GS = 10 V I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. 2 I D = 90 A 180 A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/8 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D = 90 A V GS = 0 Min. Typ. 70 Max. Unit S 18 4 0.5 nF nF nF STE180N10 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(on) tr Turn-on Delay T ime Rise Time V DD = 50 V I D = 90 A R G = 4.7 Ω V GS = 10 V (Resistive Load, see fig. 3) 65 230 Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 80 V ID = 180 A V GS = 10 V 485 90 210 680 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbo l Parameter Test Con ditions Min. t d(on) tr Turn-off Delay T ime Fall T ime V DD = 50 V I D = 90 A V GS = 10 V R G = 4.7 Ω (Resistive Load, see fig. 3) 280 100 ns ns tr (Voff) tf tc Off-voltage Rise T ime Fall T ime Cross-over Time V DD = 80 V I D = 180 A V GS = 10 V R G = 4.7 Ω (Induct ive Load, see fig. 5) 100 170 260 ns ns ns SOURCE DRAIN DIODE Symbo l Parameter Test Con ditions ISD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 180 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 180 A di/dt = 100 A/µs T j = 150 o C V DD = 50 V (see test circuit, fig. 5) t rr Q rr I RRM Min. Typ. V GS = 0 Max. Unit 180 540 A A 1.5 V 250 ns 1875 µC 15 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 STE180N10 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STE180N10 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STE180N10 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STE180N10 ISOTOP MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 11.8 12.2 0.466 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 J 4.1 4.3 0.161 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 N 4 O 7.8 0.157 0.157 8.2 0.307 0.322 A G B O F E H D N J C K L M 7/8 STE180N10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all information previously supplied. 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