TDA7346 DIGITAL CONTROLLED SURROUND SOUND MATRIX 1 STEREO INPUT THREE INDEPENDENT SURROUND MODES ARE AVAILABLE MOVIE, MUSIC AND SIMULATED - MUSIC: 4 SELECTABLE RESPONSES - MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES TWO INDEPENDENT INPUT ATTENUATORS IN 0.31dB FOR BALANCE FACILITY ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS DIP20 SO20 ORDERING NUMBER: TDA7346 (DIP20) TDA7346D (SO20) DESCRIPTION The TDA7346 reproduces surround sound by using phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor net- works and switches combined with operational amplifiers. BLOCK DIAGRAM 5.6nF LP1 100nF 680nF 100nF 4.7nF 22nF 22nF HP1 HP2 PS1 PS2 PS3 PS4 RLP1 RHP1 RPS1 RPS2 RPS3 RPS4 PS1 90Hz PS2 4KHz PS3 400Hz PS4 400Hz L-in R5 100K R6 - - + MIXING AMP Lout SIM + MUSIC PHASE SHIFTER MOVIE/ MUSIC + - OFF MOVIE/SIM L-R SCL I2C BUS DECODER LATCHES SDA DIG GND + ADDR LPF 9KHz EFFECT CONTROL REAR 100nF MIXING AMP R-in SUPPLY 100K VS February 1997 Rout AGND CREF C5 22µF LP D94AU122A 1.2nF 1/14 TDA7346 ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Value Operating Supply Voltage T amb Operating Ambient Temperature Tstg Storage Temperature Range Unit 10.5 V -40 to 85 °C -55 to +150 °C PIN CONNECTION PS1 1 20 PS2 VS 2 19 LP1 CREF 3 18 HP1 L-in 4 17 HP2 LP 5 16 R-in REAR 6 15 PS3 Lout 7 14 PS4 SDA 8 13 Rout SCL 9 12 ADDR 10 11 AGND DIG GND D94AU128 THERMAL DATA Symbol R th j-pins Description Thermal Resistance Junction-pins Ma x. Value Unit 85 °C/W QUICK REFERENCE DATA Symbol Min. Typ. Max. VS Supply Voltage Parameter 7 9 10.2 VCL Max. input signal handling 2 Unit V Vrms THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.02 S/N Signal to Noise Ratio V out = 1Vrms (mode = OFF) 106 dB SC Channel Separation f = 1KHz 70 dB 2/14 0.1 % TDA7346 TEST CIRCUIT HP1 680nF C16 HP2 0.1µF C17 L-in REAR Lout SCL SDA 6 7 9 8 18 LP 5 1.2nF C6 17 R-in 16 4 VS 0.1µF C7 LP1 19 5.6nF C15 10µF C1 TDA7346 2 PS1 1 100nF C14 100nF C2 PS3 22nF C4 PS4 22nF C5 15 20 14 3 13 11 10 12 Rout AGND DIG GND ADDR PS2 4.7nF C13 CREF 22µF C3 D93AU040C ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, all controls flat (G = 0),Effect Ctrl = -6dB, MODE = OFF; f = 1KHz unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 7 9 10.2 V 10 mA 60 80 dB 100 KΩ 2.5 Vrms 3.0 Vrms 20 dB SUPPLY VS Supply Voltage IS Supply Current SVR Ripple Rejection LCH / RCH out, Mode = OFF INPUT STAGE R II Input Resistance V CL Clipping Level THD = 0.3%; Lin or Rin 2 THD = 0.3%; Rin + Lin (2) C RANGE Control Range AVMIN Min. Attenuation AVMAX Max. Attenuation ASTEP Step Resolution VDC DC Steps -1 0 1 20 adjacent att. step dB dB 0.31 dB 0 mV EFFECT CONTROL C RANGE SSTEP Control Range Step Resolution - 21 -6 1 dB dB 3/14 TDA7346 ELECTRICAL CHARACTERISTICS (continued) SURROUND SOUND MATRIX Symbol Min. Typ. Max. Unit GOFF In-phase Gain (OFF) Parameter Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin → Rout L in → Lout Test Condition -1.5 0 1.5 dB DGOFF LR In-phase Gain Difference (OFF) -1.5 0 1.5 dB GMOV1 In-phase Gain (Movie 1) RPS1, RPS2, RPS3, RPS4 = POR Preset Mode OFF, Input signal of 1kHz, 1.4 Vp-p (Rin → Rout), (Lin → Lout) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in → Rout, Lin → Lout GMOV2 In-phase Gain (Movie 2) RPS1, RPS2, RPS3, RPS4 = POR Preset DGMOV 7 dB Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in → Rout, Lin → Lout 8 dB LR In-phase Gain Difference (Movie) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) – (Lin → Lout) 0 dB GMUS1 In-phase Gain (Music 1) RPS1 = POR PRESET 6 dB GMUS2 In-phase Gain (Music 2) RPS1 = POR PRESET Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) – (Lin → Lout) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p R in → Rout, Lin → Lout 7.5 dB DGMUS LR In-phase Gain Difference (Music) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) – (Lin → Lout) 0 dB LMON1 Simulated L Output 1 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin → Lout 4.5 dB LMON2 Simulated L Output 2 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin → Lout – 4.0 dB L MON3 Simulated L Output 3 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated Mode, EffectCtrl = 6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Lout 7.0 dB R MON1 Simulated R Output 1 RPS1, RPS2, RPS3, RPS4 = POR Preset – 4.5 dB R MON2 Simulated R Output 2 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated Mode, EffectCtrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin →R out Simulated Mode, EffectCtrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin →R out 3.8 dB R MON3 Simulated R Output 3 RPS1, RPS2, RPS3, RPS4 = POR Preset Simulated Mode, EffectCtrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Rout – 20 dB 10 KΩ 4/14 R LP1 Low Pass Filter Resistance RPS1 Phase Shifter 1 Resistance at POR 17.95 kΩ RPS2 Phase Shifter 2 Resistance at POR 8.465 KΩ RPS3 Phase Shifter 3 Resistance at POR 18.050 KΩ RPS2 Phase Shifter 4 Resistance at POR 18.050 KΩ RHPI High Pass Filter Resistance 60 KΩ RLPF LP Pin Impedance 10 KΩ TDA7346 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. 2 2.5 Max. Unit AUDIO OUTPUTS VOCL Clipping Level d = 0.3% Vrms R OUT Output resistance 100 200 300 Ω VOUT DC Voltage Level 3.5 3.8 4.1 V GENERAL N O(OFF) Output Noise (OFF) BW = 20Hz to 20KHz Rout and Lout measurement 8 µVrms NO(MOV) Output Noise (Movie) Mode =Movie , BW = 20Hz to 20KHz Rout and Lout measurement 30 µVrms N O(MUS) Output Noise (Music) Mode = Music , BW = 20Hz to 20KHz, Rout and Lout measurement 30 µVrms NO(MON) Output Noise (Simulated) Mode = Simulated, BW = 20Hz to 20KHz Rout and Lout measurement 30 µVrms d Distorsion Av = 0 ; Vin = 1Vrms SC Channel Separation 0.02 0.1 70 % dB BUS INPUTS VIL Input Low Voltage VIH Input High Voltage 3 IIN Input Current -5 VO Output Voltage SDA Acknowledge IO = 1.6mA 1 V +5 µA V V 0.4 0.8 Note: (1) Bass and Treble response: The center frequency and the resonance quality can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network. (2) The peak voltage of the two input signals must be less then (Lin + Rin) peak • AVin < VS : 2 VS 2 5/14 TDA7346 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7346 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acFigure 3: Data Validity on the I2CBUS Figure 4: Timing Diagram of I2CBUS Figure 5: Acknowledge on the I2CBUS 6/14 knowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. TDA7346 address (the 8th bit of the byte must be 0). The TDA7346 must always acknowledge at the end of each transmitted byte. A sequence of data (N bytes + achnowledge). A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7346 TDA7346 ADDRESS first byte MSB S 1 1 0 1 LSB 1 1 A MSB LSB 0 ACK DATA MSB LSB DATA ACK ACK P Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 100kbits/s SOFTWARE SPECIFICATION Chip address 1 MSB 1 0 1 1 1 A 0 LSB A CHIP ADDRESS 0 DC (HEX) 1 DE (HEX) A = Logic level on pin ADDR A = 1 if ADDR pin = open A = 0 if ADDR pin = connected to ground Software Specification MSB LSB SUBADDRESS 0 0 A5 A4 A3 A2 A1 A0 0 1 A5 A4 A3 A2 A1 A0 INPUT ATTENUATION R 1 M1 M0 1 0 0 SIMULATED MODE 1 0 1 MUSIC MODE 1 1 0 1 1 1 1 1 1 1 M1 M0 1 B3 B2 B1 B0 EFFECT CONTROL 1 M1 M0 0 0 0 C1 C0 PHASE SHIFTER 4 CONTROL 1 M1 M0 0 0 1 C1 C0 PHASE SHIFTER 3 CONTROL 1 M1 M0 0 1 0 D1 D0 PHASE SHIFTER 2 CONTROL 1 M1 M0 0 1 1 E1 E0 PHASE SHIFTER 1 CONTROL INPUT ATTENUATION L SURROUND MODES MOVIE MODE 1 1 OFF MODE 7/14 TDA7346 INPUT ATTENUATION MSB LSB I A5 A4 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.3125 dB STEPS 0 -0.3125 -0.625 -0.9375 -1.25 -1.5625 -1.875 -2.1875 2.5 dB STEPS 0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 I = 0 Attenuation Input R I = 1 Attenuation Input L Example: to program an R input attenuation equal to -11.25 you have to send 00100100 EFFECT CONTROL (-6 / -21dB) MSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8/14 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 M0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB 1dB STEPS B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 TDA7346 PHASE SHIFTER 3, 4 MSB LSB C1 C0 RESISTOR VALUE (KΩ) 1 M1 M0 0 0 F 0 0 12.060 1 M1 M0 0 0 F 0 1 14.450 1 M1 M0 0 0 F 1 0 18.050 1 M1 M0 0 0 F 1 1 39.100 LSB RESISTOR VALUE (KΩ) F = 0 Phase Shifter 4 F = 1 Phase Shifter 3 PHASE SHIFTER 2 MSB D1 D0 1 M1 M0 0 1 0 0 0 5.640 1 M1 M0 0 1 0 0 1 6.770 1 M1 M0 0 1 0 1 0 8.465 1 M1 M0 0 1 0 1 1 18.300 LSB RESISTOR VALUE (KΩ) PHASE SHIFTER 1 MSB E1 E0 1 M1 M0 0 1 1 0 0 11.745 1 M1 M0 0 1 1 0 1 14.150 1 M1 M0 0 1 1 1 0 17.950 1 M1 M0 0 1 1 1 1 37.625 Example: to program MOVIE MODE with EFFECT control = -7dB with PHASE SHIFTER resistor = 11.745KΩ, PHASE SHIFTER 2 resistor = 6.77KΩ, PHASE SHIFTER 3 resistor = 12.06KΩ, PHASE SHIFTER 4 resistor = 18.05KΩ, you have to send in sequence 5 bytes: 11010001 11001100 11001001 11000100 11000010 POWER ON RESET INPUT ATTENUATION -19.375dB EFFECT CONTROL -20dB SURROUND MODE OFF MODE PHASE SHIFTER 1 RESISTOR VALUE 17.950 KΩ PHASE SHIFTER 2 RESISTOR VALUE 8.465 KΩ PHASE SHIFTER 3, 4 RESISTOR VALUE 18.050 KΩ 9/14 TDA7346 PIN: HP1 PIN: HP2 LP1 VS VS 10K 20µA 5.5K 60K HP2 60K GND 5.5K HP1 D94AU199 D94AU198 PIN: Lin, Rin PIN: LOUT, ROUT, REAR VS VS 20µA 20µA 100Ω 100K Vref D94AU204 D94AU123 PIN: SCL, SDA PIN: ADDR VS 20µA 100K D94AU205 10/14 20µA D94AU212 TDA7346 PIN: LP PIN: PS3, PS2 VS VS 20µA 20µA 10K 18.050K PS3A PS4A D94AU124 D94AU206 PIN: CREF PIN: PS2 VS VS 20µA 20K 20µA 8.465K 20K PS2A D94AU208 D94AU125 PIN: PS1 PIN: LP1 VS VS 20µA 20µA 17.95K 10K PS1A HP1 D94AU126 D94AU211 11/14 TDA7346 SO20 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. TYP. 2.65 0.1 MAX. 0.104 0.3 a2 0.004 0.012 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45° (typ.) D 12.6 13.0 0.496 0.512 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.4 7.6 0.291 0.299 L 0.5 1.27 0.020 0.050 M S 12/14 MIN. 0.75 0.030 8° (max.) TDA7346 DIP20 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 3.3 0.130 1.34 0.053 13/14 TDA7346 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGSTHOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1997 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 14/14