STMICROELECTRONICS VND920P

VND920P
®
DOUBLE CHANNEL HIGH SIDE SOLID STATE RELAY
TARGET SPECIFICATION
TYPE
VND920P
RDS(on)
16mΩ
IOUT
35 A (*)
VCC
36 V
(*) Per channel with all the output pins connected to the PCB.
CMOS COMPATIBLE INPUT
PROPORTIONAL LOAD CURRENT SENSE
■ SHORTED LOAD PROTECTION
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ OVERVOLTAGE CLAMP
■ THERMAL SHUTDOWN
■ CURRENT LIMITATION
■ PROTECTION AGAINST LOSS OF GROUND
AND LOSS OF VCC
■
■
SO-28 (DOUBLE ISLAND)
ORDER CODES
PACKAGE
SO-28
TUBE
VND920P
T&R
VND920P13TR
with one side connected to ground. Active VCC pin
voltage clamp protects the device against low
energy
spikes
(see
ISO7637
transient
compatibility table). Active current limitation
combined with thermal shutdown and automatic
restart protect the device against overload. Builtin analog current sense output delivers a current
proportional to the load current. Device
automatically turns off in case of ground pin
disconnection.
VERY LOW STAND-BY POWER DISSIPATION
■ REVERSE BATTERY PROTECTION (**)
■
DESCRIPTION
The VND920P is a double chip device made by
using
STMicroelectronics
VIPower
M0-3
Technology, intended for driving any kind of load
CONNECTION DIAGRAM (TOP VIEW)
VCC 1
1
28
GND 1
INPUT 1
CURRENT SENSE 1
NC
NC
VCC 1
OUTPUT 1
OUTPUT 1
OUTPUT 1
VCC 2
GND 2
INPUT 2
CURRENT SENSE 2
NC
NC
VCC 2
VCC1
OUTPUT 1
OUTPUT 1
OUTPUT 1
14
15
OUTPUT 2
OUTPUT 2
OUTPUT 2
OUTPUT 2
OUTPUT 2
OUTPUT 2
VCC 2
(**) See application schematic at page 10
October 2003 - Revision 1.2 (Working document)
1/18
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1
VND920P
BLOCK DIAGRAM
VCC 1
OVERVOLTAGE
DETECTION
VCC
CLAMP
UNDERVOLTAGE
DETECTION
GND 1
Power CLAMP
DRIVER
OUTPUT 1
LOGIC
INPUT 1
CURRENT LIMITER
VDS LIMITER
IOUT
K
CURRENT
SENSE 1
OVERTEMPERATURE
DETECTION
VCC 2
OVERVOLTAGE
DETECTION
VCC
CLAMP
UNDERVOLTAGE
DETECTION
GND 2
Power CLAMP
DRIVER
INPUT 2
OUTPUT 2
LOGIC
CURRENT LIMITER
VDS LIMITER
IOUT
OVERTEMPERATURE
DETECTION
2/18
K
CURRENT
SENSE 2
VND920P
ABSOLUTE MAXIMUM RATING (Per each channel)
Symbol
VCC
- VCC
- IGND
IOUT
- IOUT
IIN
VCSENSE
Parameter
DC Supply Voltage
Reverse DC Supply Voltage
DC Reverse Ground Pin Current
DC Output Current
Reverse DC Output Current
DC Input Current
Current Sense Maximum Voltage
Value
41
- 0.3
- 200
Internally Limited
- 21
+/- 10
-3
Unit
V
V
mA
A
A
mA
V
+15
V
- INPUT
4000
V
- CURRENT SENSE
2000
V
- OUTPUT
5000
V
- VCC
Maximum Switching Energy
5000
V
355
mJ
6.25 (**)
Internally limited
- 40 to 150
- 55 to 150
W
°C
°C
°C
Electrostatic Discharge (Human Body Model: R=1.5KΩ; C=100pF)
VESD
EMAX
Ptot
Tj
Tc
TSTG
(L=0.25mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=45A)
Power Dissipation Tl≤25°C
Junction Operating Temperature
Case Operating Temperature
Storage Temperature
(**) Per island
CURRENT AND VOLTAGE CONVENTIONS
IS2
IS1
VCC1
VCC1
VCC2
IOUT1
IIN1
OUTPUT1
INPUT1
VIN1
VCC2
IOUT2
IIN2
VIN2
VOUT1
ISENSE1
CURRENT SENSE 1
OUTPUT2
INPUT2
CURRENT SENSE 2
GROUND2
GROUND1
IGND1
VSENSE1
VOUT2
ISENSE2
VSENSE2
IGND2
3/18
VND920P
THERMAL DATA (Per island)
Symbol
Rthj-lead
Parameter
Thermal Resistance Junction-lead
Value
20
Unit
°C/W
Rthj-amb
Thermal Resistance Junction-ambient (one chip ON)
55 (*)
°C/W
Rthj-amb
Thermal Resistance Junction-ambient (two chips ON)
42 (*)
°C/W
(*) When mounted on a standard single-sided FR-4 board with 1cm2 of Cu (at least 35µm thick) connected to all VCC pins.
Horizontal mounting and no artificial air flow.
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C unless otherwise specified)
(Per island)
POWER
Symbol
VCC
VUSD
VOV
RON
Vclamp
Parameter
Operating Supply Voltage
Undervoltage Shut-down
Overvoltage Shut-down
On State Resistance
Clamp Voltage
Test Conditions
Min
5.5
3
36
IOUT=10A; Tj =25°C
16
Unit
V
V
V
mΩ
IOUT=10A
32
mΩ
IOUT=3A; VCC=6V
ICC=20mA (See note 1)
48
10
55
55
25
mΩ
V
µA
10
20
µA
5
50
0
5
3
mA
µA
µA
µA
µA
Typ
50
50
See
relative
diagram
See
relative
diagram
Max
Unit
µs
µs
Typ
Max
1.25
41
Off State; VCC=13V; VIN=VOUT=0V
IS
Supply Current
Typ
13
4
Off State; VCC=13V; VIN=VOUT=0V;
Tj =25°C
On State; VCC=13V; VIN=5V; IOUT=0A;
RSENSE=3.9KΩ
IL(off1)
IL(off2)
IL(off3)
IL(off4)
Off State Output Current
Off State Output Current
Off State Output Current
Off State Output Current
Max
36
5.5
VIN=VOUT=0V
VIN=0V; VOUT=3.5V
VIN=VOUT=0V; VCC=13V; Tj =125°C
VIN=VOUT=0V; VCC=13V; Tj =25°C
0
-75
Test Conditions
RL=1.3Ω (see figure 2)
RL=1.3Ω (see figure 2)
Min
SWITCHING (VCC=13V)
Symbol
td(on)
td(off)
Parameter
Turn-on Delay Time
Turn-off Delay Time
dVOUT/dt(on) Turn-on Voltage Slope
RL=1.3Ω (see figure 2)
dVOUT/dt(off) Turn-off Voltage Slope
RL=1.3Ω (see figure 2)
V/µs
V/µs
LOGIC INPUT
Symbol
VIL
IIL
VIH
IIH
VI(hyst)
VICL
Parameter
Input Low Level
Low Level Input Current
Input High Level
High Level Input Current
Input Hysteresis Voltage
Input Clamp Voltage
Test Conditions
VIN=1.25V
Min
1
3.25
VIN=3.25V
IIN=1mA
IIN=-1mA
10
0.5
6
6.8
-0.7
8
Unit
V
µA
V
µA
V
V
V
Note 1: Vclamp and V OV are correlated. Typical difference is 5V.
4/18
1
VND920P
ELECTRICAL CHARACTERISTICS (continued)
CURRENT SENSE (9V ≤ VCC ≤ 16V) (See Fig.1)
Symbol
K1
dK1/K1
K2
dK2/K2
K3
dK3/K3
ISENSEO
VSENSE
VSENSEH
RVSENSEH
tDSENSE
Parameter
IOUT/ISENSE
Current Sense Ratio Drift
IOUT/ISENSE
Current Sense Ratio Drift
IOUT/ISENSE
Current Sense Ratio Drift
Analog Sense Leakage
Current
Test Conditions
IOUT=1A; VSENSE=0.5V;
Tj= -40°C...150°C
IOUT=1A; VSENSE=0.5V;
Tj= -40°C...+150°C
IOUT=10A; VSENSE=4V; Tj=-40°C
Tj=25°C...150°C
IOUT=10A; VSENSE=4V;
Tj=-40°C...+150°C
IOUT=30A; VSENSE=4V; Tj=-40°C
Tj=25°C...150°C
IOUT=30A; VSENSE=4V;
Tj=-40°C...+150°C
VCC=6...16V; IOUT=0A;VSENSE=0V;
Tj=-40°C...+150°C
Max Analog Sense Output VCC=5.5V; IOUT=5A; RSENSE=10KΩ
Voltage
VCC>8V; IOUT=10A; RSENSE=10KΩ
Sense Voltage in
Overtemperature
VCC=13V; RSENSE=3.9KΩ
conditions
Analog Sense Output
Impedance in
VCC=13V; Tj>TTSD; All channels open
Overtemperature
Condition
Current sense delay
to 90% I SENSE (see note 2)
response
Min
Typ
Max
3300
4400
6000
-10
+10
4200
4900
6000
4400
4900
5750
-8
+8
4200
4900
5500
4400
4900
5250
Unit
%
%
-6
+6
%
0
10
µA
2
V
4
V
5.5
V
400
Ω
500
µs
Typ
175
Max
200
15
45
75
Unit
°C
°C
°C
A
75
A
PROTECTIONS
Symbol
TTSD
TR
Thyst
Ilim
Vdemag
VON
Parameter
Shut-down Temperature
Reset Temperature
Thermal Hysteresis
DC Short Circuit Current
Turn-off Output Clamp
Voltage
Output Voltage Drop
Limitation
Test Conditions
VCC=13V
Min
150
135
7
30
5V<VCC<36V
IOUT=2A; VIN=0V; L=6mH
IOUT=1A; Tj=-40°C....+150°C
VCC-41 VCC-48 VCC-55
V
50
mV
Note 2: current sense signal delay after positive input slope
Note: Sense pin doesn’t have to be left floating.
5/18
2
VND920P
Figure 1: IOUT/ISENSE versus IOUT
6500
IOUT/ISENSE
6000
max.Tj=-40°C
5500
max.Tj=25...150°C
5000
typical value
min.Tj=25...150°C
4500
min.Tj=-40°C
4000
3500
3000
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
IOUT (A)
Figure 2: Switching Characteristics (Resistive load RL=1.3Ω)
VOUT
90%
80%
dV OUT /dt(off)
dV OUT /dt(on)
tr
10%
tf
t
ISENSE
90%
INPUT
t
tDSENSE
td(on)
td(off)
t
6/18
32
VND920P
Switching time Waveforms
VOUT
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
tr
tf
10%
t
VIN
td(on)
td(off)
t
TRUTH TABLE (Per each channel)
CONDITIONS
Normal operation
Overtemperature
Undervoltage
Overvoltage
Short circuit to GND
Short circuit to VCC
Negative output voltage clamp
INPUT
L
OUTPUT
L
CURRENT SENSE
0
Nominal
H
L
H
L
H
L
L
L
VSENSEH
0
H
L
L
L
0
0
H
L
L
L
0
0
H
L
(Tj<TTSD) 0
H
L
L
H
(Tj>TTSD) VSENSEH
0
H
L
H
L
0
< Nominal
0
7/18
VND920P
ELECTRICAL TRANSIENT REQUIREMENTS
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
CLASS
C
E
8/18
I
II
TEST LEVELS
III
IV
-25 V
+25 V
-25 V
+25 V
-4 V
+26.5 V
-50 V
+50 V
-50 V
+50 V
-5 V
+46.5 V
-75 V
+75 V
-100 V
+75 V
-6 V
+66.5 V
-100 V
+100 V
-150 V
+100 V
-7 V
+86.5 V
I
C
C
C
C
C
C
TEST LEVELS RESULTS
II
III
C
C
C
C
C
C
C
C
C
C
E
E
Delays and
Impedance
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
IV
C
C
C
C
C
E
CONTENTS
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
VND920P
Figure 3: Waveforms
NORMAL OPERATION
INPUTn
LOAD CURRENTn
SENSEn
UNDERVOLTAGE
VCCn
VUSDhyst
VUSD
INPUTn
LOAD CURRENTn
SENSEn
OVERVOLTAGE
VOV
VCCn
VCC > VUSD
VOVhyst
INPUTn
LOAD CURRENTn
SENSEn
SHORT TO GROUND
INPUTn
LOAD CURRENTn
LOAD VOLTAGEn
SENSEn
SHORT TO VCC
INPUTn
LOAD VOLTAGEn
LOAD CURRENTn
SENSEn
<Nominal
<Nominal
OVERTEMPERATURE
Tj
TTSD
TR
INPUTn
LOAD CURRENTn
SENSEn
ISENSE=
VSENSEH
RSENSE
9/18
VND920P
APPLICATION SCHEMATIC
+5V
Rprot
INPUT1
VCC1
VCC2
Dld
Rprot
C. SENSE 1
Rprot
INPUT2
Rprot
C. SENSE 2
OUTPUT1
µC
OUTPUT2
GND2
GND1
RSENSE1,2
RGND
VGND
GND PROTECTION
REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / (IS(on)max).
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on how many devices are ON in the case of
several high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor
or several devices have to share the same resistor then
the ST suggests to utilize Solution 2 (see below).
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
DGND
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also
required to prevent that, during battery voltage transient,
the current exceeds the Absolute Maximum Rating.
Safest configuration for unused INPUT and STATUS pin
is to leave them unconnected.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating. The
same applies if the device will be subject to transients on
the VCC line that are greater than the ones shown in the
ISO T/R 7637/1 table.
µC I/Os PROTECTION:
If a ground protection network is used and negative
transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot )
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up limit
of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
10/18
VND920P
High Level Input Current
Off State Output Current
IL(off1) (uA)
Iih (uA)
9
5
8
4.5
7
4
Vin=3.25V
3.5
6
3
5
2.5
4
2
3
1.5
2
1
1
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
100
125
150
175
Tc (°C)
Input Clamp Voltage
Input High Level
Vih (V)
Vicl (V)
3.6
8
7.8
3.4
Iin=1mA
7.6
3.2
7.4
3
7.2
2.8
7
6.8
2.6
6.6
2.4
6.4
2.2
6.2
2
6
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
Tc (°C)
Tc (°C)
Input Low Level
Input Hysteresis Voltage
Vil (V)
Vhyst (V)
2.6
1.5
1.4
2.4
1.3
2.2
1.2
2
1.1
1.8
1
0.9
1.6
0.8
1.4
0.7
1.2
0.6
1
0.5
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
11/18
VND920P
ILIM Vs Tcase
Overvoltage Shutdown
Vov (V)
Ilim (A)
50
100
48
90
46
80
44
70
42
60
40
50
38
40
36
30
34
20
32
10
Vcc=13V
30
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
Tc (°C)
75
100
125
150
175
100
125
150
175
Tc (°C)
Turn-on Voltage Slope
Turn-off Voltage Slope
dVout/dt(on) (V/ms)
dVout/dt(off) (V/ms)
700
550
500
650
600
Vcc=13V
Rl=1.3Ohm
450
Vcc=13V
Rl=1.3Ohm
400
550
350
500
300
450
250
200
400
150
350
100
300
50
0
250
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
Tc (°C)
Tc (ºC)
On State Resistance Vs Tcase
On State Resistance Vs VCC
Ron (mOhm)
Ron (mOhm)
50
50
45
45
Iout=10A
Vcc=8V; 36V
40
40
35
35
30
30
25
25
20
20
15
15
10
10
5
5
Tc= 150ºC
Tc= 25ºC
Tc= - 40ºC
0
0
-50
-25
0
25
50
75
Tc (ºC)
12/18
100
125
150
175
5
10
15
20
25
Vcc (V)
30
35
40
VND920P
Maximum turn off current versus load inductance
ILMAX (A)
100
A
B
C
10
1
0.01
0.1
1
L(mH)
10
100
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
13/18
VND920P
SO-28 DOUBLE ISLAND THERMAL DATA
SO-28 Double island PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.5cm2, 3cm2, 6cm2).
Thermal calculation according to the PCB heatsink area
Chip 1
ON
OFF
ON
ON
Chip 2
OFF
ON
ON
ON
Tjchip1
RthA x Pdchip1 + Tamb
RthC x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
(RthA x Pdchip1) + RthC x Pdchip2 + Tamb
Tjchip2
Note
RthC x Pdchip1 + Tamb
RthA x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
Pdchip1=Pdchip2
(RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1≠Pdchip2
RthA = Thermal resistance Junction to Ambient with one chip ON
RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2
RthC = Mutual thermal resistance
Rthj-amb Vs PCB copper area in open box free air condition
RTHj_am b
(°C/W)
70
60
50
RthA
40
RthB
30
RthC
20
10
0
1
2
3
4
5
PCB Cu heatsink area (cm ^2)/island
6
7
14/18
VND920P
SO-28 Thermal Impedance Junction Ambient Single Pulse
Zth(°C/W)
100
0,5 cm ^2/is land
3 cm ^2/is land
6 cm ^2/is land
10
One channel ON
TwoOne
channels
ON
channel ON
on same chip
1
Tw o channels ON
0.1
0.01
0.0001
0.001
0.01
0.1
1
time(s)
Thermal fitting model of a two channels HSD in
SO-28
10
100
1000
Pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
δ = tp ⁄ T
Thermal Parameter
Tj_1
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
Pd1
Tj_2
C1
C2
R1
R2
Pd2
T_amb
15/18
Area/island (cm2)
R1= (°C/W)
R2= (°C/W)
R3= (°C/W)
R4= (°C/W)
R5= (°C/W)
R6= (°C/W)
C1= (W.s/°C)
C2= (W.s/°C)
C3= (W.s/°C)
C4= (W.s/°C)
C5= (W.s/°C)
C6= (W.s/°C)
0.5
0.02
0.1
2.2
11
15
30
0.0015
7.00E-03
1.50E-02
0.2
1.5
5
6
13
8
VND920P
SO-28 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
inch
MAX.
MIN.
TYP.
2.65
MAX.
0.104
a1
0.10
0.30
0.004
0.012
b
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
C
0.50
0.020
c1
45 (typ.)
D
17.7
E
10.00
e
18.1
0.697
10.65
0.393
1.27
e3
0.713
0.419
0.050
16.51
0.650
F
7.40
7.60
0.291
0.299
L
0.40
1.27
0.016
0.050
S
8 (max.)
16/18
VND920P
SO-28 TUBE SHIPMENT (no suffix)
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
B
28
700
532
3.5
13.8
0.6
All dimensions are in mm.
A
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
16.4
60
22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
All dimensions are in mm.
16
4
12
1.5
1.5
7.5
6.5
2
End
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
17/18
500mm min
VND920P
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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18/18