VNQ05XSP16 ® QUAD CHANNEL HIGH SIDE SOLID STATE RELAY TYPE VNQ05XSP16 RON(*) 110mΩ IOUT 5A (*) VCC 36 V (*) Per each channel OUTPUT CURRENT (CONTINUOUS): 5A CMOS COMPATIBLE INPUTS ■ MULTIPLEXED PROPORTIONAL LOAD CURRENT SENSE ■ UNDERVOLTAGE & OVERVOLTAGE SHUT- DOWN ■ OVERVOLTAGE CLAMP ■ THERMAL SHUT DOWN ■ CURRENT LIMITATION ■ VERY LOW STAND-BY POWER DISSIPATION ■ PROTECTION AGAINST: n LOSS OF GROUND & LOSS OF VCC ■ REVERSE BATTERY PROTECTION (**) DESCRIPTION The VNQ05XSP16 is a monolithic device designed in STMicroelectronics VIPower M0-3 ■ PowerSO-16TM ■ ORDER CODES PACKAGE TUBE T&R PowerSO-16™ VNQ05XSP16 VNQ05XSP1613TR Technology. It is intended for driving any type of multiple loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device has four independent channels and one multiplexed analog sense output which deliver a current proportional to the selected output current. SenseEnable pin allows to connect any number of VNQ05XSP16 on the same Current Sense line. Active current limitation combined with thermal shut-down and automatic restart protect the device against overload. Device automatically turns off in case of ground pin disconnection. ABSOLUTE MAXIMUM RATING Symbol VCC -VCC IOUT IR IIN Parameter Supply voltage (continuous) Reverse supply voltage (continuous) Output current (continuous), for each channel Reverse output current (continuous), for each channel Input current (IN1,IN2,IN3,IN4,SELA,SELB,SENSENABLE) VCSENSE Current sense maximum voltage IGND VESD Ptot EMAX Tj Tc TSTG Value 41 -0.3 Internally limited -5 +/- 10 -3 Unit V V A A mA V +15 -200 V mA - INPUT 4000 V - CURRENT SENSE 2000 V - OUTPUT 5000 V - VCC Power dissipation at Tcase=25°C Maximum Switching Energy 5000 78 V W 76 mJ Internally limited - 40 to 150 -55 to 150 °C °C °C Ground current at Tcase<25°C (continuous) Electrostatic Discharge (Human Body Model: R=1.5Ω; C=100pF) (L=1.72mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=7.5A) Junction operating temperature Case Operating Temperature Storage temperature (**) See application schematic at page 9 March 2003 1/17 VNQ05XSP16 BLOCK DIAGRAM VCC OVERVOLTAGE UNDERVOLTAGE INPUT 1 INPUT 2 DEMAG 1 DRIVER 1 LOGIC OUTPUT 1 ILIM 1 INPUT 3 VdsLIM 1 INPUT 4 OVERTEMP. 1 OVERTEMP. 2 Ot1 K CS1 IOUT1 OVERTEMP. 3 OVERTEMP. 4 Same structure for the channels2,3,4 SELECT A SELECT B OUTPUT 2 DIAG LOGIC OUTPUT 3 OUTPUT 4 SENSE ENABLE GND CURRENT SENSE 2/17 QUAD ANALOG Mux CS1 CS2 CS3 CS4 VNQ05XSP16 CURRENT AND VOLTAGE CONVENTIONS IS VCC VCC IIN1 VIN1 VIN2 IIN2 INPUT1 IIN3 INPUT2 ISELA VSENSE VSELA OUTPUT2 INPUT4 ISENSE VIN4 ISELB VSELB ISENSENABLE VOUT2 IOUT3 SENSE OUTPUT3 SELA IOUT4 SELB OUTPUT4 SENSENABLE VSENSENABLE VOUT1 IOUT2 INPUT3 IIN4 VIN3 IOUT1 OUTPUT1 VOUT3 VOUT4 GND IGND CONNECTION DIAGRAM (TOP VIEW) INPUT 1 INPUT 2 INPUT 3 INPUT 4 C.SENSE SENSENABLE SELA SELB 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 GROUND N.C. OUTPUT 1 OUTPUT 2 N.C. OUTPUT 3 OUTPUT 4 VCC 17 VCC 3/17 VNQ05XSP16 THERMAL DATA Symbol Rthj-case Rthj-amb Parameter Thermal resistance junction-case Thermal resistance junction-ambient Value 1.6 51.6 (*) (MAX) (MAX) Unit °C/W °C/W (*) When mounted on FR4 printed circuit board with 0.5 cm² of copper area (at least 35 µm thick) connected to all VCC pins ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C; unless otherwise specified) (Per each channel) POWER Symbol VCC VUSD VOV IOUT1,2,3,4=1A; Tj=25°C 110 Unit V V V mΩ On state resistance IOUT1,2,3,4=1A; Tj=150°C 220 mΩ Vclamp Clamp Voltage IOUT1,2,3,4=0.5A; VCC=6V ICC=20mA (See note 1) Off state; Inputs=n.c.; VCC=13V 330 55 80 mΩ V µA IS Supply current On state; VIN=5V; VCC=13V; IOUT=0A; 10 mA Off State Output Current Off State Output Current Off State Output Current Off State Output Current RSENSE=3.9kΩ VIN=VOUT=0V VIN=0V; VOUT=3.5V VIN=VOUT=0V; Vcc=13V; Tj=125°C VIN=VOUT=0V; Vcc=13V; Tj=25°C 50 0 5 3 µA µA µA µA Typ 40 40 See relative diagram See relative diagram Max Unit µs µs Typ 7.5 Max 10 Unit A 10 A 200 °C RON IL(off1) IL(off2) IL(off3) IL(off4) Parameter Operating supply voltage Under voltage shut down Overvoltage shut down Test Conditions Min 5.5 3 36 41 Typ 13 4 48 0 -75 Max 36 5.5 SWITCHING (VCC=13V) Symbol td(on) td(off) Parameter Turn-on delay time Turn-off delay time Test Conditions RL=2.6Ω channels 1,2,3,4 (see figure 2) RL=2.6Ω channels 1,2,3,4 (see figure 2) (dVOUT/ dt)on Turn-on voltage slope RL=2.6Ω channels 1,2,3,4 (see figure 2) (dVOUT/ dt)off Turn-off voltage slope RL=2.6Ω channels 1,2,3,4 (see figure 2) Min V/µs V/µs PROTECTIONS Symbol Ilim TTSD TR THYST Vdemag VON Parameter DC short circuit current Test Conditions VCC=13V 5.5V<VCC<36V Thermal shut down 150 temperature Thermal reset temperature Thermal hysteresis Turn-off output voltage clamp Output voltage drop limitation 1 175 135 7 IOUT=2A; L=6mH IOUT=0.1A Tj=-40°C...+150°C Note 1: Vclamp and VOV are correlated. Typical difference is 5V. 4/17 Min 5 °C 15 °C VCC-41 VCC-48 VCC-55 V 50 mV VNQ05XSP16 CURRENT SENSE (9V< VCC <16V) Symbol K1 dK1/K1 K2 dK2/K2 K3 dK3/K3 ISENSEO VSENSE1,2,3,4 Parameter IOUT/ISENSE Test Conditions IOUT=0.1A; VSENSE=0.5V Tj=-40...+150°C Current Sense Ratio IOUT=0.1A; VSENSE=0.5V; Drift Tj= -40°C...+150°C IOUT=1.0A, VSENSE=4V IOUT/ISENSE Tj=-40...+150°C Current Sense Ratio IOUT=1.0A; VSENSE=4V; Drift Tj=-40°C...+150°C IOUT/ISENSE IOUT=2.0A, VSENSE=4V Tj=-40...+150°C Current Sense Ratio IOUT=2.0A; VSENSE=4V; Drift Tj=-40°C...+150°C Analog Sense Leakage Current Max analog sense output voltage VCC=6...16V; IOUT=0A;VSENSE=0V; RVSENSEH tDSENSE Typ Max 650 950 1200 -10 800 +10 1000 -8 850 % 1200 +8 1000 Unit % 1150 -6 +6 % 0 10 µA Tj=-40°C...+150°C VCC=5.5V, IOUT1,2,3,4=1.0A RSENSE=10kΩ 2 V 4 V VCC>8V, IOUT1,2,3,4=2.0A RSENSE=10kΩ VSENSEH Min Analog sense output voltage in VCC=13V; RSENSE= 3.9kΩ overtemperature condition Analog sense output VCC=13V; Tj>TTSD; impedance in overtemperature All Channels Open condition VCC=13V; RSENSE=3.9kΩ Current sense delay (see note 2) 5.5 V 400 Ω 300 500 µs Typ Max Unit 1.25 V LOGIC CHARACTERISTICS (Inputs, Sela&b, Sensenable) Symbol VIL VIH VI(hyst) IIL IIN VICL Parameter Input low level voltage Input high level voltage Input hysteresis voltage Low level input current High level input current Input clamp voltage Test Conditions VIN=1.25V Min 3.25 V 0.5 V 1 µA VIN=3.25V IIN=1mA IIN=-1mA 6 6.8 -0.7 10 µA 8 V V Note 2: current sense signal delay after positive input slope. Note: Sense pin doesn’t have to be left floating. 5/17 2 VNQ05XSP16 TRUTH TABLE CONDITIONS INPUT OUTPUT SENSE L L H L H L 0 Nominal H L L L VSENSEH 0 H L L L 0 0 H L L L 0 0 H L (Tj<TTSD) 0 H L L H (Tj>TTSD) VSENSEH 0 H H < Nominal L L 0 Normal operation Overtemperature Undervoltage Overvoltage Short circuit to GND Short circuit to VCC Negative output voltage clamp 0 TRUTH TABLE SENSENABLE L H H H H SELB X L L H H SELA X L H L H SENSE High Impedance ISENSE=IOUT1/K ISENSE=IOUT2/K ISENSE=IOUT3/K ISENSE=IOUT4/K Figure 1: IOUT/ISENSE versus IOUT IOUT/ISENSE 1500 1400 1300 max. Tj=-40°C<<150°C 1200 1100 typical value 1000 900 800 min. Tj=-40°C<<150°C 700 600 500 0 1 2 3 4 5 IOUT (A) 6/17 1 6 7 8 9 10 VNQ05XSP16 ELECTRICAL TRANSIENT REQUIREMENTS ISO T/R 7637/1 Test Levels Test Levels Test Levels Test Levels Test Levels I II III IV Delays and Impedance -25V +25V -25V +25V -4V +26.5V -50V +50V -50V +50V -5V +46.5V -75V +75V -100V +75V -6V +66.5V -100V +100V -150V +100V -7V +86.5V 2ms, 10Ω 0.2ms, 10Ω 0.1µs, 50Ω 0.1µs, 50Ω 10ms, 0.01Ω 400ms, 2Ω Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Levels Result Test Levels Result Test Levels Result Test Levels Result I II III IV C C C C C C C C C C C E C C C C C E C C C C C E Test Pulse 1 2 3a 3b 4 5 Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. Figure 2: Switching Characteristics (Resistive load RL=1.3Ω) VOUT 90% 80% dVOUT/dt(off) dVOUT/dt(on) tr 10% tf t ISENSE 90% INPUT t tDSENSE td(on) td(off) t 7/17 1 VNQ05XSP16 Figure 3: Waveforms NORMAL OPERATION (for example: Channel1 is ON) INPUT1 LOAD CURRENT1 SENSE1 SENSEN UNDERVOLTAGE VCC VUSDhyst VUSD INPUT1 LOAD CURRENT1 SENSE1 SENSEN OVERVOLTAGE VOV VCC VCC < VOV VCC > VOV INPUT1 LOAD CURRENT1 SENSE1 SENSEN SHORT TO GROUND INPUT1 LOAD CURRENT1 LOAD VOLTAGE1 SENSE1 SENSEN SHORT TO VCC INPUT1 LOAD VOLTAGE1 LOAD CURRENT1 SENSE1 <Nominal <Nominal SENSEN OVERTEMPERATURE Tj TTSD TR INPUT1 LOAD CURRENT1 SENSE1 SENSEN 8/17 1 ISENSE= VSENSEH RSENSE VNQ05XSP16 APPLICATION SCHEMATIC +5V Rprot INPUT1 VCC Dld Rprot OUTPUT1 INPUT2 Rprot INPUT3 µC Rprot INPUT4 OUTPUT2 Rprot SELA Rprot OUTPUT3 SESB Rprot SENSENABLE OUTPUT4 A/D Rprot C. SENSE GND CFILTER CPAR RGND DGND RSENSE VGND Notes: Input1,2,3,4, SELA, SELB, SENSENABLE have the same structure. RSENSE x CPAR <10µs GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / (IS(on)max). 2) RGND ≥ (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device’s datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (≅600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. µC I/Os PROTECTION: If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended Rprot value is 10kΩ. 9/17 1 VNQ05XSP16 High Level Input Current Off State Output Current Iih (µA) IL(off) (µA) 5 5 4.5 4.5 Off state Vcc=36V Vin=Vout=0V 4 3.5 Vin=3.25V 4 3.5 3 3 2.5 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (ºC) Tc (ºC) Input High Level Input Clamp Voltage Vih (V) Vicl (V) 3.6 8 3.4 7.75 Iin=1mA 7.5 3.2 7.25 3 7 2.8 6.75 2.6 6.5 2.4 6.25 2.2 2 6 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 100 125 150 175 Tc (ºC) Tc (ºC) ILIM Vs Tcase Overvoltage Shutdown Ilim (A) Vov (V) 50 20 47.5 17.5 45 15 42.5 12.5 40 10 37.5 7.5 35 5 32.5 2.5 Vcc=13V 0 30 -50 -25 0 25 50 75 Tc (ºC) 10/17 1 100 125 150 175 -50 -25 0 25 50 75 Tc (ºC) VNQ05XSP16 Turn-on Voltage Slope Turn-off Voltage Slope dVout/dt(on) (V/ms) dVout/dt(off) (V/ms) 500 600 450 550 500 Vcc=13V Rl=2.6Ohm 400 Vcc=13V Rl=2.6Ohm 450 350 400 300 350 250 300 200 250 200 150 150 100 100 50 50 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (ºC) 50 75 100 125 150 175 Tc (ºC) On State Resistance Vs Tcase On State Resistance Vs VCC Ron (mOhm) Ron (mOhm) 250 200 225 175 Iout=1A Vcc=8V & 36V 200 Tc=150ºC 150 175 Iout=1A 125 150 100 125 100 Tc=25ºC 75 75 Tc=-40ºC 50 50 25 25 0 0 -50 -25 0 25 50 75 Tc (ºC) 100 125 150 175 5 10 15 20 25 30 35 40 Vcc (V) 11/17 1 VNQ05XSP16 Maximum turn off current versus load inductance ILMAX (A) 100 A 10 B C 1 0.01 0.1 1 10 L(mH) A = Single Pulse at TJstart=150ºC B= Repetitive pulse at TJstart=100ºC C= Repetitive Pulse at TJstart=125ºC Conditions: VCC=13.5V Values are generated with RL=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 12/17 1 VNQ05XSP16 PowerSO-16™ THERMAL DATA PowerSO-16™ PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 6cm2). Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (°C/W) 55 Tj-Tamb=50°C 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 13/17 1 VNQ05XSP16 Thermal Impedance Junction Ambient Single Pulse ZT H (°C/W) 1000 100 Footprint 6 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 T ime (s) Thermal fitting model of a quad HSD in PowerSO-16 Tj_1 C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 10 100 1000 Pulse calculation formula Z THδ = R TH ⋅ δ + ZTHtp ( 1 – δ ) where δ = tp ⁄ T Thermal Parameter Pd1 C13 Tj_2 R13 C14 R14 Pd2 Tj_3 R17 R18 C7 C8 C9 R7 R8 R9 C10 R10 Pd3 Tj_4 C15 R15 C16 R16 Pd4 T_amb 14/17 1 C11 R11 C12 R12 Area/island (cm2) R1 (°C/W) R2 (°C/W) R3 ( °C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) Footprint 0.18 0.8 0.7 0.8 13 37 0.0006 1.50E-03 1.75E-02 0.4 0.75 3 6 22 5 VNQ05XSP16 POWERSO-16TM MECHANICAL DATA DIM. A1 A2 A3 A4 a b c D D1 d E (1) E1 E2 E3 e e1 F G L R1 R2 T T1 T2 Package Weight MIN. 0 3.4 1.2 0.15 0.27 0.23 9.4 7.4 0 13.85 9.3 7.3 5.9 0.8 2° mm. TYP 0.05 3.5 1.3 0.2 0.2 0.35 0.27 9.5 7.5 0.05 14.1 9.4 7.4 6.1 0.8 5.6 0.5 1.2 1 MAX. 0.1 3.6 1.4 0.25 0.43 0.32 9.6 7.6 0.1 14.35 9.5 7.5 6.3 1.1 0.25 0.8 5° 6° (typ.) 10° (typ.) (typ.) 8° P013Q 15/17 VNQ05XSP16 PowerSO-16™ SUGGESTED PAD LAYOUT TUBE SHIPMENT (no suffix) 2 +/- 0.14 0.8 +/- 0.1 0.5 +/- 0.1 7.4 +/- 0.1 10 +/- 0.1 C A B All dimensions are in mm. Base Q.ty Bulk Q.ty Tube length (± 0.5) 50 1000 532 A B C (± 0.1) 4.9 17.2 0.8 10.5 +/- 0.1 TAPE AND REEL SHIPMENT (suffix “13TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 24 4 24 1.5 1.5 11.5 6.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 16/17 1 VNQ05XSP16 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2003 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 17/17 1