L6996 DINAMICALLY PROGRAMMABLE SYNCHRONOUS STEP DOWN CONTROLLER FOR MOBILE CPUs ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5 BIT DAC WITH AVAILABLE EXTERNAL OUTPUT VOLTAGE. 0.6 TO 1.750V, DYNAMICALLY ADJUSTABLE OUTPUT VOLTAGE RANGE. ±1% OUTPUT ACCURACY OVER LINE AND LOAD. ACTIVE DROOP. CONSTANT ON TIME TOPOLOGY ALLOWS LOW DUTY CYCLE AND FAST LOAD TRANSIENT. 90% EFFICIENCY FROM 12V TO 1.35V/8A. 1.750V TO 28V BATTERY INPUT RANGE. OPERATING FREQUENCY UP TO 1MHZ. INTEGRATED HIGH CURRENT DRIVERS. LATCHED OVP AND UVP PROTECTIONS. OCP PROTECTION. 350µA TYP. QUIESCENT CURRENT. 7µA TYP. SHUTDOWN SUPPLY CURRENT. PGOOD AND OVP SIGNALS. ZERO-CURRENT DETECTION AND PULSEFREQUENCY MODE. TSSOP24 ORDERING NUMBERS: L6996D (TSSOP24) L6996DTR (Tape & Reel) DESCRIPTION The device is dc-dc controller specifically designed to provide extremely high efficiency conversion for mobile advanced microprocessors. The "constant on-time" topology assures fast load transient response. The embedded "voltage feedforward" provides nearly constant switching frequency operation. A precise 5-bit DAC allows select output voltage from 0.6V to 1V with 25mV steps and from 1V to 1.75V with 50mV steps. L6996 is capable of supporting CPUs VID combination changing during normal operation. The active droop allows adjust both the output loadline slope and the zero-load output voltage. APPLICATIONS ■ ADVANCED MOBILE CPUs SUPPLY WITH DYNAMIC TRANSITIONS. ■ NOTEBOOK/LAPTOP, CONCEPT PC CPUs SUPPLY. ■ DC/DC FROM BATTERY SUPPLY EQUIPMENTS. APPLICATION DIAGRAM 5V OSC VDR VCC 25V 5V BOOT HGATE HS L RSENSE VOUT PHASE PGOOD OVP ILIM 1.25V LGATE L6996 LS DS PGND GND CS+ CS- SS CSS SHDN VID4:0 July 2002 VFBVFB+ VPROG CVPROG 1/26 L6996 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC VCC to GND -0.3 to 6 V VDR VDR to GND -0.3 to 6 V HGATE and BOOT, to PHASE -0.3 to 6 V HGATE and BOOT, to PGND -0.3 to 36 V PHASE -0.3 to 30 V LGATE to PGND -0.3 to VDR+0.3 V ILIM, VFB+, VFB-, CS-, CS+, SHDN, VID0-4, PGOOD, OVP, VPROG to GND -0.3 to VCC+0.3 V 1 W 0 to 125 °C -55 to 125 °C Value Unit 125 °C/ W VPHASE Ptot Tj Tstg Maximum Power dissipation at Tamb = 25°C Junction operating temperature range Storage temperature range THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient PIN CONNECTION VID2 1 24 VID3 VID1 2 23 VID4 VID0 3 22 BOOT CS- 4 21 HGATE CS+ 5 20 PHASE VCC 6 19 VDR GND 7 18 LGATE VPROG 8 17 PGND VFB+ 9 16 PGOOD VFB- 10 15 OVP OSC 11 14 SHDN SS 12 13 ILIM TSSOP24 2/26 L6996 PIN FUNCTIONS N Name Description 1,2,3, 23,24 VID4-0 Voltage Identification inputs. VID0 is the LSB and VID4 is the MSB for the DAC (see VID table) 4 CS- This pin is used for both current sensing and to detect overvoltage and undervoltage conditions. 5 CS+ Current sense pin. Overcurrent condition is detected by sensing CS+ to CS- voltage. 6 VCC Supply voltage for analogy blocks. Connect it to 5V bus. 7 GND Signal ground 8 VPROG DAC output voltage. This pin provides the voltage programmed by the DAC. Connect a 10nF capacitor between this pin and GND. 9 VFB+ PWM comparator reference input. Connect this pin to VPROG. An additional external voltage divider between output and VPROG may be used to realize the active droop function. 10 VFB- PWM comparator feedback input, to be connected to the regulated output. By inserting a resistor between this pin and the regulated output, a positive offset can be added to the output voltage. 11 OSC Connect this pin to the battery through a voltage divider in order to provide the voltage feedforward feature. 12 SS 13 ILIM 14 SHDN 15 OVP 16 PGOOD 17 PGND Power Ground. This pin has to be connected close to the low side MOSFET source in order to minimize switching noise. 18 LGATE Lower MOSFET gate driver output. 19 VDR 20 PHASE This pin provides the return path of the high side driver. 21 HGATE High side MOSFET driver output. 22 BOOT Bootstrap capacitor pin. The high side driver is supplied through this pin. Soft start pin. 5µA constant current charges an external capacitor whose value sets the softstart time. An external resistor connected between this pin and GND sets the current limit threshold. ShutDown input. When connected to GND the device stops working. When high, it enables the IC operation. Open drain output. The pull-down transistor is off either in OV condition or during a VID transition. Open drain output. The pull-down transistor is on during soft-start, dynamic transitions and when an output voltage fault occurs. Voltage supply for the low side internal driver. 3/26 L6996 ELECTRICAL CHARACTERISTICS (VCC = VDR = 5V; Tamb = 0°C to 70°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 1 28 V 4.5 5.5 V 4.1 4.3 V SUPPLY SECTION Vin Input voltage range Vout=1V Fsw=110Khz Iout=1A Vcc, VDR Vccoff Turn-off voltage VHYST UVLO Hysteresys 100 mV Iqcc (VDR) Quiescent current driver VFB- > VFB+ 60 90 20 µA Iqcc (Vcc) Quiescent current VFB- > VFB+ 600 µA SHUTDOWN SECTION SHDN SHDN Threshold ISH (VDR) Driver quiescent current in shutdown. ISH (Vcc) Shut down current 1.2 V SHDN to GND 0.6 5 µA SHDN to GND 15 µA 6 µA SOFT START SECTION ISS SS charge current 4 Soft-start active range 0.9 V ON TIME Ton On time duration Vprog=CS- =1.15 Osc=250mV 720 800 880 ns Vprog=CS-=1.15 Osc=500mV 355 420 485 ns Vprog=CS-=1.15 Osc=1V 210 250 290 ns Vprog=CS-=1.15 Osc=2V 120 150 180 ns 580 ns +1 % +2 mV 6 µA OFF TIME Minimum Off Time KOSC/TOFFMIN OSC=250mV VPROG=CS-=1.15V Voltage Accuracy VID0-4 see table 1 -1 Input voltage offset V PROG=1.6V=VFB- -2 Input bias current (VP) VVFB- =1.6V 4 0.28 DAC Vprog PWM COMPARATOR IVFB- 5 CURRENT LIMIT AND ZERO CURRENT COMPARATOR ILIM ILIM input bias current CS-=VPROG=1.6V ILIM to GND = 120KΩ KC Positive and negative Current Limit factor. RILIM = 120 KΩ PHASEGND Zero Crossing Comparator offset µA 4.95 0.18 0.3 -2 0.24 µA 2 mV GATE DRIVERS High side rise time VDR=5V; C=7nF HGATE - PHASE from 2 to 4.5V 50 70 ns 50 70 ns Low side rise time 50 70 ns Low side fall time 50 70 ns 120 123 % High side fall time PROTECTIONS OVP 4/26 Over voltage trip CS- rising 117 L6996 ELECTRICAL CHARACTERISTICS (continued) (VCC = VDR = 5V; Tamb = 0°C to 70°C unless otherwise specified) Symbol UVP Parameter Test Condition Min. Typ. Max. Unit Under voltage trip CS- falling 66 69 72 % PGOOD Upper threshold (CS-/VPROG) CS- rising; PGOOD active 109 112 115 % PGOOD Lower threshold (CS-/VPROG) CS- falling; PGOOD active 84 87 90 % ISOURCE=2mA 40 60 100 Ω Ron PGOOD Table 1. DAC Output Voltage VID4 VID3 VID2 VID1 VID0 Output Voltage (V) 1 1 1 1 1 0.600 1 1 1 1 0 0.625 1 1 1 0 1 0.650 1 1 1 0 0 0.675 1 1 0 1 1 0.700 1 1 0 1 0 0.725 1 1 0 0 1 0.750 1 1 0 0 0 0.775 1 0 1 1 1 0.800 1 0 1 1 0 0.825 1 0 1 0 1 0.850 1 0 1 0 0 0.875 1 0 0 1 1 0.900 1 0 0 1 0 0.925 1 0 0 0 1 0.950 1 0 0 0 0 0.975 0 1 1 1 1 1.000 0 1 1 1 0 1.050 0 1 1 0 1 1.100 0 1 1 0 0 1.150 0 1 0 1 1 1.200 0 1 0 1 0 1.250 0 1 0 0 1 1.300 0 1 0 0 0 1.350 0 0 1 1 1 1.400 0 0 1 1 0 1.450 0 0 1 0 1 1.500 0 0 1 0 0 1.550 0 0 0 1 1 1.600 0 0 0 1 0 1.650 0 0 0 0 1 1.700 0 0 0 0 0 1.750 5/26 V IN 5 uA 5 uA 0.05 5 bit DAC pwm comparator - + + - - + positive current limit comparator Reference chain VID4:0 DAC configuration VPROG 1.416 OSC FB- FB+ CS- CS+ ILIM SS 1.236V bandgap HS control VID4:0 LS control R one-shot Ton Ton min one-shot Toff min delay S 1.12 VPROG - 0.6 VPROG CS- - + - + dynamic transition detection PHASE 80 us one-shot S R VCC Q GND zero-cross comparator - + dynamic transition mode 0.925 VPROG CS- CS- 1.075 VPROG pgood comparators + - undervoltage comparator CS- + overvoltage comparator Ton= Kosc V(CS-)/V(OSC) dynamic transition control power management soft-start control IC enable OVP OSC PGOOD CS- dynamic transition mode R S CS+ - CS+ + Q V(PHASE)<0.2V comp V(LGATE)<0.5V comp LS and HS anti-cross-conduction comparators one-shot Ton Q OSC LS driver HS driver 0.05 ILIM negative current limit comparator Ton= Kosc V(CS-)/V(OSC) S R level shifter VCC 6/26 CS- SHDN PGND LGATE VDR PHASE HGATE BOOT 5V V IN V OUT L6996 Figure 1. Functional & Block Diagram L6996 TYPICAL OPERATING CHARACTERISTICS The test conditions refer to the component list the table 5. V IN = 20V V OUT = 1.8V FSW = 270kHz Tamb = 25°C unless otherwise noted. Figure 2. Dynamic Output Voltage Transition 1.55V -> 1.35V Figure 5. Startup with Zero Load CH1 -> VOUT CH2 -> SS CH3 -> IL CH1 -> VPHASE CH2 -> VOUT CH4 -> IL Figure 6. Startup with 10A Figure 3. Dynamic Output Voltage Transition 1.35V -> 1.55V CH1 -> VOUT CH2 -> SS CH3 -> IL CH1 -> VPHASE CH2 -> VOUT CH4 -> IL Figure 4. Load Transient 0-15A CH1 -> VOUT CH2 -> VOUT CH4 -> IL 7/26 L6996 Figure 7. Test Condition: Vin = 20V, V5v=5V, Fsw = 300kHz, Tamb = +25°C Efficency [%] 0.88 Vout=1.7 0.86 0.84 Vout=1.35 0.82 0.8 Vout=1.25 0.78 0.76 0.10 1.00 Current [A] 10.00 100.00 Figure 8. Test Condition: Vout = 1.75V, Fsw = 300kHz, V5v = 5V, Tamb = +25°C Efficency [%] 0.92 0.91 0.9 0.89 0.88 0.87 0.86 0.85 0.84 0.83 0.82 0.81 Vin=7 Vin=12 Vin=20 0.1 1.0 10.0 100.0 Current [A] Figure 9. Test Condition: Vout = 1.75V, V5v = 5V, Tamb = +25°C Frequency [KHz] 410 390 Vin=7 370 350 Vin=12 330 310 Vin=20 290 270 250 4 5 6 7 8 9 10 11 Current [A] 8/26 12 13 14 15 L6996 Figure 10. Typical Application with Active Voltage Droop 5V RVIN2 CVIN1 VCC CV52 VDR OSC BOOT D BOOT C HGATE RPU2 V IN CVIN2 RVIN1 RV5 CV51 BOOT HS L RPU1 RSENSE VOUT PHASE PGOOD OVP RIL1 LS LGATE L6996 CPU DS COUT COUT1 PGND ILIM GND RIL2 CS+ CS- MIL SS CVP3 RVP1 VFBVFB+ CSS CVP1 RVP3 RVP2 VPROG SHDN CVPROG VID4:0 Figure 11. Typical Application without Active Voltage Droop 5V CVIN1 VCC BOOT HGATE RPU2 V IN OSC VDR CV52 RVIN2 CVIN2 RVIN1 RV5 CV51 C D BOOT BOOT HS L RPU1 RSENSE VOUT PHASE PGOOD OVP RIL1 ILIM LGATE L6996 LS CPU DS COUT COUT1 PGND GND RIL2 CS+ MIL CSSS CSS SHDN VID4:0 VFBVFB+ VPROG CVPROG 9/26 L6996 1 DEVICE DESCRIPTION 1.1 Constant On Time PWM Topology Figure 12. Loop block schematic diagram Vin R1 One-shot generator OSC R2 FFSR R Q CS- HS Rsense HGATE S Vout Q LS DS LGATE VID0-4 DAC Vprog VFB+ VFB- + -PWM comparator This device implements a Constant On Time control, where the Ton is the on time duration forced by a one-shot circuit. The controller calculates the one-shot time directly proportional to the V CS- pin voltage and inversely to the OSC pin voltage as in Eq 1: Eq 1 V CST O N = K O SC --------------- + τ V OS C where KOSC=180ns and τ is the internal propagation delay time (Typ. 40ns). The system imposes in steady state a minimum on time corresponding to V OSC = 2V. In fact if the VOSC voltage increases above 2V the corresponding Ton will not decrease. Connecting OSC pin to a voltage partition from VIN to GND, it allows steadystate switching frequency FSW independent of V IN. It results: Eq 2 V OUT 1 F SW = --------------- ⋅ ----------- → α O SC = F SW ⋅ K O SC V IN T O N where Eq 3 R2 V OS C α O SC = --------------- = -------------------V IN R2 + R 1 The above equations allow setting the frequency divider ratio aOSC once output voltage has been set; note that such equations hold only if VOSC<2.A minimum off-time constrain of about 500nS is introduced in order to assure the boot capacitor charge and to limit switching frequency after a load transient as well as to mask PWM comparator output against switching noise and spikes. The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three 10/26 L6996 conditions are met contemporarily: the PWM comparator output is low (i.e. the output voltage is below the reference voltage), the minimum off time is passed and the current limit comparator is not triggered (i.e. the inductor current is under the current limit programmed value). The voltage on the OSC pin must range between 50mV and 2V to ensure the system linearity. 1.2 Closing the loop The loop is closed connecting the output voltage to the FB- pin. The FB- pin is linked internally to the comparator negative pin and the positive pin is connected to the programmed voltage as in Figure 12. When the FB- goes lower than FB+, the PWM comparator output goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise spike. After the on-time (calculated as described in the previous section) the system resets the flip-flop and then turns off the high side MOSFET and turns on the low side MOSFET. Internally the device has more complex logic than a flip-flop to manage the transition in correct way. For more details refers to the schematic Fig. 1. Because the system implements a valley loop control, the average output voltage is different from the programmed one as shown in figure 13. Figure 13. Valley Regulation Vout DC Error Offset <Vout> Vref Time Figure 14. Voltage positioning network To inductor PWM COMPARATOR + L6996 Rsense R4 To Vout R1 VFBVFB+ R2 R3 Vprog The L6996 performs an externally adjustable active droop, achieving a 4m V/A load line slope using a 1.5mΩ sense resistor without use an external amplifier. Focusing the attention on the control part of the system (Figure 14), it can be considered that the inductor current can revert (the PFM function is deal towards) and the current 11/26 L6996 has an average value equal to Io. The intention is to find the output average value called Vo. It is important to remember that the loop is closed a valley of the ripple, in this conditions the inputs of PWM comparator must be equal, so the VFB+ =VFB-. Suppose R4=0 and R3=open. Considering this and watching the figure 14 it can be written two equations at the VFB+ and VFB- node: Eq 4 Rsense · Io = Vc Eq 5 ( V ov alle y – V prog ) ⋅ R1 ------------------------------------------------------------ = Vc R1 + R2 Imposing Eq4=Eq5 it can be found the VOVALLEY value: Eq 6 Vovalley = Vprog + Rs · (1 + R1/R2) · Io Form Eq6 it can be noted the active drop effect due to R1, R2 resistors; it can be also noted the output average value is different from the VPROG value, the error is due to the valley control, and it is equal to half of the ESR voltage ripple. To reduce the error of the average output voltage we can change the VPROG value using resistors. In fact considering the R3 resistor we can make a Thevenin equivalent: Eq 7 Vprogeq = Vprog · R3/(R3 + R2) Eq 8 Req = R3//R2 How it can be seen the VPROGEQ is less the VPROG and so we can reduce the average output error. Remember that the R1, R2 and RSENSE are selected in base at the Voltage Positioning needs. The R4 resistor can be used to set also a positive offset at zero load. Considering the PWM comparator inputs: Eq 9 Vo = VFB+ + R4 · 5µA Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hysteretic system the frequency can change with some parameters (input voltage, output current). In L6996 is implemented the voltage feed-forward circuit that allows constant switching frequency during steady-sate operation with the input voltage variation. There are many factors affecting switching frequency accuracy in steady-state operation. Some of these are internal as dead times, which depend on high side MOSFET driver. Others related to the external components as high side MOSFET gate charge and gate resistance, voltage drops on supply and ground rails, low side and high side RDS ON and inductor parasitic resistance. During a positive load transient, (the output current increases), the converter switches at its maximum frequency (the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output current decreases), the device stops to switch (high side MOSFET remains off). 1.3 Transition from PWM to PFM To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM mode essentially for the off section; the on section is the same. In PFM after a turn-on cycle the system turnson the low side MOSFET, until the current reaches the zero A value, when the zero-crossing comparator turns off the low side MOSFET. In this way the energy stored in the output capacitor will not flow to ground, through the low side MOSFET, but it will flow to the load. In PWM mode, after a turn on cycle, the system keeps the low side MOSFET on until the next turn-on cycle, so the energy stored in the output capacitor will flow through the low side MOSFET to ground. The PFM mode is naturally implemented in hysteretic controller, in fact in PFM mode the system reads the output voltage with a comparator and then turns on the high side MOSFET when the output voltage goes down a reference value. The device works in discontinuous mode at light load and in 12/26 L6996 continuous mode at high load. The transition from PFM to PWM occurs when load current is around half the inductor current ripple. This threshold value depends on VIN, L, and VOUT. Note that the higher the inductor value is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the transient response is. In PFM mode the frequency changes, with the output current changing, more than in PWM mode; in fact if the output current increase, the output voltage decreases more quickly; so the successive turn-on arrives before, increasing the switching frequency. The PFM waveforms may appear more noisy and asynchronous than normal operation, but this is normal behaviour mainly due to the very low load. The NOSKIP feature cannot be disabled. 1.4 Softstart If the supply voltages are already applied, the SHDN pin gives the start-up. The system starts with the high side MOSFET off and the low side MOSFET on. After the SHDN pin is turned on the SS pin voltage begins to increase and the system starts to switch. The softstart is realized by gradually increasing the current limit threshold to avoid output overvoltage. The active soft start range (where the output current limit increase linearly) starts from 0.6V to 1.5V. In this range an internal current source (5µA typ) charges the capacitor on the SS pin. The reference current (for the current limit comparator) forced through ILIM pin is proportional to SS pin voltage and it saturates at 5µA (typ.) when SS voltage is close to 1.5V; so the maximum current limit is active. Output protections like undervoltage is disabled until SS pin voltage reaches 1.5V, instead the overvoltage is always present. Once the SS pin voltage reaches the 1.5V value, the voltage on SS pin doesn't impact the system operation anymore. If the SHDN pin is turned on before the supplies, the correct start-up sequence is the following: first turn-on the power section and after the logic section (VCC pin). Figure 15. Soft-start diagram Vss 4.1V 1.5V Soft-start active range 0.6V Ilim current Time 5µA Maximum current limit Time 1.5 Current limit The current limit comparator senses inductor current through the sense resistor when the low side MOSFET is on and compares this value with the ILIM pin voltage. While the current is above the prefixed value, the control inhibits the one-shot start. To properly set the current limit threshold, it should be noted that this is a valley current limit. Average current depends on the inductor value, VIN e VOUT. Eq 10 IOUTCL = IMAX_VALLEY + ∆IL / 2 13/26 L6996 To set the current threshold, choose R ILIM according to the following equation: Eq 11 R ILIM I M AX_VAL LEY = ---------------------- ⋅ K C R SENS E Where KC is the current limit factor (0.25µA typ.). A negative current limit is also introduced during dynamic transitions, when zero-cross comparator is disabled and at the inductor current is allowed to reverse. The negative current limit is useful when performing a negative transition (that is, output voltage is reduced) to avoid too high discharging current. Both positive and negative current limit have the same threshold; but the negative current limit can be set using the OVP signal plus a transistor, that changes during the dynamic transition, as in Fig. 16 (Q5, R11). The system accuracy is function of the exactness of the resistance connected to ILIM pin and RSENSE resistor. Moreover the voltage on ILIM pin must range between 10mV and 2V to ensure the system linearity. 1.6 Protection and fault Sensing CS- pin voltage performs the output protection. The nature of the fault (that is, latched OV or latched UV) is given by the PGOOD and OVP pins. If the output voltage is within the 90% 110% range, PGOOD is high. If an overvoltage or an undervoltage occurs, the device is latched. low side MOSFET is turned ON and high side MOSFET off. PGOOD goes low. OVP goes high in case of overvoltage, allowing the fault nature to be detected. To recuperate the functionality either the device must be shut down, thought the SHDN pin, or the supply has to be removed. These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV fault). 1.7 Drivers The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching transition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the voltage on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage reaches 500mV. This is important since the driver can work properly with a large range of external power MOSFETS. The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the root square of the MOSFET gate charge and the switching frequency. So the power dissipation of the device is function of the external power MOSFET gate charge and switching frequency. Eq 12 Pdriver = VCC · QgTOT · FSW The maximum gate charge values for the low side and high side are given from: Eq 13 f SW0 Q M AXHS = ------------- ⋅ 75 nC f SW Eq 14 f SW 0 Q M AXLS = ------------- ⋅ 125nC f SW Where fSW0 = 500kHz. The equations above are valid for TJ = 150°C. If the system temperature is lower the QG can be higher. For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation; 14/26 L6996 in this case the maximum value is QMAXLS = 125nC. The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect. 1.8 Digital to analog converter The built-in digital to analog converter (DAC) allows the adjustment of the output voltage in correspondence to the Table1 in pag 4: from 0.6V to 1V with 25mV steps, and from 1V to 1.75V with 50mV steps. The DAC can receive the digital input from the CPU. The programmed voltage is available on VPROG pin, which is capable of sourcing or sinking up to 250µA. The internal reference accuracy is ±1%. 1.9 Dynamically changing DAC code L6996 detects as a transition any change in VID code which duration is larger than 200ns. Then, a timer forces the chip in a 'transition state' for about 100µs. In such a state, output protections are disabled and OVP pin goes high. Current limit threshold can be reduced during the transition state duration by using an external mos shorting part of the RILIM resistor. The MOSFET gate is driven by OVP. Reducing current limit threshold prevents from output voltage overshoot/undershoot once the new-programmed voltage has been reached (see waveforms reported below), especially when the droop is not implemented. Note that the reduced threshold must be however high enough to allow the output capacitor to charge/discharge within the transition time. During the transition state duration, zero-cross comparator is disabled and inductor current is allowed to reverse. A negative current limit is introduced. During OFF time, if inductor current is negative and reaches the threshold, low side MOSFET is forced OFF, and remain OFF, allowing negative current to flow across high side body diode, for at least T ON. After then, the low side or high side turns ON again, depending on PWM comparator output. This allows switching frequency to be close to steady state frequency also when the device works in negative current limit protection. Dynamically changing the VID code is useful for portable computers, where the CPU is supply at a higher voltage when the AC-DC adapter is plugged-in, to increase speed. A lower voltage is instead provided when only the battery powers the CPU, to save energy. The dynamic transition is usually made at light load condition, to allow the full current to be available for charging/discharging the output capacitor: Iout ~ 300mA ∆Voutmax ~250mV The current limit threshold should be set high enough to charge/discharge the output capacitor within the transition state duration (see below). If the output voltage changing is higher than 250mV the system can detect an overvoltage or undervoltage that can shut down the device. 15/26 L6996 2 APPLICATION INFORMATION 2.1 Demo board description The demoboard shows the device operation in general purpose applications. The evaluation board needs two different supplies; one for the IC section (5V), and another for the conversion section (up to 28V). Output current in excess of 20A can be reached dependently on the MOSFET type. The SW1 is used to start the device (when the supplies are already present) and to select the VID code (i.e. the output voltage). Figure 16. Schematic Diagram +5V C9 C1 R8 GND VIN R16 C12..C17 VCC VDR D1 C4 OSC GND C7 BOOT C5 +5V +5V R7 R15 VOUTSENSE Q1,2 HGATE L1 R9 R14 PHASE PGOOD VOUT R17 PGOOD OVP OVP R10 R2..R6 GND GNDSENSE CS+ CS- C11 +5V R13 VFBVFB+ C10 R23 R1 Q6 VID4:0 +5V +5V +5V +5V U3 U9 +5V R19 DPSLP Q8 VPR U2 R24 Q7 U1 SHDN +5V C8 R21 R20 VPROG C6 +5V U8 U4 +5V +5V U6 U5 GMUXSEL +5V U7 +5V R18 DPSLVR 16/26 R22 R12 SHDN VID4:0 C18..C23 GND SS +5V Rout D2 PGND ILIM R11 Q5 Q3,4,5 LGATE L6996 +5V C2 +5V C3 L6996 2.2 Demoboard Layout Figure 17. PCB Board Layout - Layer one (Top component side) Figure 20. PCB Board Layout - Layer four (Bottom component side) Figure 18. PCB Board Layout - Layer two (Internal Ground plane) Figure 21. PCB Board Layout (Component position top view) Figure 19. PCB Board Layout - Layer three (Internal signal plane) Figure 22. PCB Board Layout (Component position bottom view) 17/26 L6996 Table 2. PCB Layout guidelines Goal Suggestion Low radiation and low magnetic coupling with the adjacent circuitry 1) Small switching current loop areas. (For example Placing CIN, high side and Low Side MOSFET, Schottky diode, as close as possible each to others). 2) Controller placed as close as possible to the Power MOSFET. 3) Group the gate drive component (Boot cap and diode together near the IC. Don’t penalty the efficiency Keep the power traces and load connections short and wide. Ensure high accuracy in the current sense system Cs+, CS- traces must be made by Kelvin connection. Also the traces should be separated from the power plane by a ground plane, run parallel. Reduce the noise effects on IC 1) Put the feedback component (like the VP network as close as possible to the IC) 2) The feedback connection (like the FB trace, or CS+/CStraces….) should be route as far as possible from the switching current loops. 3) Make the controller ground connection like in the figure 16. 3 DESIGN EXAMPLES 3.1 VIN = 20V IOUT = 23A In this design it is considered a low profile demoboard, so a great attention is given to the components height. 3.2 Input capacitor A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC component of this current is quite high and dissipates a considerable amount of power on the ESR of the capacitor: Eq 15 2 Vin ⋅ ( Vin – Vout ) P CIN = ESR CIN ⋅ Iou t ⋅ ----------------------------------------------2 Vin The IRMS current is given by: Eq 16 Icin rm s = δ 2 2 Iout δ ( 1 – δ ) + ------ ( ∆I L ) 12 Neglecting the last term, the equation reduces to: Eq 17 Icin rm s = Io ut δ ( 1 – δ ) PCIN, and also ICINRMS, has a maximum equal to IOUT/2 (@ VIN = 2 × VOUT, that is, 50% duty cycle). The input, therefore, should be selected for a RMS ripple current rating as high as half the respective maximum output current. Electrolytic capacitors are the most used because are the cheapest ones and are available with a wide range of RMS current ratings. The only drawback is that, considering a requested ripple current rating, they are physically larger than other capacitors. Very good tantalum capacitors are coming available, with very low ESR and small size. The only problem is that they occasionally can burn out if subjected to very high current during the charge. So, it is better avoid this type of capacitors for the input filter of the device. In fact, they can be subjected to high surge current when connected to the power supply. If available for the requested value and voltage rating, the ceramic capacitors have usually a higher RMS current rating for a given physical size (due to the very low ESR). From the equation 17 it is found: 18/26 L6996 Icinrms = 6.4A Considering 10uF capacitors ceramic, that have ICINRMS =1.5A, 6 pzs. are needed. 3.3 Inductor selection In order to determine the inductor value is necessary considering the maximum output current to decide the inductor current saturation. Once the inductor current saturation is found automatically it is found the inductor value also. The inductor value is important also to determine the duration of the dynamic output voltage transition. In our design it is considered a very low profile inductor. L = 0.6µA The saturation current for this choke is 25A 3.4 Output capacitors The output capacitor is chosen by the output voltage static and dynamic accuracy. The static accuracy is related to the output voltage ripple value, while the dynamic accuracy is related to the output current load step. If the static precision is around +/- 4% for the 1.25V output voltage, the output accuracy is ±50mV. To determine the ESR value from the output precision is necessary before calculate the ripple current: Eq 18 Vin – Vo Vo ∆I = ----------------------- ⋅ --------- ⋅ T sw L Vin Considering a switching frequency around 270kHz from the equation above the ripple current is around 7A. So the maximum ESR should be: Eq 19 ∆V rip ple 50mV ESR = --------------------- = ---------------- = 14mΩ ∆I 3.5 ----2 The dynamic specifications are sometime more relaxed than the static requirements so the ESR value around 7mΩ should be enough. Sometimes can be considered the output capacitor effect also: 2 Eq 20 1 Io ut ⋅ L ∆Vo ut = ---------------------- ⋅ -------------2 ⋅ Vo ut C out From the above equation can be calculated the minimum output capacitance value. Considering ∆VOUT = 100mV, COUT > 1600µF should be used. Five capacitor of 330µF from PANASONIC correspond to the request. To allow the device control loop to properly work, output capacitor ESR zero must be at least ten times smaller than switching frequency. Low ESR tantalum capacitors, which ESR zero is close to 10 kHz, are suitable for output filtering. Output capacitor value COUT and its series resistance, should be large enough and small enough, respectively, to keep output voltage within the accuracy range during a load transient, and to give the device a minimum signal to noise ratio. The current ripple flows through the output capacitor, so the output capacitors should be calculated also to sustain this ripple: the RMS current value is given from Eq21. Eq 21 1 Icout rms = ----------- ∆I L 2 3 But this is usually a negligible constrain when choosing output capacitor. 19/26 L6996 3.5 Power MOSFET and Schottky Diodes Since a 5V bus powers the gate drivers of the device, the use of logic-level MOSFET is highly recommended, especially for high current applications. The breakdown voltage VBRDSS must be greater than VINMAX with a certain margin, so the selection will address 20V or 30V devices (depends on applications). The RDSON can be selected once the allowable power dissipation has been established. By selecting identical Power MOSFET as the main switch and the synchronous rectifier, the total power they dissipate does not depend on the duty cycle. Thus, if PON is this power loss (few percent of the rated output power), the required RDSON (@ 25 °C) can be derived from: PO N RD S O N = -----------------------------------------------2 Iou t ⋅ ( 1 + α ⋅ ∆T ) Eq 22 α is the temperature coefficient of RDS(ON) (typically, a = 5*10 -3 °C-1 for these low-voltage classes) and T the admitted temperature rise. It is worth noticing, however, that generally the lower RDS ON, the higher is the gate charge QG, which leads to a higher gate drive consumption. In fact, each switching cycle, a charge Q G moves from the input source to ground, resulting in an equivalent drive current: Eq 23 Iq = Q g ⋅ F SW The Schottky diode to be placed in parallel to the synchronous rectifier must have a reverse voltage VRRM greater than VINMAX. For this application are selected: two high side MOSFET STS11NF3LL and two STS17NF3LL for the low side section. 3.6 RSENSE selection The droop function consists to change the output voltage changing the output current; at high output current the output voltage is lower than the reference voltage. To implement the droop function, for the high current status, we use the RSENSE resistor in series to the inductor. Since inductor current can be very high, so the resistor must be capable to dissipate high power. Moreover we use the sense resistor to measure the output current for the current limit feature, so the RSENSE value must be very accurate also for temperature variation. To ensure higher temperature stability it could possible to split the RSENSE value. To achieve high efficiency also the RSENSE value must be as low as possible, so the Active voltage droop implemented in L6996 is very useful. For this application it are selected two 3mohms resistors from PANASONIC. 3.7 VP Network Design The voltage-positioning network is selected by the load regulation needed. In this application wit is considered 4mV/A; with a RSENSE resistor around 1.5mohms it can be used a gain around 2.66 and so a rate between R1 and R2 around 1.66 from the Eq6. It can be selected: R1=1.66KΩ R2=1KΩ A capacitor CVP1 is required in parallel with RVP1 to correctly compensate the network response. Its value is given by the following equation: Eq 24 1 1 C VP1 = ESRC OUT ⋅ C OUT -------------- + -------------- R R VP1 VP2 where COUT is the output capacitor value. When CVP1 is well chosen, a step decrease of output voltage should be observed, as an effect of a step load increase. Too small or too large C VP1 produces overshoot or undershoot instead of a step waveform. 20/26 L6996 With our parameter: CVP1 = 7.8pF No-load offset is obtained by RVP3 and of a current source internally connected to VFB+ pin. Thus: Eq 25 V OUT, I = 0 – V PRO G 1 R VP3 = ----------------------------------------------------- -----------------------R VP2 I O F FSET -------------- + 1 R VP1 where IOFFSET = 5µA. The capacitor CVP3 in parallel to RVP3 is a filter which time constant can be the same as in Eq22, so Eq 26 ESRC OUT ⋅ C OUT C VP3 = ------------------------------------------------R VP 3 3.8 Input divider The input divider can be selected with the Eq1, Eq2, Eq3 . Choosing a switching frequency around 270kHz it results: αOSC = 0.048. R1 = 560KΩ R2 = 27KΩ 3.9 Current limit resistor From the Eq12 it can be set the current limit resistor, for the positive current limit; it results: R10 + R11 = 120KΩ The negative current limit is set by the time available for the negative dynamic transition; a value around 30KΩ for R10 is a match between negative peak current and time to end the dynamic transition (around 80mS). R10=150KW R11=30KW 3.10 Softstart capacitor The soft start capacitor is selected once the soft start time is imposed. It can be consider a soft start time around 1ms. The soft start capacitor is given by: Eq 27 I l im ⋅ ∆T C SS = -------------------∆V s s Where ∆VSS is the soft start active range and ∆T is the soft stat time. From Eq 28 results: C SS = 10nF. 21/26 L6996 Table 3. Component List The component list is shared in two sections: the first for logic and general-purpose component, the second for power section: GENERAL PURPOSE COMPONENTS Part name Value R1, R2, R3, R4, R5, R6, R7, R9, R18, R19, R24 33kΩ 22/26 R8 47kΩ R10 120kΩ R11 30kΩ R12 1.66kΩ R13 1kΩ R15 560kΩ R16 27kΩ R20 130kΩ R21 39kΩ R22 36kΩ R23 270kΩ C1 47µF C2, C3 100nF C4 220nF C5 220nF Part number Manufacturer Notes Current limit resistors (to set the current limit) Voltage positioning resistors Input resistor divider (to set the switching frequency) IMVPII resistor network Tantalum/SP C6 10nF C7 220nF C8 6.8nF C9 47pF C10 10nF C11 47pF U2, U6, U8 Or gate U9, U7 Inverter gate NC7SZ04P5 FAIRCHILD U3,U4,U5 Nor gate NC7SZ02P5 FAIRCHILD Voltage positioning capacitor NC7SZ32M5 FAIRCHILD D1 BAT54A BAT54A PHILIPS Q5,Q6,Q7,Q8 BSS131 Q62702-S565 INFINEON SW1, SW2 DIP SWITCH *1 Logic network L6996 POWER SECTION SENSE RESISTOR Part name Value Part number Manufacturer Notes R14, R17 3mΩ ERJM1WSF3M0U PANASONIC 1% It is important, for this component, to keep in mind three factor: it must be able to dissipate high power. Again its variation with the temperature must be small and the precision must be high to ensure high precision with the ST voltage droop function. INPUT CAPACITOR Part name Value Part number Manufacturer Notes C12,C13,C14,C15,C16,C17 10µF ECJ5YB1E106M PANASONIC 25V ceramic 10µF ECJ5YF1E106M PANASONIC 25V ceramic 10µF C34Y5U1E106ZTE12 TOKIN 25V ceramic 10µF GMK325F106ZH TAIYO-YUDEN 35V ceramic 10µF TMK325F106ZH TAIYO-YUDEN 25V ceramic 10µF TMK432BJ106MM TAIYO-YUDEN 25V ceramic For this components can be useful control the temperature coefficient and the equivalent serie resistor and the voltage rated. OUTPUT CAPACITOR Part name Value Part number Manufacturer Notes C18,C19,C20,C21,C22,C23 270µF EEFUE0D271R PANASONIC 2V C18,C19,C20,C21,C22 330µF EEFUE0D271R PANASONIC 2V For this components can be useful control the temperature coefficient and the equivalent series resistor and the voltage rated. INDUCTOR Part name Value Part number Manufacturer L1 0.6µF ETQP6F0R6BFA PANASONIC 0.6µF A959AS-R60N TOKO 0.6µF CEP12D38H-0R6 SUMIDA Notes For the inductor important factors are the saturation current and the equivalent series resistor (for the efficiency improvements) POWER MOS Part name Value Part number Manufacturer Notes High side Q1, Q2 STS11NF3LL STS11F3LL STMicroelectronics STSJ25NF3LL STSJ25NF3LL STMicroelectronics Low Side Q3, Q4 STS17NH3LL STS17NH3LL STMicroelectronics Q5 N.M STS25NH3LL STS25NH3LL STMicroelectronics . Note N.M.=Not Mounted. For the MOSFET choose is important to know the input voltage and output voltage. The MOSFET must able 23/26 L6996 dissipate high power (for switching losses or conduction losses). POWER DIODES Part name Value Part number Manufacturer Notes D2 STPS2L25U STPS2L25U STMICROELECTRONICS 25V This component must have low forward voltage and must have high reverse voltage (at least equal at the input voltage). 24/26 L6996 mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.20 A1 0.05 A2 0.80 b MAX. 0.047 0.15 0.002 1.05 0.031 0.19 0.30 0.007 0.012 c 0.09 0.20 0.003 0.008 D 7.70 7.90 0.303 E E1 L1 7.80 6.40 4.30 e L 1.00 4.40 0.60 0.006 0.039 0.307 0.041 0.311 0.252 4.50 0.170 0.65 0.45 OUTLINE AND MECHANICAL DATA 0.173 0.177 0.025 0.75 0.018 1.00 0.024 0.039 0.030 TSSOP24 Thin Shrink Small Outline Package k 0˚ min., 8˚ max. 7100777 (JEDEC MO-153-AD) 25/26 L6996 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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