FDC642P P-Channel 2.5V Specified PowerTrenchTM MOSFET General Description Features This P-Channel 2.5V specified MOSFET is produced using Fairchild's advanced PowerTrench process that has been especially tailored to minimize on-state resistance and yet maintain low gate charge for superior switching performance. Fast switching speed. These devices have been designed to offer exceptional power dissipation in a very small footprint for applications where the larger packages are impractical. Low gate charge (7.2nC typical). Applications Load switch Battery protection Power management High performance trench technology for extremely low RDS(ON). SuperSOTTM-6 package: small footprint (72% smaller than standard SO-8); low profile (1mm thick). D -4 A, -20 V. RDS(ON) = 0.065 Ω @ VGS = -4.5 V RDS(ON) = 0.100 Ω @ VGS = -2.5 V S 1 6 2 5 3 4 D TM SuperSOT -6 D D G Absolute Maximum Ratings Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain Current - Continuous Drain Current - Pulsed PD TA = 25°C unless otherwise noted Power Dissipation for Single Operation TJ, Tstg Ratings Units -20 V ±8 -4 V (Note 1) (Note 1a) -20 (Note 1a) 1.6 (Note 1b) 0.8 Operating and Storage Junction Temperature Range A W -55 to +150 °C Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W Package Outlines and Ordering Information Device Marking Device Reel Size Tape Width Quantity .642 FDC642P 7’’ 8mm 3000 units 1999 Fairchild Semiconductor Corporation FDC642P, Rev. B FDC642P July 1999 Symbol TA = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA ∆BVDSS ∆TJ IDSS Breakdown Voltage Temperature Coefficient ID = -250 µA, Referenced to 25°C Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V IGSSF Gate-Body Leakage Current, Forward VGS = 8 V, VDS = 0 V 100 µA nA IGSSR Gate-Body Leakage Current, Reverse VGS = -8 V, VDS = 0 V -100 nA -1.5 V On Characteristics -20 V -16 mV/°C -1 (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA ∆VGS(th) ∆TJ RDS(on) Gate Threshold Voltage Temperature Coefficient ID = -250 µA, Referenced to 25°C 2.5 Static Drain-Source On-Resistance 0.054 0.076 0.077 ID(on) On-State Drain Current VGS = -4.5 V, ID = -4 A VGS = -4.5 V, ID = -4 A, TJ=125°C VGS = -2.5 V, ID = -3.2 A VGS = -4.5 V, VDS = -5 V gFS Forward Transconductance VDS = -5 V, ID = -4 A -0.4 -0.7 mV/°C 0.065 0.105 0.100 -10 Ω A 9 S 640 pF Dynamic Characteristics VDS = -10 V, VGS = 0 V f = 1.0 MHz Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) tf Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge 180 pF 90 pF (Note 2) VDD = -10 V, ID = -1 A VGS = -4.5 V, RGEN = 6 Ω 11 20 ns 19 30 ns Turn-Off Delay Time 26 42 ns Turn-Off Fall Time 35 55 ns 7.2 10 nC VDS = -10 V, ID = -4 A VGS = -4.5 V, 1.7 nC 1.6 nC Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.3 A (Note 2) -0.75 -1.3 A -1.2 V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 78° C/W when mounted on a 1.0 in2 pad of 2 oz. copper. b) 156° C/W when mounted on a minimum pad of 2 oz.copper. 2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0% FDC642P, Rev. B FDC642P Electrical Characteristics FDC642P Typical Characteristics 1.6 VGS = -4.5V RDS(ON), NORMALIZED -3.5V -3.0V 15 -2.5V 10 -2.0V 5 -1.5V 0 DRAIN-SOURCE ON-RESISTANCE -ID, DRAIN-SOURCE CURRENT (A) 20 VGS = -2.5V 1.4 -3.0V 1.2 -3.5V -4.0V -4.5V 1 0.8 0 1 2 3 4 5 0 4 8 Figure 1. On-Region Characteristics. 20 0.25 ID = - 4A VGS = - 4.5V 1.4 RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 16 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.5 1.3 1.2 1.1 1 0.9 0.8 ID = -2A 0.2 0.15 0.1 TA = 125oC TA = 25oC 0.05 0 0.7 -50 -25 0 25 50 75 100 125 1 150 2 3 4 5 -VGS, GATE TO SOURCE VOLTAGE (V) o TJ, JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 10 -IS, REVERSE DRAIN CURRENT (A) TA = -55oC VDS = -5V -ID, DRAIN CURRENT (A) 12 - ID, DRAIN CURRENT (A) -VDS, DRAIN-SOURCE VOLTAGE (V) 25oC 8 125oC 6 4 2 VGS = 0V 10 T = 125oC 1 25oC -55oC 0.1 0.01 0.001 0 0.4 0.8 1.2 1.6 2 -VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 2.4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDC642P, Rev. B (continued) 5 1250 f = 1 MHz VGS = 0 V VDS = -5V -10V -15V ID = -4A 4 1000 CAPACITANCE (pF) -VGS, GATE-SOURCE VOLTAGE (V) FDC642P Typical Characteristics 3 2 1 750 CISS 500 250 COSS CRSS 0 0 0 2 4 6 8 10 0 Qg, GATE CHARGE (nC) 5 10 15 20 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate-Charge Characteristics Figure 8. Capacitance Characteristics 100 5 10 10ms 100ms 1s DC 1 VGS= -4.5V SINGLE PULSE o RθJA= 156 C/W 0.1 POWER (W) 1ms TA = 25oC 3 2 1 o TA= 25 C 0.01 0 0.1 1 10 100 0.1 1 10 100 1000 SINGLE PULSE TIME (SEC) -VDS, DRAIN-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area Figure 10. Single Pulse Maximum Power Dissipation r(t), NORMALIZED EFFECTIVE 1 TRANSIENT THERMAL RESISTANCE -ID, DRAIN CURRENT (A) SINGLE PULSE RθJA = 156oC/W 4 100µs RDS(ON) LIMIT 0.5 D = 0.5 0.2 0.1 0.05 R θJA (t) = r(t) * R θJA R θJA = 156°C/W 0.2 0.1 P(pk) 0.05 t1 0.02 0.02 0.01 t2 TJ - TA = P * R θJA (t) 0.01 Duty Cycle, D = t 1 / t 2 Single Pulse 0.005 0.00001 0.0001 0.001 0.01 0.1 t1 , TIME (sec) 1 10 100 300 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient themal response will change depending on the circuit board design. FDC642P, Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. 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