STD6N52K3 STF6N52K3 N-channel 525 V, 1 Ω, 5 A, DPAK, TO-220FP SuperMESH3™ Power MOSFET Preliminary Data Features Type RDS(on) max VDSS ID Pw STD6N52K3 525 V < 1.2 Ω 5A 70 W STF6N52K3 525 V < 1.2 Ω 5 A(1) 25 W 3 3 1. Limited by package 1 2 TO-220FP ■ 100% avalanche tested ■ Extremely high dv/dt capability ■ Gate charge minimized ■ Very low intrinsic capacitances ■ Improved diode reverse recovery characteristics ■ Zener-protected Figure 1. 1 DPAK Internal schematic diagram Application ■ Switching applications Description The new SuperMESH3™ series is obtained through the combination of a further fine tuning of ST's well established strip-based PowerMESH™ layout with a new optimization of the vertical structure. In addition to reducing on-resistance significantly versus previous generation, special attention has been taken to ensure a very good dv/dt capability and higher margin in breakdown voltage for the most demanding application. Table 1. Device summary Order codes Marking Package Packaging STD6N52K3 6N52K3 DPAK Tape and reel STF6N52K3 6N52K3 TO-220FP Tube September 2008 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/12 www.st.com 12 Contents STD6N52K3 - STF6N52K3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 .............................................. 6 STD6N52K3 - STF6N52K3 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Value Symbol Parameter Unit DPAK TO-220FP VDS Drain-source voltage (VGS = 0) 525 V VGS Gate- source voltage ± 30 V Drain current (continuous) at TC = 25 °C ID Drain current (continuous) at TC = 100 °C ID IDM (2) PTOT dv/dt 3.15 3.15 A Total dissipation at TC = 25 °C 70 25 W 0.56 0.2 W/°C Peak diode recovery voltage slope Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) Tstg Storage temperature 20 (1) A 20 VISO Tj (1) Drain current (pulsed) Derating factor (3) 5 (1) 5 9 V/ns -- Max. operating junction temperature A 2500 V -55 to 150 °C 150 °C 1. Limited by package 2. Pulse width limited by safe operating area 3. ISD ≤ 6.3 A, di/dt = TBD, VDD = 80% V(BR)DSS. Table 3. Symbol Thermal data Parameter DPAK TO-220FP Unit Rthj-case Thermal resistance junction-case max 1.79 5 °C/W Rthj-pcb Thermal resistance junction-pcb max 50 -- °C/W Rthj-amb Thermal resistance junction-ambient max -- 62.5 °C/W Tl Maximum lead temperature for soldering purpose Table 4. 300 °C Avalanche characteristics Symbol Parameter Max value Unit IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) TBD A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR, VDD = 50V) TBD mJ 3/12 Electrical characteristics 2 STD6N52K3 - STF6N52K3 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. Symbol V(BR)DSS On /off states Parameter Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 IDSS VDS = Max rating Zero gate voltage drain current (VGS = 0) VDS = Max rating, TC=125 °C IGSS Gate-body leakage current (VDS = 0) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on Static drain-source on resistance Symbol gfs (1) Typ. Max. Unit 525 V 1 50 µA µA ± 10 µA 3.75 4.5 V 1.0 1.2 Ω Typ. Max. Unit VGS = ± 30 V VGS(th) Table 6. Min. 3 VGS = 10 V, ID = 2.5 A Dynamic Parameter Forward transconductance Test conditions Min. VDS = 15 V, ID = 2.5 A TBD S Input capacitance Output capacitance Reverse transfer capacitance VDS = 50 V, f = 1 MHz, VGS = 0 TBD TBD TBD pF pF pF Equivalent output capacitance VGS = 0, VDS = 0 to 240 V TBD pF RG Intrinsic gate resistance f = 1 MHz open drain TBD Ω Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 240 V, ID = 5 A, VGS = 10 V (see Figure 3) TBD TBD TBD nC nC nC Ciss Coss Crss COSS eq(1) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7. Symbol td(on) tr td(off) tf 4/12 Switching times Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 150 V, ID = 3.15 A, RG = 4.7 Ω, VGS = 10 V (see Figure 2) Min. Typ. TBD TBD TBD TBD Max Unit ns ns ns ns STD6N52K3 - STF6N52K3 Table 8. Electrical characteristics Source drain diode Symbol Parameter ISD ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD = 5 A, VGS = 0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 5 A, di/dt = 100 A/µs VDD = 60 V (see Figure 7) TBD TBD TBD ns nC A Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 5 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 7) TBD TBD TBD ns nC A trr Qrr IRRM trr Qrr IRRM Test conditions Min. Typ. Max. Unit 6.3 25 A A 1.6 V 1. Pulse width limited by safe operating area 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% Table 9. Symbol BVGSO(1) Gate-source Zener diode Parameter Gate-source breakdown voltage Test conditions Igs=± 1 mA (open drain) Min Typ Max Unit 30 V 1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components 5/12 Test circuits STD6N52K3 - STF6N52K3 3 Test circuits Figure 2. Switching times test circuit for resistive load Figure 4. Test circuit for inductive load Figure 5. switching and diode recovery times Unclamped Inductive load test circuit Figure 6. Unclamped inductive waveform Switching time waveform 6/12 Figure 3. Figure 7. Gate charge test circuit STD6N52K3 - STF6N52K3 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 7/12 Package mechanical data STD6N52K3 - STF6N52K3 TO-220FP mechanical data mm. Dim. Min. A 4.40 inch Typ Max. Min. 4.60 0.173 Typ. 0.181 Max. B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.70 0.017 0.027 F 0.75 1.00 0.030 0.039 F1 1.15 1.50 0.045 0.067 F2 1.15 1.50 0.045 0.067 G 4.95 5.20 0.195 0.204 G1 2.40 2.70 0.094 0.106 H 10 10.40 0.393 L2 16 0.409 0.630 28.6 30.6 1.126 L4 9.80 10.60 0.385 1.204 0.417 L5 2.9 3.6 0.114 0.141 L6 15.90 16.40 0.626 0.645 L7 9 9.30 0.354 0.366 Dia 3 3.2 0.118 0.126 B D A E L3 L3 L6 F2 H G G1 Dia F F1 L7 L2 L5 1 2 3 L4 7012510-I 8/12 STD6N52K3 - STF6N52K3 Package mechanical data TO-252 (DPAK) mechanical data DIM. mm. min. typ max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 D1 E 6.20 5.10 6.40 E1 6.60 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1 L1 2.80 L2 L4 0.80 0.60 R V2 1 0.20 0o 8o 0068772_G 9/12 Package mechanical data 5 STD6N52K3 - STF6N52K3 Package mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA DIM. mm MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 B1 D 10/12 inch 1.5 D1 1.5 E 1.65 MIN. MAX. 12.1 0.476 1.6 0.059 0.063 1.85 0.065 0.073 0.059 F 7.4 7.6 0.291 0.299 K0 2.55 2.75 0.100 0.108 0.153 0.161 P0 3.9 4.1 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 R 40 W 15.7 1.574 16.3 0.618 0.641 inch MAX. MIN. MAX. 330 12.992 13.2 0.504 0.520 18.4 0.645 0.724 0.059 0.795 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 STD6N52K3 - STF6N52K3 6 Revision history Revision history Table 10. Document revision history Date Revision 03-Sep-2008 1 Changes Initial release 11/12 STD6N52K3 - STF6N52K3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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