STP5N120 N-channel 1200V - 2.8Ω - 4.4A - TO-220 Zener - protected SuperMESH™ Power MOSFET TARGET SPECIFICATION Features Type VDSS RDS(on) ID PW STP5N120 1200V < 3.5 Ω 4.4A 160W ■ 100% avalanche tested ■ Extremely high dv/dt capability ■ ESD improved capability ■ New high voltage benchmark ■ Gate charge minimized 3 1 2 TO-220 Description The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage Power MOSFETs. Internal schematic diagram Application ■ Switching application Order code Part number Marking Package Packaging STP5N120 5N120 TO-220 Tube May 2007 Rev 1 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. 1/10 www.st.com 10 Contents STP5N120 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2/10 ................................................ 6 STP5N120 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage (VGS=0) 1200 V VGS Gate-source voltage ± 30 V ID Drain current (continuous) at TC = 25°C 4.4 A ID Drain current (continuous) at TC = 100°C 2.772 A Drain current (pulsed) 17.6 A Derating factor 1.28 W/°C Total dissipation at TC = 25°C 160 W VESD(G-S) Gate source ESD (HBM-C = 100pF, R= 1.5KΩ) 3000 V dv/dt (2) Peak diode recovery voltage slope 4.5 V/ns -55 to 150 °C Value Unit Thermal resistance junction-case max 0.78 °C/W Rthj-amb (1) Thermal resistance junction-amb max 62.5 °C/W 300 °C IDM (1) PTOT Tj Tstg Operating junction temperature Storage temperature 1. Pulse width limited by safe operating area 2. ISD ≤4.4A, di/dt ≤200A/µs, VDD ≤80% V(BR)DSS Table 2. Symbol Rthj-case Tl Thermal data Parameter Maximum lead temperature for soldering purpose 1. When mounted on 1inch² FR-4 board, 2 oz Cu Table 3. Avalanche characteristics Symbol Parameter Max value Unit IAS Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 4.4 A EAS Single pulse avalanche energy (starting Tj=25°C, ID=IAS, VDD= 50V) Tbd mJ 3/10 Electrical characteristics 2 STP5N120 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol V(BR)DSS On/off states Parameter Drain-source breakdown voltage Test conditions ID = 1mA, VGS= 0 Min. Typ. Max. 1200 Unit V VDS = Max rating, VDS = Max rating,Tc=125°C 1 50 µA µA Gate body leakage current (VDS = 0) VGS = ± 30V ±10 µA VGS(th) Gate threshold voltage VDS= VGS, ID = 100µA 3.75 4.5 V RDS(on) Static drain-source on resistance VGS= 10V, ID= 2.3A 2.8 3.5 Ω Typ. Max. Unit IDSS Zero gate voltage drain current (VGS = 0) IGSS Table 5. Symbol 3 Dynamic Parameter Test conditions Min. gfs(1) Forward transconductance VDS = 15V, ID = 2.3A Tbd S Ciss Input capacitance Output capacitance Reverse transfer capacitance VDS =25V, f=1MHz, VGS=0 120 115 25 pF pF pF Equivalent output capacitance VGS = 0V, VDS = 0V to 800V 50 pF RG Intrinsic gate resistance f = 1MHz open drain Tbd Ω Qg Total gate charge Gate-source charge Gate-drain charge VDD=960V, ID = 4.4A 55 8 22 nC nC nC Coss Crss Coss eq.(2) Qgs Qgd VGS =10V (see Figure 2) 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/10 STP5N120 Electrical characteristics Table 6. Symbol td(on) tr td(off) tf Table 7. Symbol ISD ISDM VSD(1) trr Qrr IRRM trr Qrr IRRM 1. Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit Tbd Tbd Tbd Tbd VDD = 600V, ID = 2.2A, RG=4.7Ω, VGS=10V (see Figure 4) ns ns ns ns Source drain diode Parameter Test conditions Min Typ. Source-drain current Source-drain current (pulsed) Forward on voltage ISD= 4.4A, VGS=0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 4.4A, VDD=100V Reverse recovery time Reverse recovery charge Reverse recovery current di/dt = 50A/µs,Tj=25°C (see Figure 3) ISD= 4.4A,VDD=100V di/dt=50A/µs,Tj=150°C (see Figure 3) Max Unit 4.4 17.6 mA A 1.6 V Tbd Tbd Tbd ns µC A Tbd Tbd Tbd ns µC A Pulsed: pulse duration = 300µs, duty cycle 1.5% Table 8. Symbol Gate-source zener diode Parameter Test conditions BVGSO (1) Gate-source breakdown voltage Igs ± 1mA, (open drain) Min Typ. Max Unit 30 V 1. The built-in-back zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated zener diodes thus avoid the usage of external components. 5/10 Test circuit STP5N120 3 Test circuit Figure 1. Switching times test circuit for resistive load Figure 3. Test circuit for inductive load Figure 4. switching and diode recovery times Unclamped inductive load test circuit Figure 5. Unclamped inductive waveform Switching time waveform 6/10 Figure 2. Figure 6. Gate charge test circuit STP5N120 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 7/10 Package mechanical data STP5N120 TO-220 mechanical data mm inch Dim Min A b b1 c D D1 E e e1 F H1 J1 L L1 L20 L30 ∅P Q 8/10 Typ 4.40 0.61 1.14 0.49 15.25 Max Min 4.60 0.88 1.70 0.70 15.75 0.173 0.024 0.044 0.019 0.6 10.40 2.70 5.15 1.32 6.60 2.72 14 3.93 0.393 0.094 0.194 0.048 0.244 0.094 0.511 0.137 1.27 10 2.40 4.95 1.23 6.20 2.40 13 3.50 Max 0.181 0.034 0.066 0.027 0.62 0.050 16.40 28.90 3.75 2.65 Typ 0.409 0.106 0.202 0.051 0.256 0.107 0.551 0.154 0.645 1.137 3.85 2.95 0.147 0.104 0.151 0.116 STP5N120 5 Revision history Revision history Table 9. Revision history Date Revision 21-May-2007 1 Changes First release 9/10 STP5N120 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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